Adapt layers and tolerances to correspond with four layer qualities.

hardware/dscomm.pro

@@ -1,4 +1,4 @@
-update=So 06 Sep 2020 04:18:15 CEST
+update=Sa 19 Sep 2020 12:37:47 CEST
 version=1
 last_client=kicad
 [general]
@@ -26,41 +26,43 @@ ERC_TestSimilarLabels=1
 version=1
 PageLayoutDescrFile=elabdev-black.kicad_wks
 LastNetListRead=dscomm.net
-CopperLayerCount=2
+CopperLayerCount=4
 BoardThickness=1.6
 AllowMicroVias=0
 AllowBlindVias=0
 RequireCourtyardDefinitions=0
 ProhibitOverlappingCourtyards=1
 MinTrackWidth=0.09
-MinViaDiameter=0.4
+MinViaDiameter=0.45
 MinViaDrill=0.2
-MinMicroViaDiameter=0.2
+MinMicroViaDiameter=0.45
 MinMicroViaDrill=0.09999999999999999
 MinHoleToHole=0.25
-TrackWidth1=0.09
-TrackWidth2=0.1016
+TrackWidth1=0.2
+TrackWidth2=0.09
 TrackWidth3=0.127
-ViaDiameter1=0.4
-ViaDrill1=0.2
+ViaDiameter1=0.9
+ViaDrill1=0.6
 ViaDiameter2=0.45
-ViaDrill2=0.3
+ViaDrill2=0.2
+ViaDiameter3=0.6
+ViaDrill3=0.3
 dPairWidth1=0.2
 dPairGap1=0.25
 dPairViaGap1=0.25
-SilkLineWidth=0.12
+SilkLineWidth=0.15
 SilkTextSizeV=1
 SilkTextSizeH=1
 SilkTextSizeThickness=0.15
 SilkTextItalic=0
 SilkTextUpright=1
-CopperLineWidth=0.2
-CopperTextSizeV=1.5
-CopperTextSizeH=1.5
-CopperTextThickness=0.3
+CopperLineWidth=0.09999999999999999
+CopperTextSizeV=1
+CopperTextSizeH=1
+CopperTextThickness=0.25
 CopperTextItalic=0
 CopperTextUpright=1
-EdgeCutLineWidth=0.05
+EdgeCutLineWidth=0.09999999999999999
 CourtyardLineWidth=0.05
 OthersLineWidth=0.15
 OthersTextSizeV=1
@@ -68,8 +70,8 @@ OthersTextSizeH=1
 OthersTextSizeThickness=0.15
 OthersTextItalic=0
 OthersTextUpright=1
-SolderMaskClearance=0.051
-SolderMaskMinWidth=0.25
+SolderMaskClearance=0
+SolderMaskMinWidth=0
 SolderPasteClearance=0
 SolderPasteRatio=-0
 [pcbnew/Layer.F.Cu]
@@ -79,11 +81,11 @@ Enabled=1
 [pcbnew/Layer.In1.Cu]
 Name=In1.Cu
 Type=0
-Enabled=0
+Enabled=1
 [pcbnew/Layer.In2.Cu]
 Name=In2.Cu
 Type=0
-Enabled=0
+Enabled=1
 [pcbnew/Layer.In3.Cu]
 Name=In3.Cu
 Type=0
@@ -201,9 +203,9 @@ Name=B.Cu
 Type=0
 Enabled=1
 [pcbnew/Layer.B.Adhes]
-Enabled=1
+Enabled=0
 [pcbnew/Layer.F.Adhes]
-Enabled=1
+Enabled=0
 [pcbnew/Layer.B.Paste]
 Enabled=1
 [pcbnew/Layer.F.Paste]
@@ -221,9 +223,9 @@ Enabled=1
 [pcbnew/Layer.Cmts.User]
 Enabled=1
 [pcbnew/Layer.Eco1.User]
-Enabled=1
+Enabled=0
 [pcbnew/Layer.Eco2.User]
-Enabled=1
+Enabled=0
 [pcbnew/Layer.Edge.Cuts]
 Enabled=1
 [pcbnew/Layer.Margin]
@@ -241,11 +243,22 @@ Enabled=0
 [pcbnew/Netclasses]
 [pcbnew/Netclasses/Default]
 Name=Default
-Clearance=0.09
-TrackWidth=0.09
-ViaDiameter=0.4
-ViaDrill=0.2
-uViaDiameter=0.3
+Clearance=0.2
+TrackWidth=0.2
+ViaDiameter=0.9
+ViaDrill=0.6
+uViaDiameter=0.5
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/1]
+Name=Power
+Clearance=0.2
+TrackWidth=0.5
+ViaDiameter=1
+ViaDrill=0.7
+uViaDiameter=0.5
 uViaDrill=0.1
 dPairWidth=0.2
 dPairGap=0.25