Import project samples to illustrate hardware features in ARM firmware;

This addition resolves #111 and #112 and concludes milestone group 6.

firmware/SendcommCmdsys/SendcommCmdsys.componentinfo.xml

@@ -0,0 +1,4 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
+	<ProjectComponents />
+</Store>

firmware/SendcommCmdsys/src/ASF/common/boards/board.h

@@ -0,0 +1,456 @@
+/**
+ * \file
+ *
+ * \brief Standard board header file.
+ *
+ * This file includes the appropriate board header file according to the
+ * defined board (parameter BOARD).
+ *
+ * Copyright (c) 2009-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/**
+ * \defgroup group_common_boards Generic board support
+ *
+ * The generic board support module includes board-specific definitions
+ * and function prototypes, such as the board initialization function.
+ *
+ * \{
+ */
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*! \name Base Boards
+ */
+//! @{
+#define EVK1100                     1  //!< AT32UC3A EVK1100 board.
+#define EVK1101                     2  //!< AT32UC3B EVK1101 board.
+#define UC3C_EK                     3  //!< AT32UC3C UC3C-EK board.
+#define EVK1104                     4  //!< AT32UC3A3 EVK1104 board.
+#define EVK1105                     5  //!< AT32UC3A EVK1105 board.
+#define STK600_RCUC3L0              6  //!< STK600 RCUC3L0 board.
+#define UC3L_EK                     7  //!< AT32UC3L-EK board.
+#define XPLAIN                      8  //!< ATxmega128A1 Xplain board.
+#define STK600_RC064X              10  //!< ATxmega256A3 STK600 board.
+#define STK600_RC100X              11  //!< ATxmega128A1 STK600 board.
+#define UC3_A3_XPLAINED            13  //!< ATUC3A3 UC3-A3 Xplained board.
+#define UC3_L0_XPLAINED            15  //!< ATUC3L0 UC3-L0 Xplained board.
+#define STK600_RCUC3D              16  //!< STK600 RCUC3D board.
+#define STK600_RCUC3C0             17  //!< STK600 RCUC3C board.
+#define XMEGA_B1_XPLAINED          18  //!< ATxmega128B1 Xplained board.
+#define XMEGA_A1_XPLAINED          19  //!< ATxmega128A1 Xplain-A1 board.
+#define XMEGA_A1U_XPLAINED_PRO     20  //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
+#define STK600_RCUC3L4             21  //!< ATUCL4 STK600 board.
+#define UC3_L0_XPLAINED_BC         22  //!< ATUC3L0 UC3-L0 Xplained board controller board.
+#define MEGA1284P_XPLAINED_BC      23  //!< ATmega1284P-Xplained board controller board.
+#define STK600_RC044X              24  //!< STK600 with RC044X routing card board.
+#define STK600_RCUC3B0             25  //!< STK600 RCUC3B0 board.
+#define UC3_L0_QT600               26  //!< QT600 UC3L0 MCU board.
+#define XMEGA_A3BU_XPLAINED        27  //!< ATxmega256A3BU Xplained board.
+#define STK600_RC064X_LCDX         28  //!< XMEGAB3 STK600 RC064X LCDX board.
+#define STK600_RC100X_LCDX         29  //!< XMEGAB1 STK600 RC100X LCDX board.
+#define UC3B_BOARD_CONTROLLER      30  //!< AT32UC3B1 board controller for Atmel boards.
+#define RZ600                      31  //!< AT32UC3A RZ600 MCU board.
+#define SAM3S_EK                   32  //!< SAM3S-EK board.
+#define SAM3U_EK                   33  //!< SAM3U-EK board.
+#define SAM3X_EK                   34  //!< SAM3X-EK board.
+#define SAM3N_EK                   35  //!< SAM3N-EK board.
+#define SAM3S_EK2                  36  //!< SAM3S-EK2 board.
+#define SAM4S_EK                   37  //!< SAM4S-EK board.
+#define STK600_RCUC3A0             38  //!< STK600 RCUC3A0 board.
+#define STK600_MEGA                39  //!< STK600 MEGA board.
+#define MEGA_1284P_XPLAINED        40  //!< ATmega1284P Xplained board.
+#define SAM4S_XPLAINED             41  //!< SAM4S Xplained board.
+#define ATXMEGA128A1_QT600         42  //!< QT600 ATXMEGA128A1 MCU board.
+#define ARDUINO_DUE_X              43  //!< Arduino Due/X board.
+#define STK600_RCUC3L3             44  //!< ATUCL3 STK600 board.
+#define SAM4L_EK                   45  //!< SAM4L-EK board.
+#define STK600_MEGA_RF             46  //!< STK600 MEGA RF EVK board.
+#define XMEGA_C3_XPLAINED          47  //!< ATxmega384C3 Xplained board.
+#define STK600_RC032X              48  //!< STK600 with RC032X routing card board.
+#define SAM4S_EK2                  49  //!< SAM4S-EK2 board.
+#define XMEGA_E5_XPLAINED          50  //!< ATxmega32E5 Xplained board.
+#define SAM4E_EK                   51  //!< SAM4E-EK board.
+#define ATMEGA256RFR2_XPLAINED_PRO 52  //!< ATmega256RFR2 Xplained Pro board.
+#define SAM4S_XPLAINED_PRO         53  //!< SAM4S Xplained Pro board.
+#define SAM4L_XPLAINED_PRO         54  //!< SAM4L Xplained Pro board.
+#define ATMEGA256RFR2_ZIGBIT       55  //!< ATmega256RFR2 zigbit.
+#define XMEGA_RF233_ZIGBIT         56  //!< ATxmega256A3U with AT86RF233 Zigbit.
+#define XMEGA_RF212B_ZIGBIT        57  //!< ATxmega256A3U with AT86RF212B Zigbit.
+#define SAM4S_WPIR_RD              58  //!< SAM4S-WPIR-RD board.
+#define SAMD20_XPLAINED_PRO        59  //!< SAM D20 Xplained Pro board.
+#define SAM4L8_XPLAINED_PRO        60  //!< SAM4L8 Xplained Pro board.
+#define SAM4N_XPLAINED_PRO         61  //!< SAM4N Xplained Pro board.
+#define XMEGA_A3_REB_CBB           62  //!< XMEGA REB Controller Base board.
+#define ATMEGARFX_RCB              63  //!< RFR2 & RFA1 RCB.
+#define SAM4C_EK                   64  //!< SAM4C-EK board.
+#define RCB256RFR2_XPRO            65  //!< RFR2 RCB Xplained Pro board.
+#define SAMG53_XPLAINED_PRO        66  //!< SAMG53 Xplained Pro board.
+#define SAM4CP16BMB                67  //!< SAM4CP16BMB board.
+#define SAM4E_XPLAINED_PRO         68  //!< SAM4E Xplained Pro board.
+#define SAMD21_XPLAINED_PRO        69  //!< SAM D21 Xplained Pro board.
+#define SAMR21_XPLAINED_PRO        70  //!< SAM R21 Xplained Pro board.
+#define SAM4CMP_DB                 71  //!< SAM4CMP demo board.
+#define SAM4CMS_DB                 72  //!< SAM4CMS demo board.
+#define ATPL230AMB                 73  //!< ATPL230AMB board.
+#define SAMD11_XPLAINED_PRO        74  //!< SAM D11 Xplained Pro board.
+#define SAMG55_XPLAINED_PRO        75  //!< SAMG55 Xplained Pro board.
+#define SAML21_XPLAINED_PRO        76  //!< SAM L21 Xplained Pro board.
+#define SAMD10_XPLAINED_MINI       77  //!< SAM D10 Xplained Mini board.
+#define SAMDA1_XPLAINED_PRO        78  //!< SAM DA1 Xplained Pro board.
+#define SAMW25_XPLAINED_PRO        79  //!< SAMW25 Xplained Pro board.
+#define SAMC21_XPLAINED_PRO        80  //!< SAM C21 Xplained Pro board.
+#define SAMV71_XPLAINED_ULTRA      81  //!< SAMV71 Xplained Ultra board.
+#define ATMEGA328P_XPLAINED_MINI   82  //!< ATMEGA328P Xplained MINI board.
+#define ATMEGA328PB_XPLAINED_MINI  83  //!< ATMEGA328PB Xplained MINI board.
+#define SAMB11_XPLAINED_PRO        84  //!< SAM B11 Xplained Pro board.
+#define SAME70_XPLAINED            85  //!< SAME70 Xplained board.
+#define SAML22_XPLAINED_PRO        86  //!< SAM L22 Xplained Pro board.
+#define SAML22_XPLAINED_PRO_B      87  //!< SAM L22 Xplained Pro board.
+#define SAMR21ZLL_EK               88  //!< SAMR21ZLL-EK board.
+#define ATMEGA168PB_XPLAINED_MINI  89  //!< ATMEGA168PB Xplained MINI board.
+#define ATMEGA324PB_XPLAINED_PRO   90  //!< ATMEGA324PB Xplained Pro board.
+#define SAMB11ZR_XPLAINED_PRO      92  //!< SAM B11 ZR Xplained Pro board.
+#define SAMR30_XPLAINED_PRO        93  //!< SAM R30 Xplained Pro board.
+#define SAMHA1G16A_XPLAINED_PRO    94  //!< SAM HA1G16A Xplained Pro board.
+#define SAMR34_XPLAINED_PRO        95  //!< SAM R34 Xplained Pro board.
+#define SIMULATOR_XMEGA_A1         97  //!< Simulator for XMEGA A1 devices.
+#define AVR_SIMULATOR_UC3          98  //!< Simulator for the AVR UC3 device family.
+#define USER_BOARD                 99  //!< User-reserved board (if any).
+#define DUMMY_BOARD                100 //!< Dummy board to support board-independent applications (e.g. bootloader).
+#define SAMB11ZR_SENSOR_TAG        101 //!< SAMB11ZR sensor tag board
+#define SAMR30_MODULE_XPLAINED_PRO 102 //!< SAM R30 Module Xplained Pro board.
+#define SAMR21G18_MODULE           103 //!< SAMR21G18-MR210UA Module.
+#define SAMR21B18_MODULE           104 //!< SAMR21B18-MZ210PA Module.
+#define WLR089_XPLAINED_PRO        105 //!< WLR089_XPLAINED_PRO board.
+#define SAMR34_SENDCOMM            123 //!< SAMR34 Sendcomm board.
+//! @}
+
+/*! \name Extension Boards
+ */
+//! @{
+#define EXT1102                      1  //!< AT32UC3B EXT1102 board
+#define MC300                        2  //!< AT32UC3 MC300 board
+#define SENSORS_XPLAINED_INERTIAL_1  3  //!< Xplained inertial sensor board 1
+#define SENSORS_XPLAINED_INERTIAL_2  4  //!< Xplained inertial sensor board 2
+#define SENSORS_XPLAINED_PRESSURE_1  5  //!< Xplained pressure sensor board
+#define SENSORS_XPLAINED_LIGHTPROX_1 6  //!< Xplained light & proximity sensor board
+#define SENSORS_XPLAINED_INERTIAL_A1 7  //!< Xplained inertial sensor board "A"
+#define RZ600_AT86RF231              8  //!< AT86RF231 RF board in RZ600
+#define RZ600_AT86RF230B             9  //!< AT86RF230B RF board in RZ600
+#define RZ600_AT86RF212             10  //!< AT86RF212 RF board in RZ600
+#define SENSORS_XPLAINED_BREADBOARD 11  //!< Xplained sensor development breadboard
+#define SECURITY_XPLAINED           12  //!< Xplained ATSHA204 board
+#define USER_EXT_BOARD              99  //!< User-reserved extension board (if any).
+//! @}
+
+#if BOARD == EVK1100
+#  include "evk1100/evk1100.h"
+#elif BOARD == EVK1101
+#  include "evk1101/evk1101.h"
+#elif BOARD == UC3C_EK
+#  include "uc3c_ek/uc3c_ek.h"
+#elif BOARD == EVK1104
+#  include "evk1104/evk1104.h"
+#elif BOARD == EVK1105
+#  include "evk1105/evk1105.h"
+#elif BOARD == STK600_RCUC3L0
+#  include "stk600/rcuc3l0/stk600_rcuc3l0.h"
+#elif BOARD == UC3L_EK
+#  include "uc3l_ek/uc3l_ek.h"
+#elif BOARD == STK600_RCUC3L4
+#  include "stk600/rcuc3l4/stk600_rcuc3l4.h"
+#elif BOARD == XPLAIN
+#  include "xplain/xplain.h"
+#elif BOARD == STK600_MEGA
+  /*No header-file to include*/
+#elif BOARD == STK600_MEGA_RF
+#  include "stk600.h"
+#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
+#  include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
+#elif BOARD == ATMEGA256RFR2_ZIGBIT
+#  include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
+#elif BOARD == STK600_RC032X
+#  include "stk600/rc032x/stk600_rc032x.h"
+#elif BOARD == STK600_RC044X
+#  include "stk600/rc044x/stk600_rc044x.h"
+#elif BOARD == STK600_RC064X
+#  include "stk600/rc064x/stk600_rc064x.h"
+#elif BOARD == STK600_RC100X
+#  include "stk600/rc100x/stk600_rc100x.h"
+#elif BOARD == UC3_A3_XPLAINED
+#  include "uc3_a3_xplained/uc3_a3_xplained.h"
+#elif BOARD == UC3_L0_XPLAINED
+#  include "uc3_l0_xplained/uc3_l0_xplained.h"
+#elif BOARD == STK600_RCUC3B0
+#  include "stk600/rcuc3b0/stk600_rcuc3b0.h"
+#elif BOARD == STK600_RCUC3D
+#  include "stk600/rcuc3d/stk600_rcuc3d.h"
+#elif BOARD == STK600_RCUC3C0
+#  include "stk600/rcuc3c0/stk600_rcuc3c0.h"
+#elif BOARD == SAMG53_XPLAINED_PRO
+#  include "samg53_xplained_pro/samg53_xplained_pro.h"
+#elif BOARD == SAMG55_XPLAINED_PRO
+#  include "samg55_xplained_pro/samg55_xplained_pro.h"
+#elif BOARD == XMEGA_B1_XPLAINED
+#  include "xmega_b1_xplained/xmega_b1_xplained.h"
+#elif BOARD == STK600_RC064X_LCDX
+#  include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
+#elif BOARD == STK600_RC100X_LCDX
+#  include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
+#elif BOARD == XMEGA_A1_XPLAINED
+#  include "xmega_a1_xplained/xmega_a1_xplained.h"
+#elif BOARD == XMEGA_A1U_XPLAINED_PRO
+#  include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
+#elif BOARD == UC3_L0_XPLAINED_BC
+#  include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
+#elif BOARD == SAM3S_EK
+#  include "sam3s_ek/sam3s_ek.h"
+#  include "system_sam3s.h"
+#elif BOARD == SAM3S_EK2
+#  include "sam3s_ek2/sam3s_ek2.h"
+#  include "system_sam3sd8.h"
+#elif BOARD == SAM3U_EK
+#  include "sam3u_ek/sam3u_ek.h"
+#  include "system_sam3u.h"
+#elif BOARD == SAM3X_EK
+#  include "sam3x_ek/sam3x_ek.h"
+#  include "system_sam3x.h"
+#elif BOARD == SAM3N_EK
+#  include "sam3n_ek/sam3n_ek.h"
+#  include "system_sam3n.h"
+#elif BOARD == SAM4S_EK
+#  include "sam4s_ek/sam4s_ek.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_WPIR_RD
+#  include "sam4s_wpir_rd/sam4s_wpir_rd.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_XPLAINED
+#  include "sam4s_xplained/sam4s_xplained.h"
+#  include "system_sam4s.h"
+#elif BOARD == SAM4S_EK2
+#  include "sam4s_ek2/sam4s_ek2.h"
+#  include "system_sam4s.h"
+#elif BOARD == MEGA_1284P_XPLAINED
+  /*No header-file to include*/
+#elif BOARD == ARDUINO_DUE_X
+#  include "arduino_due_x/arduino_due_x.h"
+#  include "system_sam3x.h"
+#elif BOARD == SAM4L_EK
+#  include "sam4l_ek/sam4l_ek.h"
+#elif BOARD == SAM4E_EK
+#  include "sam4e_ek/sam4e_ek.h"
+#elif BOARD == SAMD20_XPLAINED_PRO
+#  include "samd20_xplained_pro/samd20_xplained_pro.h"
+#elif BOARD == SAMD21_XPLAINED_PRO
+#  include "samd21_xplained_pro/samd21_xplained_pro.h"
+#elif BOARD == SAMR21_XPLAINED_PRO
+#  include "samr21_xplained_pro/samr21_xplained_pro.h"
+#elif BOARD == SAMR30_XPLAINED_PRO && defined(__SAMR30G18A__)
+#  include "samr30_xplained_pro/samr30_xplained_pro.h"
+#elif BOARD == SAMR30_MODULE_XPLAINED_PRO && defined(__SAMR30E18A__)
+#  include "samr30_module_xplained_pro/samr30_module_xplained_pro.h"
+#elif BOARD == SAMR21ZLL_EK
+#  include "samr21zll_ek/samr21zll_ek.h"
+#elif BOARD == SAMD11_XPLAINED_PRO
+#  include "samd11_xplained_pro/samd11_xplained_pro.h"
+#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__)
+#  include "saml21_xplained_pro/saml21_xplained_pro.h"
+#elif BOARD == SAML22_XPLAINED_PRO
+#  include "saml22_xplained_pro/saml22_xplained_pro.h"
+#elif BOARD == SAML22_XPLAINED_PRO_B
+#  include "saml22_xplained_pro_b/saml22_xplained_pro_b.h"
+#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__)
+#  include "saml21_xplained_pro_b/saml21_xplained_pro.h"
+#elif BOARD == SAMD10_XPLAINED_MINI
+#  include "samd10_xplained_mini/samd10_xplained_mini.h"
+#elif BOARD == SAMDA1_XPLAINED_PRO
+#  include "samda1_xplained_pro/samda1_xplained_pro.h"
+#elif BOARD == SAMHA1G16A_XPLAINED_PRO
+#  include "samha1g16a_xplained_pro/samha1g16a_xplained_pro.h"
+#elif BOARD == SAMC21_XPLAINED_PRO
+#  include "samc21_xplained_pro/samc21_xplained_pro.h"
+#elif BOARD == SAM4N_XPLAINED_PRO
+#  include "sam4n_xplained_pro/sam4n_xplained_pro.h"
+#elif BOARD == SAMW25_XPLAINED_PRO
+#  include "samw25_xplained_pro/samw25_xplained_pro.h"
+#elif BOARD == SAMV71_XPLAINED_ULTRA
+#  include "samv71_xplained_ultra/samv71_xplained_ultra.h"
+#elif BOARD == MEGA1284P_XPLAINED_BC
+#  include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
+#elif BOARD == UC3_L0_QT600
+#  include "uc3_l0_qt600/uc3_l0_qt600.h"
+#elif BOARD == XMEGA_A3BU_XPLAINED
+#  include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
+#elif BOARD == XMEGA_E5_XPLAINED
+#  include "xmega_e5_xplained/xmega_e5_xplained.h"
+#elif BOARD == UC3B_BOARD_CONTROLLER
+#  include "uc3b_board_controller/uc3b_board_controller.h"
+#elif BOARD == RZ600
+#  include "rz600/rz600.h"
+#elif BOARD == STK600_RCUC3A0
+#  include "stk600/rcuc3a0/stk600_rcuc3a0.h"
+#elif BOARD == ATXMEGA128A1_QT600
+#  include "atxmega128a1_qt600/atxmega128a1_qt600.h"
+#elif BOARD == STK600_RCUC3L3
+#  include "stk600/rcuc3l3/stk600_rcuc3l3.h"
+#elif BOARD == SAM4S_XPLAINED_PRO
+#  include "sam4s_xplained_pro/sam4s_xplained_pro.h"
+#elif BOARD == SAM4L_XPLAINED_PRO
+#  include "sam4l_xplained_pro/sam4l_xplained_pro.h"
+#elif BOARD == SAM4L8_XPLAINED_PRO
+#  include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
+#elif BOARD == SAM4C_EK
+#  include "sam4c_ek/sam4c_ek.h"
+#elif BOARD == SAM4CMP_DB
+#  include "sam4cmp_db/sam4cmp_db.h"
+#elif BOARD == SAM4CMS_DB
+#  include "sam4cms_db/sam4cms_db.h"
+#elif BOARD == SAM4CP16BMB
+#  include "sam4cp16bmb/sam4cp16bmb.h"
+#elif BOARD == ATPL230AMB
+#  include "atpl230amb/atpl230amb.h"
+#elif BOARD == XMEGA_C3_XPLAINED
+#  include "xmega_c3_xplained/xmega_c3_xplained.h"
+#elif BOARD == XMEGA_RF233_ZIGBIT
+#  include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
+#elif BOARD == XMEGA_A3_REB_CBB
+#  include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
+#elif BOARD == ATMEGARFX_RCB
+#  include "atmegarfx_rcb/atmegarfx_rcb.h"
+#elif BOARD == RCB256RFR2_XPRO
+#  include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
+#elif BOARD == XMEGA_RF212B_ZIGBIT
+#  include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
+#elif BOARD == SAM4E_XPLAINED_PRO
+#  include "sam4e_xplained_pro/sam4e_xplained_pro.h"
+#elif BOARD == ATMEGA328P_XPLAINED_MINI
+#  include "atmega328p_xplained_mini/atmega328p_xplained_mini.h"
+#elif BOARD == ATMEGA328PB_XPLAINED_MINI
+#  include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h"
+#elif BOARD == SAMB11_XPLAINED_PRO
+#  include "samb11_xplained_pro/samb11_xplained_pro.h"
+#elif BOARD == SAME70_XPLAINED
+#  include "same70_xplained/same70_xplained.h"
+#elif BOARD == ATMEGA168PB_XPLAINED_MINI
+#  include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h"
+#elif BOARD == ATMEGA324PB_XPLAINED_PRO
+#  include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h"
+#elif BOARD == SAMB11ZR_XPLAINED_PRO
+#  include "samb11zr_xplained_pro/samb11zr_xplained_pro.h"
+#elif BOARD == SIMULATOR_XMEGA_A1
+#  include "simulator/xmega_a1/simulator_xmega_a1.h"
+#elif BOARD == AVR_SIMULATOR_UC3
+#  include "avr_simulator_uc3/avr_simulator_uc3.h"
+#elif BOARD == SAMR21G18_MODULE
+# include "samr21g18_module/samr21g18_module.h"
+#elif BOARD == SAMR21B18_MODULE
+# include "samr21b18_module/samr21b18_module.h"
+#elif BOARD == SAMR34_XPLAINED_PRO && defined(__SAMR34J18B__)
+#  include "samr34_xplained_pro/samr34_xplained_pro.h"
+#elif BOARD == WLR089_XPLAINED_PRO && defined(__WLR089U0__)
+#  include "wlr089_xplained_pro/wlr089_xplained_pro.h"
+#elif BOARD == USER_BOARD
+// User-reserved area: #include the header file of your board here (if any).
+#  include "user_board.h"
+#elif BOARD == SAMR34_SENDCOMM && defined(__SAMR34J18B__)
+#  include "samr34_sendcomm/samr34_sendcomm.h"
+#elif BOARD == DUMMY_BOARD
+#  include "dummy/dummy_board.h"
+#elif BOARD == SAMB11ZR_SENSOR_TAG
+#  include "samb11zr_sensor_tag/samb11zr_sensor_tag.h"
+#else
+#  error No known Atmel board defined
+#endif
+
+#if (defined EXT_BOARD)
+#  if EXT_BOARD == MC300
+#    include "mc300/mc300.h"
+#  elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
+        (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)  || \
+        (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
+        (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
+#    include "sensors_xplained/sensors_xplained.h"
+#  elif EXT_BOARD == RZ600_AT86RF231
+#     include "at86rf231/at86rf231.h"
+#  elif EXT_BOARD == RZ600_AT86RF230B
+#    include "at86rf230b/at86rf230b.h"
+#  elif EXT_BOARD == RZ600_AT86RF212
+#    include "at86rf212/at86rf212.h"
+#  elif EXT_BOARD == SECURITY_XPLAINED
+#    include "security_xplained.h"
+#  elif EXT_BOARD == USER_EXT_BOARD
+    // User-reserved area: #include the header file of your extension board here
+    // (if any).
+#  endif
+#endif
+
+
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+
+#endif  // #ifdef __AVR32_ABI_COMPILER__
+#else
+/*! \brief This function initializes the board target resources
+ *
+ * This function should be called to ensure proper initialization of the target
+ * board hardware connected to the part.
+ */
+extern void board_init(void);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \}
+ */
+
+#endif  // _BOARD_H_

firmware/SendcommCmdsys/src/ASF/common/services/serial/sam0_usart/usart_serial.h

@@ -0,0 +1,141 @@
+/**
+ * \file
+ *
+ * \brief USART Serial wrapper service for the SAM D/L/C/R devices.
+ *
+ * Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef _USART_SERIAL_H_
+#define _USART_SERIAL_H_
+
+#include "compiler.h"
+#include "status_codes.h"
+#include "usart.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \name Serial Management Configuration */
+
+typedef Sercom * usart_inst_t;
+
+//struct usart_module usart;
+
+/*! \brief Initializes the Usart in serial mode.
+ *
+ * \param[in,out] module  Software instance of the USART to initialize.
+ * \param[in]     hw      Base address of the hardware USART.
+ * \param[in]     config  Configuration settings for the USART.
+ *
+ * \retval true if the initialization was successful
+ * \retval false if initialization failed (error in baud rate calculation)
+ */
+static inline bool usart_serial_init(
+		struct usart_module *const module,
+		usart_inst_t const hw,
+		const struct usart_config *const config)
+{
+	if (usart_init(module, hw, config) == STATUS_OK) {
+		return true;
+	}
+	else {
+		return false;
+	}
+}
+
+/** \brief Sends a character with the USART.
+ *
+ * \param[in,out] module  Software instance of the USART.
+ * \param[in]     c       Character to write.
+ *
+ * \return Status code
+ */
+static inline enum status_code usart_serial_putchar(
+		struct usart_module *const module,
+		uint8_t c)
+{
+	while(STATUS_OK !=usart_write_wait(module, c));
+
+	return STATUS_OK;
+}
+
+/** \brief Waits until a character is received, and returns it.
+ *
+ * \param[in,out] module  Software instance of the USART.
+ * \param[out]    c       Destination for the read character.
+ */
+static inline void usart_serial_getchar(
+		struct usart_module *const module,
+		uint8_t *c)
+{
+	uint16_t temp = 0;
+
+	while(STATUS_OK != usart_read_wait(module, &temp));
+
+	*c = temp;
+}
+
+/**
+ * \brief Send a sequence of bytes to USART device
+ *
+ * \param[in,out] module   Software instance of the USART.
+ * \param[in]     tx_data  Data buffer to read the data to write from.
+ * \param[in]     length   Length of data to write.
+ */
+static inline enum status_code usart_serial_write_packet(
+		struct usart_module *const module,
+		const uint8_t *tx_data,
+		uint16_t length)
+{
+	return usart_write_buffer_wait(module, tx_data, length);
+}
+
+/**
+ * \brief Receive a sequence of bytes from USART device
+ *
+ * \param[in,out] module   Software instance of the USART.
+ * \param[out]    rx_data  Data buffer to store the read data into.
+ * \param[in]     length   Length of data to read.
+ */
+static inline enum status_code usart_serial_read_packet(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	return usart_read_buffer_wait(module, rx_data, length);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _USART_SERIAL_H_

firmware/SendcommCmdsys/src/ASF/common/services/serial/serial.h

@@ -0,0 +1,269 @@
+/**
+ * \file
+ *
+ * \brief Serial Mode management
+ *
+ * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SERIAL_H_INCLUDED
+#define SERIAL_H_INCLUDED
+
+#include <parts.h>
+#include "status_codes.h"
+
+/**
+ * \typedef usart_if
+ *
+ * This type can be used independently to refer to USART module for the
+ * architecture used. It refers to the correct type definition for the
+ * architecture, ie. USART_t* for XMEGA or avr32_usart_t* for UC3.
+ */
+
+#if XMEGA
+# include "xmega_usart/usart_serial.h"
+#elif MEGA_RF
+# include "megarf_usart/usart_serial.h"
+#elif UC3
+# include "uc3_usart/usart_serial.h"
+#elif (SAMB)
+#include "samb_uart/uart_serial.h"
+#elif (SAM0)
+#include "sam0_usart/usart_serial.h"
+#elif SAM
+# include "sam_uart/uart_serial.h"
+#else
+# error Unsupported chip type
+#endif
+
+/**
+ *
+ * \defgroup serial_group Serial Interface (Serial)
+ *
+ * See \ref serial_quickstart.
+ *
+ * This is the common API for serial interface. Additional features are available
+ * in the documentation of the specific modules.
+ *
+ * \section serial_group_platform Platform Dependencies
+ *
+ * The serial API is partially chip- or platform-specific. While all
+ * platforms provide mostly the same functionality, there are some
+ * variations around how different bus types and clock tree structures
+ * are handled.
+ *
+ * The following functions are available on all platforms, but there may
+ * be variations in the function signature (i.e. parameters) and
+ * behaviour. These functions are typically called by platform-specific
+ * parts of drivers, and applications that aren't intended to be
+ * portable:
+ *   - usart_serial_init()
+ *   - usart_serial_putchar()
+ *   - usart_serial_getchar()
+ *   - usart_serial_write_packet()
+ *   - usart_serial_read_packet()
+ *
+ *
+ * @{
+ */
+ 
+//! @}
+
+/**
+ * \page serial_quickstart Quick start guide for Serial Interface service
+ *
+ * This is the quick start guide for the \ref serial_group "Serial Interface module", with
+ * step-by-step instructions on how to configure and use the serial in a
+ * selection of use cases.
+ *
+ * The use cases contain several code fragments. The code fragments in the
+ * steps for setup can be copied into a custom initialization function, while
+ * the steps for usage can be copied into, e.g., the main application function.
+ *
+ * \section serial_use_cases Serial use cases
+ * - \ref serial_basic_use_case
+ * - \subpage serial_use_case_1
+ *
+ * \section serial_basic_use_case Basic use case - transmit a character
+ * In this use case, the serial module is configured for:
+ * - Using USARTD0
+ * - Baudrate: 9600
+ * - Character length: 8 bit
+ * - Parity mode: Disabled
+ * - Stop bit: None
+ * - RS232 mode
+ *
+ * The use case waits for a received character on the configured USART and
+ * echoes the character back to the same USART.
+ *
+ * \section serial_basic_use_case_setup Setup steps
+ *
+ * \subsection serial_basic_use_case_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclk)"
+ *
+ * \subsection serial_basic_use_case_setup_code Example code
+ * The following configuration must be added to the project (typically to a 
+ * conf_uart_serial.h file, but it can also be added to your main application file.)
+ *
+ * \note The following takes SAM3X configuration for example, other devices have similar
+ * configuration, but their parameters may be different, refer to corresponding header files.
+ *
+ * \code
+	#define USART_SERIAL                     &USARTD0
+	#define USART_SERIAL_BAUDRATE            9600
+	#define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
+	#define USART_SERIAL_PARITY              US_MR_PAR_NO
+	#define USART_SERIAL_STOP_BIT            false
+\endcode
+ *
+ * A variable for the received byte must be added:
+ * \code uint8_t received_byte; \endcode
+ *
+ * Add to application initialization:
+ * \code
+	    sysclk_init();
+
+	    static usart_serial_options_t usart_options = {
+	       .baudrate = USART_SERIAL_BAUDRATE,
+	       .charlength = USART_SERIAL_CHAR_LENGTH,
+	       .paritytype = USART_SERIAL_PARITY,
+	       .stopbits = USART_SERIAL_STOP_BIT
+	    };
+
+	    usart_serial_init(USART_SERIAL, &usart_options);
+\endcode
+ *
+ * \subsection serial_basic_use_case_setup_flow Workflow
+ * -# Initialize system clock:
+ *   - \code sysclk_init(); \endcode
+ * -# Create serial USART options struct:
+ *   - \code
+	static usart_serial_options_t usart_options = {
+	   .baudrate = USART_SERIAL_BAUDRATE,
+	   .charlength = USART_SERIAL_CHAR_LENGTH,
+	   .paritytype = USART_SERIAL_PARITY,
+	   .stopbits = USART_SERIAL_STOP_BIT
+	};
+\endcode
+ * -# Initialize the serial service:
+ *   - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode
+ *
+ * \section serial_basic_use_case_usage Usage steps
+ *
+ * \subsection serial_basic_use_case_usage_code Example code
+ * Add to application C-file:
+ * \code
+	usart_serial_getchar(USART_SERIAL, &received_byte);
+	usart_serial_putchar(USART_SERIAL, received_byte);
+\endcode
+ *
+ * \subsection serial_basic_use_case_usage_flow Workflow
+ * -# Wait for reception of a character:
+ *   - \code usart_serial_getchar(USART_SERIAL, &received_byte); \endcode
+ * -# Echo the character back:
+ *   - \code usart_serial_putchar(USART_SERIAL, received_byte); \endcode
+ */
+
+/**
+ * \page serial_use_case_1 Advanced use case - Send a packet of serial data
+ *
+ * In this use case, the USART module is configured for:
+ * - Using USARTD0
+ * - Baudrate: 9600
+ * - Character length: 8 bit
+ * - Parity mode: Disabled
+ * - Stop bit: None
+ * - RS232 mode
+ *
+ * The use case sends a string of text through the USART.
+ *
+ * \section serial_use_case_1_setup Setup steps
+ *
+ * \subsection serial_use_case_1_setup_prereq Prerequisites
+ * -# \ref sysclk_group "System Clock Management (sysclk)"
+ *
+ * \subsection serial_use_case_1_setup_code Example code
+ * The following configuration must be added to the project (typically to a 
+ * conf_uart_serial.h file, but it can also be added to your main application file.):
+ *
+ * \note The following takes SAM3X configuration for example, other devices have similar
+ * configuration, but their parameters may be different, refer to corresponding header files.
+ *
+ * \code
+	#define USART_SERIAL                     &USARTD0
+	#define USART_SERIAL_BAUDRATE            9600
+	#define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
+	#define USART_SERIAL_PARITY              US_MR_PAR_NO
+	#define USART_SERIAL_STOP_BIT            false
+\endcode
+ *
+ * Add to application initialization:
+ * \code
+	    sysclk_init();
+
+	    static usart_serial_options_t usart_options = {
+	       .baudrate = USART_SERIAL_BAUDRATE,
+	       .charlength = USART_SERIAL_CHAR_LENGTH,
+	       .paritytype = USART_SERIAL_PARITY,
+	       .stopbits = USART_SERIAL_STOP_BIT
+	    };
+
+	    usart_serial_init(USART_SERIAL, &usart_options);
+\endcode
+ *
+ * \subsection serial_use_case_1_setup_flow Workflow
+ * -# Initialize system clock:
+ *   - \code sysclk_init(); \endcode
+ * -# Create USART options struct:
+ *   - \code
+	static usart_serial_options_t usart_options = {
+	   .baudrate = USART_SERIAL_BAUDRATE,
+	   .charlength = USART_SERIAL_CHAR_LENGTH,
+	   .paritytype = USART_SERIAL_PARITY,
+	   .stopbits = USART_SERIAL_STOP_BIT
+	};
+\endcode
+ * -# Initialize in RS232 mode:
+ *   - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode
+ *
+ * \section serial_use_case_1_usage Usage steps
+ *
+ * \subsection serial_use_case_1_usage_code Example code
+ * Add to, e.g., main loop in application C-file:
+ * \code
+	usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String"));
+\endcode
+ *
+ * \subsection serial_use_case_1_usage_flow Workflow
+ * -# Write a string of text to the USART:
+ *   - \code usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String")); \endcode
+ */
+
+#endif /* SERIAL_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/common/utils/interrupt.h

@@ -0,0 +1,132 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for 8- and 32-bit AVR
+ *
+ * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef UTILS_INTERRUPT_H
+#define UTILS_INTERRUPT_H
+
+#include <parts.h>
+
+#if XMEGA || MEGA
+#  include "interrupt/interrupt_avr8.h"
+#elif UC3
+#  include "interrupt/interrupt_avr32.h"
+#elif SAM || SAMB
+#  include "interrupt/interrupt_sam_nvic.h"
+#else
+#  error Unsupported device.
+#endif
+
+/**
+ * \defgroup interrupt_group Global interrupt management
+ *
+ * This is a driver for global enabling and disabling of interrupts.
+ *
+ * @{
+ */
+
+#if defined(__DOXYGEN__)
+/**
+ * \def CONFIG_INTERRUPT_FORCE_INTC
+ * \brief Force usage of the ASF INTC driver
+ *
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
+ * This is useful to ensure compatibility across compilers and shall be used only when required
+ * by the application needs.
+ */
+#  define CONFIG_INTERRUPT_FORCE_INTC
+#endif
+
+//! \name Global interrupt flags
+//@{
+/**
+ * \typedef irqflags_t
+ * \brief Type used for holding state of interrupt flag
+ */
+
+/**
+ * \def cpu_irq_enable
+ * \brief Enable interrupts globally
+ */
+
+/**
+ * \def cpu_irq_disable
+ * \brief Disable interrupts globally
+ */
+
+/**
+ * \fn irqflags_t cpu_irq_save(void)
+ * \brief Get and clear the global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_restore.
+ *
+ * \return Current state of interrupt flags.
+ *
+ * \note This function leaves interrupts disabled.
+ */
+
+/**
+ * \fn void cpu_irq_restore(irqflags_t flags)
+ * \brief Restore global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_save.
+ *
+ * \param flags State to set interrupt flag to.
+ */
+
+/**
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
+ * \brief Check if interrupts are globally enabled in supplied flags
+ *
+ * \param flags Currents state of interrupt flags.
+ *
+ * \return True if interrupts are enabled.
+ */
+
+/**
+ * \def cpu_irq_is_enabled
+ * \brief Check if interrupts are globally enabled
+ *
+ * \return True if interrupts are enabled.
+ */
+//@}
+
+//! @}
+
+/**
+ * \ingroup interrupt_group
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions
+ */
+
+#endif /* UTILS_INTERRUPT_H */

firmware/SendcommCmdsys/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c

@@ -0,0 +1,76 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "interrupt_sam_nvic.h"
+
+#if !defined(__DOXYGEN__)
+/* Deprecated - global flag to determine the global interrupt state. Required by
+ * QTouch library, however new applications should use cpu_irq_is_enabled()
+ * which probes the true global interrupt state from the CPU special registers.
+ */
+volatile bool g_interrupt_enabled = true;
+#endif
+
+void cpu_irq_enter_critical(void)
+{
+	if (cpu_irq_critical_section_counter == 0) {
+		if (cpu_irq_is_enabled()) {
+			cpu_irq_disable();
+			cpu_irq_prev_interrupt_state = true;
+		} else {
+			/* Make sure the to save the prev state as false */
+			cpu_irq_prev_interrupt_state = false;
+		}
+
+	}
+
+	cpu_irq_critical_section_counter++;
+}
+
+void cpu_irq_leave_critical(void)
+{
+	/* Check if the user is trying to leave a critical section when not in a critical section */
+	Assert(cpu_irq_critical_section_counter > 0);
+
+	cpu_irq_critical_section_counter--;
+
+	/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
+	   was enabled when entering critical state */
+	if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
+		cpu_irq_enable();
+	}
+}
+

firmware/SendcommCmdsys/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h

@@ -0,0 +1,179 @@
+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef UTILS_INTERRUPT_INTERRUPT_H
+#define UTILS_INTERRUPT_INTERRUPT_H
+
+#include <compiler.h>
+#include <parts.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \weakgroup interrupt_group
+ *
+ * @{
+ */
+
+/**
+ * \name Interrupt Service Routine definition
+ *
+ * @{
+ */
+
+/**
+ * \brief Define service routine
+ *
+ * \note For NVIC devices the interrupt service routines are predefined to
+ *       add to vector table in binary generation, so there is no service
+ *       register at run time. The routine collections are in exceptions.h.
+ *
+ * Usage:
+ * \code
+	ISR(foo_irq_handler)
+	{
+	     // Function definition
+	     ...
+	}
+\endcode
+ *
+ * \param func Name for the function.
+ */
+#  define ISR(func)   \
+	void func (void)
+
+/**
+ * \brief Initialize interrupt vectors
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to initialize them, except defined the vector function with
+ * right name.
+ *
+ * This must be called prior to \ref irq_register_handler.
+ */
+#  define irq_initialize_vectors()   \
+	do {                             \
+	} while(0)
+
+/**
+ * \brief Register handler for interrupt
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to register them, except defined the vector function with
+ * right name.
+ *
+ * Usage:
+ * \code
+	irq_initialize_vectors();
+	irq_register_handler(foo_irq_handler);
+\endcode
+ *
+ * \note The function \a func must be defined with the \ref ISR macro.
+ * \note The functions prototypes can be found in the device exception header
+ *       files (exceptions.h).
+ */
+#  define irq_register_handler(int_num, int_prio)                      \
+	NVIC_ClearPendingIRQ(    (IRQn_Type)int_num);                      \
+	NVIC_SetPriority(    (IRQn_Type)int_num, int_prio);                \
+	NVIC_EnableIRQ(      (IRQn_Type)int_num);                          \
+
+//@}
+
+#  define cpu_irq_enable()                     \
+	do {                                       \
+		g_interrupt_enabled = true;            \
+		__DMB();                               \
+		__enable_irq();                        \
+	} while (0)
+#  define cpu_irq_disable()                    \
+	do {                                       \
+		__disable_irq();                       \
+		__DMB();                               \
+		g_interrupt_enabled = false;           \
+	} while (0)
+
+typedef uint32_t irqflags_t;
+
+#if !defined(__DOXYGEN__)
+extern volatile bool g_interrupt_enabled;
+#endif
+
+#define cpu_irq_is_enabled()    (__get_PRIMASK() == 0)
+
+static volatile uint32_t cpu_irq_critical_section_counter;
+static volatile bool     cpu_irq_prev_interrupt_state;
+
+static inline irqflags_t cpu_irq_save(void)
+{
+	volatile irqflags_t flags = cpu_irq_is_enabled();
+	cpu_irq_disable();
+	return flags;
+}
+
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
+{
+	return (flags);
+}
+
+static inline void cpu_irq_restore(irqflags_t flags)
+{
+	if (cpu_irq_is_enabled_flags(flags))
+		cpu_irq_enable();
+}
+
+void cpu_irq_enter_critical(void);
+void cpu_irq_leave_critical(void);
+
+/**
+ * \weakgroup interrupt_deprecated_group
+ * @{
+ */
+
+#define Enable_global_interrupt()            cpu_irq_enable()
+#define Disable_global_interrupt()           cpu_irq_disable()
+#define Is_global_interrupt_enabled()        cpu_irq_is_enabled()
+
+//@}
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */

firmware/SendcommCmdsys/src/ASF/common2/services/delay/delay.h

@@ -0,0 +1,91 @@
+/**
+ * \file
+ *
+ * \brief Common Delay Service
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef DELAY_H_INCLUDED
+#define DELAY_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup group_common_services_delay Busy-Wait Delay Routines
+ *
+ * This module provides simple loop-based delay routines for those
+ * applications requiring a brief wait during execution. Common for
+ * API ver. 2.
+ *
+ * @{
+ */
+
+#ifdef SYSTICK_MODE
+#include "sam0/systick_counter.h"
+#endif
+#ifdef CYCLE_MODE
+#include "sam0/cycle_counter.h"
+#endif
+
+void delay_init(void);
+
+/**
+ * \def delay_s
+ * \brief Delay in at least specified number of seconds.
+ * \param delay Delay in seconds
+ */
+#define delay_s(delay)          ((delay) ? cpu_delay_s(delay) : cpu_delay_us(1))
+
+/**
+ * \def delay_ms
+ * \brief Delay in at least specified number of milliseconds.
+ * \param delay Delay in milliseconds
+ */
+#define delay_ms(delay)         ((delay) ? cpu_delay_ms(delay) : cpu_delay_us(1))
+
+/**
+ * \def delay_us
+ * \brief Delay in at least specified number of microseconds.
+ * \param delay Delay in microseconds
+ */
+#define delay_us(delay)         ((delay) ? cpu_delay_us(delay) : cpu_delay_us(1))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* DELAY_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/common2/services/delay/sam0/systick_counter.c

@@ -0,0 +1,86 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "delay.h"
+
+/**
+ * Value used to calculate ms delay. Default to be used with a 8MHz clock;
+ */
+static uint32_t cycles_per_ms = 8000000UL / 1000;
+static uint32_t cycles_per_us = 8000000UL / 1000000;
+
+/**
+ * \brief Initialize the delay driver.
+ *
+ * This must be called during start up to initialize the delay routine with
+ * the current used main clock. It must run any time the main CPU clock is changed.
+ */
+void delay_init(void)
+{
+	cycles_per_ms = system_gclk_gen_get_hz(0);
+	cycles_per_ms /= 1000;
+	cycles_per_us = cycles_per_ms / 1000;
+
+	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+}
+
+/**
+ * \brief Delay loop to delay at least n number of microseconds
+ *
+ * \param n  Number of microseconds to wait
+ */
+void delay_cycles_us(
+		uint32_t n)
+{
+	while (n--) {
+		/* Devide up to blocks of 10u */
+		delay_cycles(cycles_per_us);
+	}
+}
+
+/**
+ * \brief Delay loop to delay at least n number of milliseconds
+ *
+ * \param n  Number of milliseconds to wait
+ */
+void delay_cycles_ms(
+		uint32_t n)
+{
+	while (n--) {
+		/* Devide up to blocks of 1ms */
+		delay_cycles(cycles_per_ms);
+	}
+}

firmware/SendcommCmdsys/src/ASF/common2/services/delay/sam0/systick_counter.h

@@ -0,0 +1,103 @@
+/**
+ * \file
+ *
+ * \brief ARM functions for busy-wait delay loops
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef CYCLE_COUNTER_H_INCLUDED
+#define CYCLE_COUNTER_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Convenience functions for busy-wait delay loops
+ *
+ * @{
+ */
+
+/**
+ * \brief Delay loop to delay n number of cycles
+ * Delay program execution for at least the specified number of CPU cycles.
+ *
+ * \param n  Number of cycles to delay
+ */
+static inline void delay_cycles(
+		const uint32_t n)
+{
+	if (n > 0) {
+		SysTick->LOAD = n;
+		SysTick->VAL = 0;
+
+		while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
+		};
+	}
+}
+
+void delay_cycles_us(uint32_t n);
+
+void delay_cycles_ms(uint32_t n);
+
+/**
+ * \brief Delay program execution for at least the specified number of microseconds.
+ *
+ * \param delay  number of microseconds to wait
+ */
+#define cpu_delay_us(delay)      delay_cycles_us(delay)
+
+/**
+ * \brief Delay program execution for at least the specified number of milliseconds.
+ *
+ * \param delay  number of milliseconds to wait
+ */
+#define cpu_delay_ms(delay)      delay_cycles_ms(delay)
+
+/**
+ * \brief Delay program execution for at least the specified number of seconds.
+ *
+ * \param delay  number of seconds to wait
+ */
+#define cpu_delay_s(delay)       delay_cycles_ms(1000 * delay)
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CYCLE_COUNTER_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/boards/samr34_sendcomm/board_init.c

@@ -0,0 +1,80 @@
+/**
+ * \file
+ *
+ * \brief SAM R34 Xplained Pro board initialization
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include <compiler.h>
+#include <board.h>
+#include <conf_board.h>
+#include <port.h>
+
+#if defined(__GNUC__)
+void board_init(void) WEAK __attribute__((alias("system_board_init")));
+#elif defined(__ICCARM__)
+void board_init(void);
+#  pragma weak board_init=system_board_init
+#endif
+
+void system_board_init(void)
+{
+	struct port_config pin_conf;
+	port_get_config_defaults(&pin_conf);
+
+	/* Configure LEDs as outputs, turn them off */
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(LED_0_PIN, &pin_conf);
+	port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
+	
+	/* Configure LEDs as outputs, turn them off */
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(LED_1_PIN, &pin_conf);
+	port_pin_set_output_level(LED_1_PIN, LED_1_INACTIVE);
+#ifdef RFSWITCH_ENABLE
+	/* Configure RFSWITCH as output */
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(RF_SWITCH_PIN, &pin_conf);
+	port_pin_set_output_level(RF_SWITCH_PIN, RF_SWITCH_INACTIVE);	
+#endif
+
+#ifdef TCXO_ENABLE
+	/* Configure TXPO PWR as output */
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(TCXO_PWR_PIN, &pin_conf);
+	port_pin_set_output_level(TCXO_PWR_PIN, TCXO_PWR_INACTIVE);
+#endif
+	/* Set buttons as inputs */
+	pin_conf.direction  = PORT_PIN_DIR_INPUT;
+	pin_conf.input_pull = PORT_PIN_PULL_UP;
+	port_pin_set_config(BUTTON_0_PIN, &pin_conf);
+		
+}

firmware/SendcommCmdsys/src/ASF/sam0/boards/samr34_sendcomm/samr34_sendcomm.h

@@ -0,0 +1,526 @@
+/**
+ * \file
+ *
+ * \brief SAMR34 Sendcomm board definition
+ *
+ * Copyright (c) 2020 Europalab Devices ApS
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * This file is part of Sendcomm.
+ *
+ * Sendcomm is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Sendcomm is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Sendcomm. If not, see <https://www.gnu.org/licenses/>.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef SAMR34_SENDCOMM_H_INCLUDED
+#define SAMR34_SENDCOMM_H_INCLUDED
+
+#include <conf_board.h>
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup group_common_boards
+ * \defgroup samr34_xplained_pro_group SAM R34 Xplained Pro board
+ *
+ * @{
+ */
+
+void system_board_init(void);
+
+/**
+ * \defgroup samr34xplained_pro_features_group Features
+ *
+ * Symbols that describe features and capabilities of the board.
+ *
+ * @{
+ */
+
+/** Name string macro */
+#define BOARD_NAME                "SAMR34_SENDCOMM"
+
+/** \name Resonator definitions
+ *  @{ */
+#define BOARD_FREQ_SLCK_XTAL      (32768U)
+#define BOARD_FREQ_SLCK_BYPASS    (32768U)
+#define BOARD_FREQ_MAINCK_XTAL    0 /* Not Mounted */
+#define BOARD_FREQ_MAINCK_BYPASS  0 /* Not Mounted */
+#define BOARD_MCK                 CHIP_FREQ_CPU_MAX
+#define BOARD_OSC_STARTUP_US      15625
+/** @} */
+
+/** \name LED0 definitions
+ *  @{ */
+#define LED0_PIN                  PIN_PA19
+#define LED0_ACTIVE               false
+#define LED0_INACTIVE             !LED0_ACTIVE
+/** @} */
+
+/** \name LED1 definitions
+ *  @{ */
+#define LED1_PIN                  PIN_PA18
+#define LED1_ACTIVE               false
+#define LED1_INACTIVE             !LED1_ACTIVE
+/** @} */
+
+/** \name SW0 definitions
+ *  @{ */
+#define SW0_PIN                   PIN_PA28
+#define SW0_ACTIVE                false
+#define SW0_INACTIVE              !SW0_ACTIVE
+#define SW0_EIC_PIN               PIN_PA28
+#define SW0_EIC_MUX               MUX_PA28A_EIC_EXTINT8
+#define SW0_EIC_PINMUX            PINMUX_PA28A_EIC_EXTINT8
+#define SW0_EIC_LINE              8
+/** @} */
+
+/** \name RF SWITCH definitions
+ *  @{ */
+#define RF_SWITCH_PIN				PIN_PA13
+#define RF_SWITCH_ACTIVE             true
+#define RF_SWITCH_INACTIVE	        !RF_SWITCH_ACTIVE
+/** @} */
+
+/** \name TCXO PWR Pin definitions
+ *  @{ */
+#define TCXO_PWR_PIN				PIN_PA09
+#define TCXO_PWR_ACTIVE             true
+#define TCXO_PWR_INACTIVE	        !TCXO_PWR_ACTIVE
+/** @} */
+
+
+/**
+ * \name LED #0 definitions
+ *
+ * Wrapper macros for LED0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ *  @{ */
+#define LED_0_NAME                "LED0 (yellow)"
+#define LED_0_PIN                 LED0_PIN
+#define LED_0_ACTIVE              LED0_ACTIVE
+#define LED_0_INACTIVE            LED0_INACTIVE
+#define LED0_GPIO                 LED0_PIN
+#define LED0                      LED0_PIN
+
+#define LED_0_PWM3CTRL_MODULE     TCC0
+#define LED_0_PWM3CTRL_CHANNEL    3
+#define LED_0_PWM3CTRL_OUTPUT     3
+#define LED_0_PWM3CTRL_PIN        PIN_PA19F_TCC0_WO3
+#define LED_0_PWM3CTRL_MUX        MUX_PA19F_TCC0_WO3
+#define LED_0_PWM3CTRL_PINMUX     PINMUX_PA19F_TCC0_WO3
+/** @} */
+
+/**
+ * \name LED #1 definitions
+ *
+ * Wrapper macros for LED1, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ *  @{ */
+#define LED_1_NAME                "LED1 (Green)"
+#define LED_1_PIN                 LED1_PIN
+#define LED_1_ACTIVE              LED1_ACTIVE
+#define LED_1_INACTIVE            LED1_INACTIVE
+#define LED1_GPIO                 LED1_PIN
+#define LED1                      LED1_PIN
+
+#define LED_1_PWM2CTRL_MODULE     TCC0
+#define LED_1_PWM2CTRL_CHANNEL    2
+#define LED_1_PWM2CTRL_OUTPUT     2
+#define LED_1_PWM2CTRL_PIN        PINMUX_PA18F_TCC0_WO2
+#define LED_1_PWM2CTRL_MUX        MUX_PA18F_TCC0_WO2
+#define LED_1_PWM2CTRL_PINMUX     PINMUX_PA18F_TCC0_WO2
+/** @} */
+
+/** Number of on-board LEDs */
+#define LED_COUNT                 2
+
+
+/**
+ * \name Button #0 definitions
+ *
+ * Wrapper macros for SW0, to ensure common naming across all Xplained Pro
+ * boards.
+ *
+ *  @{ */
+#define BUTTON_0_NAME             "SW0"
+#define BUTTON_0_PIN              SW0_PIN
+#define BUTTON_0_ACTIVE           SW0_ACTIVE
+#define BUTTON_0_INACTIVE         SW0_INACTIVE
+#define BUTTON_0_EIC_PIN          SW0_EIC_PIN
+#define BUTTON_0_EIC_MUX          SW0_EIC_MUX
+#define BUTTON_0_EIC_PINMUX       SW0_EIC_PINMUX
+#define BUTTON_0_EIC_LINE         SW0_EIC_LINE
+/** @} */
+
+/** Number of on-board buttons */
+#define BUTTON_COUNT 1
+
+/** \name Extension header #1 pin definitions
+ *  @{
+ */
+#define EXT1_PIN_3                PIN_PA06
+#define EXT1_PIN_4                PIN_PA07
+#define EXT1_PIN_5                PIN_PA08
+#define EXT1_PIN_6                PIN_PA28
+#define EXT1_PIN_7                PIN_PA18
+#define EXT1_PIN_8                PIN_PA19
+#define EXT1_PIN_9                PIN_PA22
+#define EXT1_PIN_10               PIN_PA15
+#define EXT1_PIN_11               PIN_PA16
+#define EXT1_PIN_12               PIN_PA17
+#define EXT1_PIN_13               PIN_PA05
+#define EXT1_PIN_14               PIN_PA04
+#define EXT1_PIN_15               PIN_PA23
+#define EXT1_PIN_16               PIN_PB22
+#define EXT1_PIN_17               PIN_PB02
+#define EXT1_PIN_18               PIN_PB23
+/** @} */
+
+/** \name Extension header #1 pin definitions by function
+ *  @{
+ */
+#define EXT1_PIN_ADC_0            EXT1_PIN_3
+#define EXT1_PIN_ADC_1            EXT1_PIN_4
+#define EXT1_PIN_GPIO_0           EXT1_PIN_5
+#define EXT1_PIN_GPIO_1           EXT1_PIN_6
+#define EXT1_PIN_PWM_0            EXT1_PIN_7
+#define EXT1_PIN_PWM_1            EXT1_PIN_8
+#define EXT1_PIN_IRQ              EXT1_PIN_9
+#define EXT1_PIN_I2C_SDA          EXT1_PIN_11
+#define EXT1_PIN_I2C_SCL          EXT1_PIN_12
+#define EXT1_PIN_UART_RX          EXT1_PIN_13
+#define EXT1_PIN_UART_TX          EXT1_PIN_14
+#define EXT1_PIN_SPI_SS_1         EXT1_PIN_10
+#define EXT1_PIN_SPI_SS_0         EXT1_PIN_15
+#define EXT1_PIN_SPI_MOSI         EXT1_PIN_16
+#define EXT1_PIN_SPI_MISO         EXT1_PIN_17
+#define EXT1_PIN_SPI_SCK          EXT1_PIN_18
+/** @} */
+
+/** \name Extension header #1 ADC definitions
+ *  @{
+ */
+#define EXT1_ADC_MODULE           ADC
+#define EXT1_ADC_6_CHANNEL        6
+#define EXT1_ADC_6_PIN            PIN_PA06B_ADC_AIN6
+#define EXT1_ADC_6_MUX            MUX_PA06B_ADC_AIN6
+#define EXT1_ADC_6_PINMUX         PINMUX_PA06B_ADC_AIN6
+#define EXT1_ADC_7_CHANNEL        7
+#define EXT1_ADC_7_PIN            PIN_PA07B_ADC_AIN7
+#define EXT1_ADC_7_MUX            MUX_PA07B_ADC_AIN7
+#define EXT1_ADC_7_PINMUX         PINMUX_PA07B_ADC_AIN7
+/** @} */
+
+/** \name Extension header #1 PWM definitions
+ *  @{
+ */
+#define EXT1_PWM_MODULE           TCC0
+#define EXT1_PWM_0_CHANNEL        2
+#define EXT1_PWM_0_PIN            PIN_PA18F_TCC0_WO2
+#define EXT1_PWM_0_MUX            MUX_PA18F_TCC0_WO2
+#define EXT1_PWM_0_PINMUX         PINMUX_PA18F_TCC0_WO2
+#define EXT1_PWM_1_CHANNEL        3
+#define EXT1_PWM_1_PIN            PIN_PA19F_TCC0_WO3
+#define EXT1_PWM_1_MUX            MUX_PA19F_TCC0_WO3
+#define EXT1_PWM_1_PINMUX         PINMUX_PA19F_TCC0_WO3
+/** @} */
+
+/** \name Extension header #1 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT1_IRQ_MODULE           EIC
+#define EXT1_IRQ_INPUT            6
+#define EXT1_IRQ_PIN              PIN_PA22A_EIC_EXTINT6
+#define EXT1_IRQ_MUX              MUX_PA22A_EIC_EXTINT6
+#define EXT1_IRQ_PINMUX           PINMUX_PA22A_EIC_EXTINT6
+/** @} */
+
+/** \name Extension header #1 I2C definitions
+ *  @{
+ */
+#define EXT1_I2C_MODULE              SERCOM1
+#define EXT1_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA16C_SERCOM1_PAD0
+#define EXT1_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA17C_SERCOM1_PAD1
+#define EXT1_I2C_SERCOM_DMAC_ID_TX   SERCOM1_DMAC_ID_TX
+#define EXT1_I2C_SERCOM_DMAC_ID_RX   SERCOM1_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #1 UART definitions
+ *  @{
+ */
+#define EXT1_UART_MODULE              SERCOM0
+#define EXT1_UART_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EXT1_UART_SERCOM_PINMUX_PAD0  PINMUX_PA04D_SERCOM0_PAD0
+#define EXT1_UART_SERCOM_PINMUX_PAD1  PINMUX_PA05D_SERCOM0_PAD1
+#define EXT1_UART_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EXT1_UART_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+#define EXT1_UART_SERCOM_DMAC_ID_TX   SERCOM0_DMAC_ID_TX
+#define EXT1_UART_SERCOM_DMAC_ID_RX   SERCOM0_DMAC_ID_RX
+
+#define EXT1_UART_SERCOM_PIN_PAD0     PIN_PA04D_SERCOM0_PAD0
+#define EXT1_UART_SERCOM_PIN_PAD1     PIN_PA05D_SERCOM0_PAD1
+/** @} */
+
+/** \name Extension header #1 SPI definitions
+ *  @{
+ */
+#define EXT1_SPI_MODULE              SERCOM5
+#define EXT1_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT1_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB02D_SERCOM5_PAD0
+#define EXT1_SPI_SERCOM_PINMUX_PAD1  PINMUX_PA23D_SERCOM5_PAD1
+#define EXT1_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
+#define EXT1_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
+#define EXT1_SPI_SERCOM_DMAC_ID_TX   SERCOM5_DMAC_ID_TX
+#define EXT1_SPI_SERCOM_DMAC_ID_RX   SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 pin definitions
+ *  @{
+ */
+#define EXT3_PIN_5                PIN_PA27
+#define EXT3_PIN_10               PIN_PA08
+#define EXT3_PIN_11               PIN_PA16
+#define EXT3_PIN_12               PIN_PA17
+#define EXT3_PIN_15               PIN_PA14
+#define EXT3_PIN_16               PIN_PB22
+#define EXT3_PIN_17               PIN_PB02
+#define EXT3_PIN_18               PIN_PB23
+/** @} */
+
+/** \name Extension header #3 pin definitions by function
+ *  @{
+ */
+#define EXT3_PIN_GPIO_1           EXT3_PIN_5
+#define EXT3_PIN_I2C_SDA          EXT3_PIN_11
+#define EXT3_PIN_I2C_SCL          EXT3_PIN_12
+#define EXT3_PIN_SPI_SS_1         EXT3_PIN_10
+#define EXT3_PIN_SPI_SS_0         EXT3_PIN_15
+#define EXT3_PIN_SPI_MOSI         EXT3_PIN_16
+#define EXT3_PIN_SPI_MISO         EXT3_PIN_17
+#define EXT3_PIN_SPI_SCK          EXT3_PIN_18
+/** @} */
+
+
+/** \name Extension header #3 IRQ/External interrupt definitions
+ *  @{
+ */
+#define EXT3_IRQ_MODULE           EIC
+#define EXT3_IRQ_INPUT            0
+#define EXT3_IRQ_PIN              PIN_PA16A_EIC_EXTINT0
+#define EXT3_IRQ_MUX              MUX_PA16A_EIC_EXTINT0
+#define EXT3_IRQ_PINMUX           PINMUX_PA16A_EIC_EXTINT0
+/** @} */
+
+/** \name Extension header #3 I2C definitions
+ *  @{
+ */
+#define EXT3_I2C_MODULE              SERCOM1
+#define EXT3_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA16C_SERCOM1_PAD0
+#define EXT3_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA17C_SERCOM1_PAD1
+#define EXT3_I2C_SERCOM_DMAC_ID_TX   SERCOM1_DMAC_ID_TX
+#define EXT3_I2C_SERCOM_DMAC_ID_RX   SERCOM1_DMAC_ID_RX
+/** @} */
+
+/** \name Extension header #3 UART definitions
+ *  @{
+ */
+#define EXT3_UART_MODULE              SERCOM1
+#define EXT3_UART_SERCOM_MUX_SETTING  USART_RX_3_TX_2_XCK_3
+#define EXT3_UART_SERCOM_PINMUX_PAD0  PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD1  PINMUX_UNUSED
+#define EXT3_UART_SERCOM_PINMUX_PAD2  PINMUX_PA18C_SERCOM1_PAD2
+#define EXT3_UART_SERCOM_PINMUX_PAD3  PINMUX_PA19C_SERCOM1_PAD3
+#define EXT3_UART_SERCOM_DMAC_ID_TX   SERCOM1_DMAC_ID_TX
+#define EXT3_UART_SERCOM_DMAC_ID_RX   SERCOM1_DMAC_ID_RX
+
+/** @} */
+
+/** \name Extension header #3 SPI definitions
+ *  @{
+ */
+#define EXT3_SPI_MODULE              SERCOM5
+#define EXT3_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EXT3_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB02D_SERCOM5_PAD0
+#define EXT3_SPI_SERCOM_PINMUX_PAD1  PINMUX_UNUSED
+#define EXT3_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
+#define EXT3_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
+#define EXT3_SPI_SERCOM_DMAC_ID_TX   SERCOM5_DMAC_ID_TX
+#define EXT3_SPI_SERCOM_DMAC_ID_RX   SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger I2C interface definitions
+ * @{
+ */
+#define EDBG_I2C_MODULE              SERCOM1
+#define EDBG_I2C_SERCOM_PINMUX_PAD0  PINMUX_PA16C_SERCOM1_PAD0
+#define EDBG_I2C_SERCOM_PINMUX_PAD1  PINMUX_PA17C_SERCOM1_PAD1
+#define EDBG_I2C_SERCOM_DMAC_ID_TX   SERCOM1_DMAC_ID_TX
+#define EDBG_I2C_SERCOM_DMAC_ID_RX   SERCOM1_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger SPI interface definitions
+ * @{
+ */
+#define EDBG_SPI_MODULE              SERCOM5
+#define EDBG_SPI_SERCOM_MUX_SETTING  SPI_SIGNAL_MUX_SETTING_E
+#define EDBG_SPI_SERCOM_PINMUX_PAD0  PINMUX_PB02D_SERCOM5_PAD0
+#define EDBG_SPI_SERCOM_PINMUX_PAD1  PINMUX_UNUSED
+#define EDBG_SPI_SERCOM_PINMUX_PAD2  PINMUX_PB22D_SERCOM5_PAD2
+#define EDBG_SPI_SERCOM_PINMUX_PAD3  PINMUX_PB23D_SERCOM5_PAD3
+#define EDBG_SPI_SERCOM_DMAC_ID_TX   SERCOM5_DMAC_ID_TX
+#define EDBG_SPI_SERCOM_DMAC_ID_RX   SERCOM5_DMAC_ID_RX
+/** @} */
+
+/** \name Embedded debugger CDC Gateway USART interface definitions
+ * @{
+ */
+#define EDBG_CDC_MODULE              SERCOM0
+#define EDBG_CDC_SERCOM_MUX_SETTING  USART_RX_1_TX_0_XCK_1
+#define EDBG_CDC_SERCOM_PINMUX_PAD0  PINMUX_PA04D_SERCOM0_PAD0
+#define EDBG_CDC_SERCOM_PINMUX_PAD1  PINMUX_PA05D_SERCOM0_PAD1
+#define EDBG_CDC_SERCOM_PINMUX_PAD2  PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_PINMUX_PAD3  PINMUX_UNUSED
+#define EDBG_CDC_SERCOM_DMAC_ID_TX   SERCOM0_DMAC_ID_TX
+#define EDBG_CDC_SERCOM_DMAC_ID_RX   SERCOM0_DMAC_ID_RX
+/** @} */
+
+/** \name USB definitions
+ * @{
+ */
+#define USB_ID
+#define USB_TARGET_DP_PIN            PIN_PA25G_USB_DP
+#define USB_TARGET_DP_MUX            MUX_PA25G_USB_DP
+#define USB_TARGET_DP_PINMUX         PINMUX_PA25G_USB_DP
+#define USB_TARGET_DM_PIN            PIN_PA24G_USB_DM
+#define USB_TARGET_DM_MUX            MUX_PA24G_USB_DM
+#define USB_TARGET_DM_PINMUX         PINMUX_PA24G_USB_DM
+#define USB_VBUS_PIN                 PIN_PA07
+#define USB_VBUS_EIC_LINE            7
+#define USB_VBUS_EIC_MUX             MUX_PA07A_EIC_EXTINT7
+#define USB_VBUS_EIC_PINMUX          PINMUX_PA07A_EIC_EXTINT7
+#define USB_ID_PIN                   PIN_PA15
+#define USB_ID_EIC_LINE              15
+#define USB_ID_EIC_MUX               MUX_PA15A_EIC_EXTINT15
+#define USB_ID_EIC_PINMUX            PINMUX_PA15A_EIC_EXTINT15
+
+#define SX_RF_SPI                  SERCOM4
+#define SX_RF_RESET_PIN            PIN_PB15
+#define SX_RF_SPI_CS               PIN_PB31
+#define SX_RF_SPI_MOSI             PIN_PB30
+#define SX_RF_SPI_MISO             PIN_PC19
+#define SX_RF_SPI_SCK              PIN_PC18
+
+#define SX_RF_SPI_SERCOM_MUX_SETTING   SPI_SIGNAL_MUX_SETTING_E
+#define SX_RF_SPI_SERCOM_PINMUX_PAD0   PINMUX_PC19F_SERCOM4_PAD0
+#define SX_RF_SPI_SERCOM_PINMUX_PAD1   PINMUX_UNUSED
+#define SX_RF_SPI_SERCOM_PINMUX_PAD2   PINMUX_PB30F_SERCOM4_PAD2
+#define SX_RF_SPI_SERCOM_PINMUX_PAD3   PINMUX_PC18F_SERCOM4_PAD3
+
+#define DIO0_PIN                   PIN_PB16
+#define DIO0_ACTIVE                true
+#define DIO0_INACTIVE              !DIO0_ACTIVE
+#define DIO0_EIC_PIN               PIN_PB16A_EIC_EXTINT0
+#define DIO0_EIC_MUX               MUX_PB16A_EIC_EXTINT0
+#define DIO0_EIC_PINMUX            PINMUX_PB16A_EIC_EXTINT0
+#define DIO0_EIC_LINE              0 
+
+#define DIO1_PIN                   PIN_PA11
+#define DIO1_ACTIVE                true
+#define DIO1_INACTIVE              !DIO1_ACTIVE
+#define DIO1_EIC_PIN               PIN_PA11A_EIC_EXTINT11
+#define DIO1_EIC_MUX               MUX_PA11A_EIC_EXTINT11
+#define DIO1_EIC_PINMUX            PINMUX_PA11A_EIC_EXTINT11
+#define DIO1_EIC_LINE              11
+
+#define DIO2_PIN                   PIN_PA12
+#define DIO2_ACTIVE                true
+#define DIO2_INACTIVE              !DIO2_ACTIVE
+#define DIO2_EIC_PIN               PIN_PA12A_EIC_EXTINT12
+#define DIO2_EIC_MUX               MUX_PA12A_EIC_EXTINT12
+#define DIO2_EIC_PINMUX            PINMUX_PA12A_EIC_EXTINT12
+#define DIO2_EIC_LINE              12
+
+#define DIO3_PIN                   PIN_PB17
+#define DIO3_ACTIVE                true
+#define DIO3_INACTIVE              !DIO3_ACTIVE
+#define DIO3_EIC_PIN               PIN_PB17A_EIC_EXTINT1
+#define DIO3_EIC_MUX               MUX_PB17A_EIC_EXTINT1
+#define DIO3_EIC_PINMUX            PINMUX_PB17A_EIC_EXTINT1
+#define DIO3_EIC_LINE              1
+
+#define DIO4_PIN                   PIN_PA10
+#define DIO4_ACTIVE                true
+#define DIO4_INACTIVE              !DIO4_ACTIVE
+#define DIO4_EIC_PIN               PIN_PA10A_EIC_EXTINT10
+#define DIO4_EIC_MUX               MUX_PA10A_EIC_EXTINT10
+#define DIO4_EIC_PINMUX            PINMUX_PA10A_EIC_EXTINT10
+#define DIO4_EIC_LINE              10
+
+#define DIO5_PIN                   PIN_PB00
+#define DIO5_ACTIVE                true
+#define DIO5_INACTIVE              !DIO5_ACTIVE
+#define DIO5_EIC_PIN               PIN_PB00A_EIC_EXTINT0
+#define DIO5_EIC_MUX               MUX_PB00A_EIC_EXTINT0
+#define DIO5_EIC_PINMUX            PINMUX_PB00A_EIC_EXTINT0
+#define DIO5_EIC_LINE              0
+
+#define SX_RF_RESET_HIGH		   true
+#define SX_RF_RESET_LOW		       !SX_RF_RESET_HIGH
+
+/** @} */
+
+/**
+ * \brief Turns off the specified LEDs.
+ *
+ * \param led_gpio LED to turn off (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Off(led_gpio)     port_pin_set_output_level(led_gpio,true)
+
+/**
+ * \brief Turns on the specified LEDs.
+ *
+ * \param led_gpio LED to turn on (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_On(led_gpio)      port_pin_set_output_level(led_gpio,false)
+
+/**
+ * \brief Toggles the specified LEDs.
+ *
+ * \param led_gpio LED to toggle (LEDx_GPIO).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+#define LED_Toggle(led_gpio)  port_pin_toggle_output_level(led_gpio)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* SAMR34_SENDCOMM_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/adc/adc_callback.h

@@ -0,0 +1,172 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef ADC_CALLBACK_H_INCLUDED
+#define ADC_CALLBACK_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_adc_group
+ *
+ * @{
+ */
+
+#include <adc.h>
+
+/**
+ * Enum for the possible types of ADC asynchronous jobs that may be issued to
+ * the driver.
+ */
+enum adc_job_type {
+	/** Asynchronous ADC read into a user provided buffer */
+	ADC_JOB_READ_BUFFER,
+};
+
+/**
+ * \name Callback Management
+ * @{
+ */
+void adc_register_callback(
+		struct adc_module *const module,
+		adc_callback_t callback_func,
+		enum adc_callback callback_type);
+
+void adc_unregister_callback(
+		struct adc_module *module,
+		enum adc_callback callback_type);
+
+/**
+ * \brief Enables callback.
+ *
+ * Enables the callback function registered by \ref
+ * adc_register_callback. The callback function will be called from the
+ * interrupt handler when the conditions for the callback type are met.
+ *
+ * \param[in]     module Pointer to ADC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return    Status of the operation.
+ * \retval     STATUS_OK              If operation was completed
+ * \retval     STATUS_ERR_INVALID     If operation was not completed,
+ *                                    due to invalid callback_type
+ *
+ */
+static inline void adc_enable_callback(
+		struct adc_module *const module,
+		enum adc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->enabled_callback_mask |= (1 << callback_type);
+
+	/* Enable window interrupt if this is a window callback */
+	if (callback_type == ADC_CALLBACK_WINDOW) {
+		adc_enable_interrupt(module, ADC_INTERRUPT_WINDOW);
+	}
+	/* Enable overrun interrupt if error callback is registered */
+	if (callback_type == ADC_CALLBACK_ERROR) {
+		adc_enable_interrupt(module, ADC_INTERRUPT_OVERRUN);
+	}
+}
+
+/**
+ * \brief Disables callback.
+ *
+ * Disables the callback function registered by the \ref
+ * adc_register_callback.
+ *
+ * \param[in]     module Pointer to ADC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ *
+ * \return    Status of the operation.
+ * \retval     STATUS_OK              If operation was completed
+ * \retval     STATUS_ERR_INVALID     If operation was not completed,
+ *                                    due to invalid callback_type
+ *
+ */
+static inline void adc_disable_callback(
+		struct adc_module *const module,
+		enum adc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	module->enabled_callback_mask &= ~(1 << callback_type);
+
+	/* Disable window interrupt if this is a window callback */
+	if (callback_type == ADC_CALLBACK_WINDOW) {
+		adc_disable_interrupt(module, ADC_INTERRUPT_WINDOW);
+	}
+	/* Disable overrun interrupt if this is the error callback */
+	if (callback_type == ADC_CALLBACK_ERROR) {
+		adc_disable_interrupt(module, ADC_INTERRUPT_OVERRUN);
+	}
+}
+
+/** @} */
+
+
+/**
+ * \name Job Management
+ * @{
+ */
+enum status_code adc_read_buffer_job(
+		struct adc_module *const module_inst,
+		uint16_t *buffer,
+		uint16_t samples);
+
+enum status_code adc_get_job_status(
+		struct adc_module *module_inst,
+		enum adc_job_type type);
+
+void adc_abort_job(
+		struct adc_module *module_inst,
+		enum adc_job_type type);
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ADC_CALLBACK_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/adc/adc_sam_l_c/adc.c

@@ -0,0 +1,830 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (c) 2014-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "adc.h"
+#if (ADC_INST_NUM > 1) || (SAMC20)
+
+#  define _ADC_GCLK_ID(n,unused)           TPASTE3(ADC,n,_GCLK_ID),
+#  define _ADC_APBCMASK(n,unused)          TPASTE2(MCLK_APBCMASK_ADC,n),
+
+#  define _ADC_FUSES_BIASCOMP_ADDR(n,unused)        TPASTE3(ADC,n,_FUSES_BIASCOMP_ADDR),
+#  define _ADC_FUSES_BIASCOMP_Pos(n,unused)         TPASTE3(ADC,n,_FUSES_BIASCOMP_Pos),
+#  define _ADC_FUSES_BIASREFBUF_ADDR(n,unused)      TPASTE3(ADC,n,_FUSES_BIASREFBUF_ADDR),
+#  define _ADC_FUSES_BIASREFBUF_Pos(n,unused)       TPASTE3(ADC,n,_FUSES_BIASREFBUF_Pos),
+#  define _ADC_EXTCHANNEL_MSB(n,unused)             TPASTE3(ADC,n,_EXTCHANNEL_MSB),
+
+#  define ADC_GCLK_ID       MREPEAT(ADC_INST_NUM, _ADC_GCLK_ID, 0)
+#  define ADC_APBCMASKS     MREPEAT(ADC_INST_NUM, _ADC_APBCMASK, 0)
+
+#  define ADC_FUSES_BIASCOMP_ADDR     MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASCOMP_ADDR, 0)
+#  define ADC_FUSES_BIASCOMP_Pos      MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASCOMP_Pos, 0)
+#  define ADC_FUSES_BIASREFBUF_ADDR   MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASREFBUF_ADDR, 0)
+#  define ADC_FUSES_BIASREFBUF_Pos    MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASREFBUF_Pos, 0)
+#  define ADC_EXTCHANNEL_MSB          MREPEAT(ADC_INST_NUM, _ADC_EXTCHANNEL_MSB, 0)
+
+#endif
+
+/* List of ADC GCLK IDs */
+const uint8_t _adc_gclk_ids[ADC_INST_NUM] = { ADC_GCLK_ID };
+
+/* List of ADC APB Masks */
+#if (ADC_INST_NUM > 1) || (SAMC20)
+const uint32_t _adc_apbcmasks[ADC_INST_NUM] = { ADC_APBCMASKS };
+#endif
+
+/* List of Number of external channels of ADC modules. */
+const uint32_t _adc_extchannel_msb[ADC_INST_NUM] = { ADC_EXTCHANNEL_MSB };
+
+/* List of address of comparator scaling of ADC modules. */
+const uint32_t _adc_biascomp_addr[ADC_INST_NUM] = { ADC_FUSES_BIASCOMP_ADDR };
+
+/* List of address of bias reference buffer scaling of ADC modules. */
+const uint32_t _adc_biasrefbuf_addr[ADC_INST_NUM] = { ADC_FUSES_BIASREFBUF_ADDR };
+
+/* List of offset of comparator scaling of ADC modules. */
+const uint8_t _adc_biascomp_pos[ADC_INST_NUM] = { ADC_FUSES_BIASCOMP_Pos };
+
+/* List of offset of bias reference buffer scaling of ADC modules. */
+const uint8_t _adc_biasrefbuf_pos[ADC_INST_NUM] = { ADC_FUSES_BIASREFBUF_Pos };
+
+
+/**
+ * \internal Find the index of given ADC module instance.
+ *
+ * \param[in] ADC module instance pointer.
+ *
+ * \return Index of the given ADC module instance.
+ */
+uint8_t _adc_get_inst_index(
+		Adc *const hw)
+{
+	/* List of available ADC modules. */
+	Adc *const adc_modules[ADC_INST_NUM] = ADC_INSTS;
+
+	/* Find index for ADC instance. */
+	for (uint32_t i = 0; i < ADC_INST_NUM; i++) {
+		if (hw == adc_modules[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given. */
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \brief Initializes an ADC configuration structure to defaults.
+ *
+ * Initializes a given ADC configuration struct to a set of known default
+ * values. This function should be called on any new instance of the
+ * configuration struct before being modified by the user application.
+ *
+ * The default configuration is as follows:
+ *  \li GCLK generator 0 (GCLK main) clock source
+ *  \li Internal bandgap reference
+ *  \li Div 2 clock prescaler
+ *  \li 12-bit resolution
+ *  \li Window monitor disabled
+ *  \li Positive input on ADC PIN 1
+ *  \li Negative input on Internal ground
+ *  \li Averaging disabled
+ *  \li Oversampling disabled
+ *  \li Right adjust data
+ *  \li Single-ended mode
+ *  \li Free running disabled
+ *  \li All events (input and generation) disabled
+ *  \li ADC run in standby disabled
+ *  \li ADC On demand disabled
+ *  \li No sampling time compensation
+ *  \li Disable the positive input sequense
+ *  \li No reference compensation
+ *  \li No gain/offset correction
+ *  \li No added sampling time
+ *
+ * \param[out] config  Pointer to configuration struct to initialize to
+ *                     default values
+ */
+void adc_get_config_defaults(struct adc_config *const config)
+{
+	Assert(config);
+	config->clock_source                  = GCLK_GENERATOR_0;
+	config->reference                     = ADC_REFERENCE_INTREF;
+	config->clock_prescaler               = ADC_CLOCK_PRESCALER_DIV2;
+	config->resolution                    = ADC_RESOLUTION_12BIT;
+	config->window.window_mode            = ADC_WINDOW_MODE_DISABLE;
+	config->window.window_upper_value     = 0;
+	config->window.window_lower_value     = 0;
+#if SAMR30 || SAMR34 || SAMR35 || (WLR089)
+	config->positive_input                = ADC_POSITIVE_INPUT_PIN6;
+#else
+	config->positive_input                = ADC_POSITIVE_INPUT_PIN1;
+#endif
+	config->negative_input                = ADC_NEGATIVE_INPUT_GND;
+	config->accumulate_samples            = ADC_ACCUMULATE_DISABLE;
+	config->divide_result                 = ADC_DIVIDE_RESULT_DISABLE;
+	config->left_adjust                   = false;
+	config->differential_mode             = false;
+	config->freerunning                   = false;
+	config->event_action                  = ADC_EVENT_ACTION_DISABLED;
+	config->run_in_standby                = false;
+	config->on_demand                     = false;
+	config->sampling_time_compensation_enable  = false;
+	config->positive_input_sequence_mask_enable = 0;
+	config->reference_compensation_enable = false;
+	config->correction.correction_enable  = false;
+	config->correction.gain_correction    = ADC_GAINCORR_RESETVALUE;
+	config->correction.offset_correction  = ADC_OFFSETCORR_RESETVALUE;
+	config->sample_length                 = 0;
+}
+
+/**
+ * \brief Sets the ADC window mode.
+ *
+ * Sets the ADC window mode to a given mode and value range.
+ *
+ * \param[in] module_inst         Pointer to the ADC software instance struct
+ * \param[in] window_mode         Window monitor mode to set
+ * \param[in] window_lower_value  Lower window monitor threshold value
+ * \param[in] window_upper_value  Upper window monitor threshold value
+  */
+void adc_set_window_mode(
+		struct adc_module *const module_inst,
+		const enum adc_window_mode window_mode,
+		const int16_t window_lower_value,
+		const int16_t window_upper_value)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	Adc *const adc_module = module_inst->hw;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set window mode */
+	uint32_t ctrlc = adc_module->CTRLC.reg;
+	ctrlc = (ctrlc & (~ADC_CTRLC_WINMODE_Msk)) | window_mode;
+	adc_module->CTRLC.reg = ctrlc;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set lower window monitor threshold value */
+	adc_module->WINLT.reg = window_lower_value;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set upper window monitor threshold value */
+	adc_module->WINUT.reg = window_upper_value;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+* \internal Configure MUX settings for the analog pins.
+*
+* This function will set the given ADC input pins
+* to the analog function in the pin mux, giving
+* the ADC access to the analog signal.
+*
+* \param [in] index   Index of the ADC module instance.
+* \param [in] pin     AINxx pin to configure
+*/
+static inline void _adc_configure_ain_pin(uint8_t index, uint32_t pin)
+{
+#define PIN_INVALID_ADC_AIN    0xFFFFUL
+
+	/* Pinmapping table for AINxx -> GPIO pin number */
+#if (SAML21) || (SAML22) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	const uint32_t pinmapping[] = {
+#if (SAML21E)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,			
+#elif (SAMR30E)
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA06B_ADC_AIN6,  PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAML21G) || (SAMR30G) || (SAMR34J) || (SAMR35J) || (WLR089U0)
+#if !(SAMR30 || SAMR34 || SAMR35 || (WLR089)) 
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+#endif
+#if (SAMR34JXXB) || (SAMR35JXXB) || (WLR089U0)
+			PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+#else
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+#endif
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+#if (SAMR34JXXB) || (SAMR35JXXB) || (WLR089U0)
+			PIN_PB00B_ADC_AIN8,  PIN_INVALID_ADC_AIN,
+#else
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#endif
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAML21J)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAML22G)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAML22J)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#elif (SAML22N)
+			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+			PIN_PC00B_ADC_AIN16, PIN_PC01B_ADC_AIN17,
+			PIN_PC02B_ADC_AIN18, PIN_PC03B_ADC_AIN19,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+#   else
+#       error ADC pin mappings are not defined for this device.
+#   endif
+	};
+#elif (SAMC20)
+	const uint32_t pinmapping[] = {
+#   if (SAMC20E)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   elif (SAMC20G)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   elif (SAMC20J)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   else
+#       error ADC pin mappings are not defined for this device.
+#   endif
+	};
+#elif (SAMC21)
+	const uint32_t *pinmapping = NULL;;
+	const uint32_t pinmapping0[] = {
+#   if (SAMC21E)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   elif (SAMC21G)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   elif (SAMC21J)
+			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+#   else
+#       error ADC pin mappings are not defined for this device.
+#   endif
+		};
+	const uint32_t pinmapping1[] = {
+#   if (SAMC21E)
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
+#   elif (SAMC21G)
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_PB02B_ADC1_AIN2,  PIN_PB03B_ADC1_AIN3,
+		PIN_PB08B_ADC1_AIN4,  PIN_PB09B_ADC1_AIN5,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+		PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
+#   elif (SAMC21J)
+		PIN_PB00B_ADC1_AIN0,  PIN_PB01B_ADC1_AIN1,
+		PIN_PB02B_ADC1_AIN2,  PIN_PB03B_ADC1_AIN3,
+		PIN_PB08B_ADC1_AIN4,  PIN_PB09B_ADC1_AIN5,
+		PIN_PB04B_ADC1_AIN6,  PIN_PB05B_ADC1_AIN7,
+		PIN_PB06B_ADC1_AIN8,  PIN_PB07B_ADC1_AIN9,
+		PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
+#   else
+#       error ADC pin mappings are not defined for this device.
+#   endif
+	};
+
+	switch(index) {
+	case 0:
+		pinmapping = pinmapping0;
+		break;
+	case 1:
+		pinmapping = pinmapping1;
+		break;
+	default:
+		break;
+	}
+	Assert(pinmapping);
+#endif
+
+	uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
+
+	if (pin <= _adc_extchannel_msb[index]) {
+		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
+
+		Assert(pin_map_result != PIN_INVALID_ADC_AIN);
+
+		struct system_pinmux_config config;
+		system_pinmux_get_config_defaults(&config);
+
+		/* Analog functions are all on MUX setting B */
+		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+		config.mux_position = 1;
+
+		system_pinmux_pin_set_config(pin_map_result, &config);
+	}
+}
+
+/**
+ * \internal Writes an ADC configuration to the hardware module.
+ *
+ * Writes out a given ADC module configuration to the hardware module.
+ *
+ * \param[in]  index        Index of the ADC module instance
+ * \param[out] module_inst  Pointer to the ADC software instance struct
+ * \param[in]  config       Pointer to configuration struct
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               The configuration was successful
+ * \retval STATUS_ERR_INVALID_ARG  Invalid argument(s) were provided
+ */
+static enum status_code _adc_set_config(
+		uint8_t index,
+		struct adc_module *const module_inst,
+		struct adc_config *const config)
+{
+	uint8_t adjres = 0;
+	uint32_t resolution = ADC_RESOLUTION_16BIT;
+	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
+
+	/* Get the hardware module pointer */
+	Adc *const adc_module = module_inst->hw;
+
+	/* Configure GCLK channel and enable clock */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->clock_source;
+	system_gclk_chan_set_config(_adc_gclk_ids[index], &gclk_chan_conf);
+	system_gclk_chan_enable(_adc_gclk_ids[index]);
+
+	/* Setup pinmuxing for analog inputs */
+	_adc_configure_ain_pin(index, config->positive_input);
+	_adc_configure_ain_pin(index, config->negative_input);
+
+	/* Set pinmux for positive input sequence*/
+	for(uint8_t i=0;i <= _adc_extchannel_msb[index];i++){
+		if(config->positive_input_sequence_mask_enable & (1 << i)){
+			_adc_configure_ain_pin(index, i);
+		}
+	}
+
+	/* Configure run in standby and on demand */
+	adc_module->CTRLA.reg = ((config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos)
+						    | (config->on_demand << ADC_CTRLA_ONDEMAND_Pos)) ;
+
+	/* Configure reference */
+	adc_module->REFCTRL.reg =
+			(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos)
+			| (config->reference);
+
+	/* Set adjusting result and number of samples */
+	switch (config->resolution) {
+
+	case ADC_RESOLUTION_CUSTOM:
+		adjres = config->divide_result;
+		accumulate = config->accumulate_samples;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_13BIT:
+		/* Increase resolution by 1 bit */
+		adjres = ADC_DIVIDE_RESULT_2;
+		accumulate = ADC_ACCUMULATE_SAMPLES_4;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_14BIT:
+		/* Increase resolution by 2 bit */
+		adjres = ADC_DIVIDE_RESULT_4;
+		accumulate = ADC_ACCUMULATE_SAMPLES_16;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+	case ADC_RESOLUTION_15BIT:
+		/* Increase resolution by 3 bit */
+		adjres = ADC_DIVIDE_RESULT_2;
+		accumulate = ADC_ACCUMULATE_SAMPLES_64;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+
+	case ADC_RESOLUTION_16BIT:
+		/* Increase resolution by 4 bit */
+		adjres = ADC_DIVIDE_RESULT_DISABLE;
+		accumulate = ADC_ACCUMULATE_SAMPLES_256;
+		/* 16-bit result register */
+		resolution = ADC_RESOLUTION_16BIT;
+		break;
+	case ADC_RESOLUTION_8BIT:
+		/* 8-bit result register */
+		resolution = ADC_RESOLUTION_8BIT;
+		break;
+	case ADC_RESOLUTION_10BIT:
+		/* 10-bit result register */
+		resolution = ADC_RESOLUTION_10BIT;
+		break;
+	case ADC_RESOLUTION_12BIT:
+		/* 12-bit result register */
+		resolution = ADC_RESOLUTION_12BIT;
+		break;
+
+	default:
+		/* Unknown. Abort. */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Check validity of sample length value */
+	if (config->sample_length > 63) {
+		return STATUS_ERR_INVALID_ARG;
+	} else {
+		/* Configure sample length */
+		adc_module->SAMPCTRL.reg =
+				(config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos)
+				| (config->sampling_time_compensation_enable << ADC_SAMPCTRL_OFFCOMP_Pos);
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure CTRLB */
+	adc_module->CTRLB.reg =
+			config->clock_prescaler;
+	adc_module->CTRLC.reg =
+			resolution |
+			(config->correction.correction_enable << ADC_CTRLC_CORREN_Pos) |
+			(config->freerunning << ADC_CTRLC_FREERUN_Pos) |
+			(config->left_adjust << ADC_CTRLC_LEFTADJ_Pos) |
+			(config->differential_mode << ADC_CTRLC_DIFFMODE_Pos);
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Check validity of window thresholds */
+	if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
+		switch (resolution) {
+		case ADC_RESOLUTION_8BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 127 ||
+					config->window.window_lower_value < -128 ||
+					config->window.window_upper_value > 127 ||
+					config->window.window_upper_value < -128)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 255 ||
+					config->window.window_upper_value > 255){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_10BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 511 ||
+					config->window.window_lower_value < -512 ||
+					config->window.window_upper_value > 511 ||
+					config->window.window_upper_value < -512)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 1023 ||
+					config->window.window_upper_value > 1023){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_12BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 2047 ||
+					config->window.window_lower_value < -2048 ||
+					config->window.window_upper_value > 2047 ||
+					config->window.window_upper_value < -2048)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 4095 ||
+					config->window.window_upper_value > 4095){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case ADC_RESOLUTION_16BIT:
+			if (config->differential_mode &&
+					(config->window.window_lower_value > 32767 ||
+					config->window.window_lower_value < -32768 ||
+					config->window.window_upper_value > 32767 ||
+					config->window.window_upper_value < -32768)) {
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			} else if (config->window.window_lower_value > 65535 ||
+					config->window.window_upper_value > 65535){
+				/* Invalid value */
+				return STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		}
+	}
+
+	/* Configure window mode */
+	adc_module->CTRLC.reg |= config->window.window_mode;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure lower threshold */
+	adc_module->WINLT.reg =
+			config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure lower threshold */
+	adc_module->WINUT.reg = config->window.window_upper_value <<
+			ADC_WINUT_WINUT_Pos;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure pin scan mode and positive and negative input pins */
+	adc_module->INPUTCTRL.reg =
+			config->negative_input |
+			config->positive_input;
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	/* Configure events */
+	adc_module->EVCTRL.reg = config->event_action;
+
+	/* Disable all interrupts */
+	adc_module->INTENCLR.reg =
+			(1 << ADC_INTENCLR_WINMON_Pos) |(1 << ADC_INTENCLR_OVERRUN_Pos)
+			| (1 << ADC_INTENCLR_RESRDY_Pos);
+
+	if (config->correction.correction_enable){
+		/* Make sure gain_correction value is valid */
+		if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
+			return STATUS_ERR_INVALID_ARG;
+		} else {
+			/* Set gain correction value */
+			adc_module->GAINCORR.reg = config->correction.gain_correction <<
+					ADC_GAINCORR_GAINCORR_Pos;
+		}
+
+		while (adc_is_syncing(module_inst)) {
+			/* Wait for synchronization */
+		}
+
+		/* Make sure offset correction value is valid */
+		if (config->correction.offset_correction > 2047 ||
+				config->correction.offset_correction < -2048) {
+			return STATUS_ERR_INVALID_ARG;
+		} else {
+			/* Set offset correction value */
+			adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
+					ADC_OFFSETCORR_OFFSETCORR_Pos;
+		}
+
+		while (adc_is_syncing(module_inst)) {
+			/* Wait for synchronization */
+		}
+	}
+
+	/* Load in the fixed device ADC calibration constants */
+	adc_module->CALIB.reg =
+			ADC_CALIB_BIASREFBUF(
+				(*(uint32_t *)_adc_biasrefbuf_addr[index] >> _adc_biasrefbuf_pos[index])
+			) |
+			ADC_CALIB_BIASCOMP(
+				(*(uint32_t *)_adc_biascomp_addr[index] >> _adc_biascomp_pos[index])
+			);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the ADC.
+ *
+ * Initializes the ADC device struct and the hardware module based on the
+ * given configuration struct values.
+ *
+ * \param[out] module_inst Pointer to the ADC software instance struct
+ * \param[in]  hw          Pointer to the ADC module instance
+ * \param[in]  config      Pointer to the configuration struct
+ *
+ * \return Status of the initialization procedure.
+ * \retval STATUS_OK                The initialization was successful
+ * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) were provided
+ * \retval STATUS_BUSY          The module is busy with a reset operation
+ * \retval STATUS_ERR_DENIED        The module is enabled
+ */
+enum status_code adc_init(
+		struct adc_module *const module_inst,
+		Adc *hw,
+		struct adc_config *config)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(hw);
+	Assert(config);
+
+	/* Temporary variable to hold ADC instance number */
+	uint8_t instance = _adc_get_inst_index(hw);
+
+	/* Associate the software module instance with the hardware module */
+	module_inst->hw = hw;
+#if (SAML22)
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_ADC);
+#elif (SAML21) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_ADC);
+#else
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, _adc_apbcmasks[instance]);
+#endif
+
+	if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
+		/* We are in the middle of a reset. Abort. */
+		return STATUS_BUSY;
+	}
+
+	while (adc_is_syncing(module_inst)) {
+		/* Wait for synchronization */
+	}
+
+	if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
+		/* Module must be disabled before initialization. Abort. */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Store the selected reference for later use */
+	module_inst->reference = config->reference;
+
+	/* Make sure the voltage reference is enabled if requested by the config */
+	if (module_inst->reference == ADC_REFERENCE_INTREF) {
+		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
+	}
+
+#if ADC_CALLBACK_MODE == true
+	for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
+		module_inst->callback[i] = NULL;
+	};
+
+	module_inst->registered_callback_mask = 0;
+	module_inst->enabled_callback_mask = 0;
+	module_inst->remaining_conversions = 0;
+	module_inst->job_status = STATUS_OK;
+
+	_adc_instances[instance] = module_inst;
+
+	if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
+			!config->freerunning) {
+		module_inst->software_trigger = true;
+	} else {
+		module_inst->software_trigger = false;
+	}
+#endif
+
+	/* Write configuration to module */
+	return _adc_set_config(instance, module_inst, config);
+}

firmware/SendcommCmdsys/src/ASF/sam0/drivers/adc/adc_sam_l_c/adc_callback.c

@@ -0,0 +1,254 @@
+/**
+ * \file
+ *
+ * \brief SAM Peripheral Analog-to-Digital Converter Driver
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "adc_callback.h"
+
+struct adc_module *_adc_instances[ADC_INST_NUM];
+
+static void _adc_interrupt_handler(const uint8_t instance)
+{
+	struct adc_module *module = _adc_instances[instance];
+
+	/* get interrupt flags and mask out enabled callbacks */
+	uint32_t flags = module->hw->INTFLAG.reg & module->hw->INTENSET.reg;
+
+	if (flags & ADC_INTFLAG_RESRDY) {
+		/* clear interrupt flag */
+		module->hw->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+
+		/* store ADC result in job buffer */
+		*(module->job_buffer++) = module->hw->RESULT.reg;
+
+		if (--module->remaining_conversions > 0) {
+			if (module->software_trigger == true
+				&& (!(module->hw->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY))) {
+				adc_start_conversion(module);
+			}
+		} else {
+			adc_disable_interrupt(module, ADC_INTERRUPT_RESULT_READY);
+			if (module->job_status == STATUS_BUSY) {
+				/* job is complete. update status,disable interrupt
+				 *and call callback */
+				module->job_status = STATUS_OK;
+
+				if ((module->enabled_callback_mask &
+						(1 << ADC_CALLBACK_READ_BUFFER)) &&
+					(module->registered_callback_mask &
+						(1 << ADC_CALLBACK_READ_BUFFER))) {
+					(module->callback[ADC_CALLBACK_READ_BUFFER])(module);
+				}
+			}
+		}
+	}
+
+	if (flags & ADC_INTFLAG_WINMON) {
+		module->hw->INTFLAG.reg = ADC_INTFLAG_WINMON;
+		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_WINDOW)) &&
+				(module->registered_callback_mask & (1 << ADC_CALLBACK_WINDOW))) {
+			(module->callback[ADC_CALLBACK_WINDOW])(module);
+		}
+
+	}
+
+	if (flags & ADC_INTFLAG_OVERRUN) {
+		module->hw->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_ERROR)) &&
+				(module->registered_callback_mask & (1 << ADC_CALLBACK_ERROR))) {
+			(module->callback[ADC_CALLBACK_ERROR])(module);
+		}
+	}
+}
+
+/** Interrupt handler for the ADC module. */
+#if (ADC_INST_NUM > 1) || (SAMC20)
+#   define _ADC_INTERRUPT_HANDLER(n, m) \
+		void ADC##n##_Handler(void) \
+		{ \
+			_adc_interrupt_handler(n); \
+		}
+
+	MREPEAT(ADC_INST_NUM, _ADC_INTERRUPT_HANDLER, 0)
+#else
+void ADC_Handler(void)
+{
+	_adc_interrupt_handler(0);
+}
+#endif
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled for the interrupt handler to call it
+ * when the condition for the callback is met.
+ *
+ * \param[in] module         Pointer to ADC software instance struct
+ * \param[in] callback_func  Pointer to callback function
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+void adc_register_callback(
+		struct adc_module *const module,
+		adc_callback_t callback_func,
+		enum adc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->registered_callback_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters a callback function which is implemented by the user.
+ *
+ * \param[in] module         Pointer to ADC software instance struct
+ * \param[in] callback_type  Callback type given by an enum
+ *
+ */
+void adc_unregister_callback(
+		struct adc_module *const module,
+		enum adc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->registered_callback_mask &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Read multiple samples from ADC.
+ *
+ * Read \c samples from the ADC into the \c buffer.
+ * If there is no hardware trigger defined (event action) the
+ * driver will retrigger the ADC conversion whenever a conversion
+ * is complete until \c samples has been acquired. To avoid
+ * jitter in the sampling frequency using an event trigger is advised.
+ *
+ * \param[in]  module_inst  Pointer to the ADC software instance struct
+ * \param[in]  samples      Number of samples to acquire
+ * \param[out] buffer       Buffer to store the ADC samples
+ *
+ * \return Status of the job start.
+ * \retval STATUS_OK        The conversion job was started successfully and is
+ *                          in progress
+ * \retval STATUS_BUSY      The ADC is already busy with another job
+ */
+enum status_code adc_read_buffer_job(
+		struct adc_module *const module_inst,
+		uint16_t *buffer,
+		uint16_t samples)
+{
+	Assert(module_inst);
+	Assert(samples);
+	Assert(buffer);
+
+	if(module_inst->remaining_conversions != 0 ||
+			module_inst->job_status == STATUS_BUSY){
+		return STATUS_BUSY;
+	}
+
+	module_inst->job_status = STATUS_BUSY;
+	module_inst->remaining_conversions = samples;
+	module_inst->job_buffer = buffer;
+
+	adc_enable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
+
+	if(module_inst->software_trigger == true) {
+		adc_start_conversion(module_inst);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Gets the status of a job.
+ *
+ * Gets the status of an ongoing or the last job.
+ *
+ * \param [in]  module_inst Pointer to the ADC software instance struct
+ * \param [in]  type        Type of to get status
+ *
+ * \return Status of the job.
+ */
+enum status_code adc_get_job_status(
+		struct adc_module *module_inst,
+		enum adc_job_type type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	if (type == ADC_JOB_READ_BUFFER ) {
+		return module_inst->job_status;
+	} else {
+		return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Aborts an ongoing job.
+ *
+ * Aborts an ongoing job.
+ *
+ * \param [in]  module_inst Pointer to the ADC software instance struct
+ * \param [in]  type        Type of job to abort
+ */
+void adc_abort_job(
+		struct adc_module *module_inst,
+		enum adc_job_type type)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	if (type == ADC_JOB_READ_BUFFER) {
+		/* Disable interrupt */
+		adc_disable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
+		/* Mark job as aborted */
+		module_inst->job_status = STATUS_ABORTED;
+		module_inst->remaining_conversions = 0;
+	}
+}
+

firmware/SendcommCmdsys/src/ASF/sam0/drivers/adc/adc_sam_l_c/adc_feature.h

@@ -0,0 +1,727 @@
+/**
+ * \file
+ *
+ * \brief SAM ADC functionality
+ *
+ * Copyright (c) 2014-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef ADC_FEATURE_H_INCLUDED
+#define ADC_FEATURE_H_INCLUDED
+
+/**
+ * \addtogroup asfdoc_sam0_adc_group
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*@{*/
+#if (SAMC20) || (SAMC21) || defined(__DOXYGEN__)
+/** Output Driver Strength Selection feature support. */
+#  define FEATURE_ADC_SUPPORT_MASTER_SLAVE
+#endif
+/*@}*/
+
+#if ADC_CALLBACK_MODE == true
+#  include <system_interrupt.h>
+
+#if !defined(__DOXYGEN__)
+extern struct adc_module *_adc_instances[ADC_INST_NUM];
+#endif
+
+/** Forward definition of the device instance. */
+struct adc_module;
+
+/** Type of the callback functions. */
+typedef void (*adc_callback_t)(struct adc_module *const module);
+
+/**
+ * \brief ADC callback enum.
+ *
+ * Callback types for ADC callback driver.
+ *
+ */
+enum adc_callback {
+	/** Callback for buffer received */
+	ADC_CALLBACK_READ_BUFFER,
+	/** Callback when window is hit */
+	ADC_CALLBACK_WINDOW,
+	/** Callback for error */
+	ADC_CALLBACK_ERROR,
+#  if !defined(__DOXYGEN__)
+	/** Number of available callbacks */
+	ADC_CALLBACK_N,
+#  endif
+};
+
+#endif
+
+/**
+ * \brief ADC reference voltage enum.
+ *
+ * Enum for the possible reference voltages for the ADC.
+ *
+ */
+enum adc_reference {
+	/** Internal Bandgap Reference */
+	ADC_REFERENCE_INTREF  = ADC_REFCTRL_REFSEL_INTREF,
+	/** 1/1.48V<SUB>CC</SUB> reference */
+	ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
+	/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */
+	ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
+	/** External reference A */
+	ADC_REFERENCE_AREFA   = ADC_REFCTRL_REFSEL_AREFA,
+#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	/** External reference B */
+	ADC_REFERENCE_AREFB   = ADC_REFCTRL_REFSEL_AREFB,
+#endif
+#if (SAMC20) || (SAMC21)
+	/** DAC */
+	ADC_REFERENCE_DAC     = ADC_REFCTRL_REFSEL_DAC,
+#endif
+	/** VDDANA */
+	ADC_REFERENCE_INTVCC2 = ADC_REFCTRL_REFSEL_INTVCC2,
+};
+
+/**
+ * \brief ADC clock prescaler enum.
+ *
+ * Enum for the possible clock prescaler values for the ADC.
+ *
+ */
+enum adc_clock_prescaler {
+	/** ADC clock division factor 2 */
+	ADC_CLOCK_PRESCALER_DIV2   = ADC_CTRLB_PRESCALER_DIV2,
+	/** ADC clock division factor 4 */
+	ADC_CLOCK_PRESCALER_DIV4   = ADC_CTRLB_PRESCALER_DIV4,
+	/** ADC clock division factor 8 */
+	ADC_CLOCK_PRESCALER_DIV8   = ADC_CTRLB_PRESCALER_DIV8,
+	/** ADC clock division factor 16 */
+	ADC_CLOCK_PRESCALER_DIV16  = ADC_CTRLB_PRESCALER_DIV16,
+	/** ADC clock division factor 32 */
+	ADC_CLOCK_PRESCALER_DIV32  = ADC_CTRLB_PRESCALER_DIV32,
+	/** ADC clock division factor 64 */
+	ADC_CLOCK_PRESCALER_DIV64  = ADC_CTRLB_PRESCALER_DIV64,
+	/** ADC clock division factor 128 */
+	ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
+	/** ADC clock division factor 256 */
+	ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
+};
+
+/**
+ * \brief ADC resolution enum.
+ *
+ * Enum for the possible resolution values for the ADC.
+ *
+ */
+enum adc_resolution {
+	/** ADC 12-bit resolution */
+	ADC_RESOLUTION_12BIT = ADC_CTRLC_RESSEL_12BIT,
+	/** ADC 16-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_16BIT = ADC_CTRLC_RESSEL_16BIT,
+	/** ADC 10-bit resolution */
+	ADC_RESOLUTION_10BIT = ADC_CTRLC_RESSEL_10BIT,
+	/** ADC 8-bit resolution */
+	ADC_RESOLUTION_8BIT  = ADC_CTRLC_RESSEL_8BIT,
+	/** ADC 13-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_13BIT,
+	/** ADC 14-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_14BIT,
+	/** ADC 15-bit resolution using oversampling and decimation */
+	ADC_RESOLUTION_15BIT,
+	/** ADC 16-bit result register for use with averaging. When using this mode
+	  * the ADC result register will be set to 16-bit wide, and the number of
+	  * samples to accumulate and the division factor is configured by the
+	  * \ref adc_config.accumulate_samples and \ref adc_config.divide_result
+	  * members in the configuration struct.
+	  */
+	ADC_RESOLUTION_CUSTOM,
+};
+
+/**
+ * \brief ADC window monitor mode enum.
+ *
+ * Enum for the possible window monitor modes for the ADC.
+ *
+ */
+enum adc_window_mode {
+	/** No window mode */
+	ADC_WINDOW_MODE_DISABLE          = ADC_CTRLC_WINMODE_DISABLE,
+	/** RESULT > WINLT */
+	ADC_WINDOW_MODE_ABOVE_LOWER      = ADC_CTRLC_WINMODE_MODE1,
+	/** RESULT < WINUT */
+	ADC_WINDOW_MODE_BELOW_UPPER      = ADC_CTRLC_WINMODE_MODE2,
+	/** WINLT < RESULT < WINUT */
+	ADC_WINDOW_MODE_BETWEEN          = ADC_CTRLC_WINMODE_MODE3,
+	/** !(WINLT < RESULT < WINUT) */
+	ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_CTRLC_WINMODE_MODE4,
+};
+
+/**
+ * \brief ADC event action enum.
+ *
+ * Enum for the possible actions to take on an incoming event.
+ *
+ */
+enum adc_event_action {
+	/** Event action disabled */
+	ADC_EVENT_ACTION_DISABLED         = 0,
+	/** Flush ADC and start conversion */
+	ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_FLUSHEI,
+	/** Start conversion */
+	ADC_EVENT_ACTION_START_CONV       = ADC_EVCTRL_STARTEI,
+};
+
+/**
+ * \brief ADC positive MUX input selection enum.
+ *
+ * Enum for the possible positive MUX input selections for the ADC.
+ *
+ */
+enum adc_positive_input {
+	/** ADC0 pin */
+	ADC_POSITIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXPOS_AIN0,
+	/** ADC1 pin */
+	ADC_POSITIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXPOS_AIN1,
+	/** ADC2 pin */
+	ADC_POSITIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXPOS_AIN2,
+	/** ADC3 pin */
+	ADC_POSITIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXPOS_AIN3,
+	/** ADC4 pin */
+	ADC_POSITIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXPOS_AIN4,
+	/** ADC5 pin */
+	ADC_POSITIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXPOS_AIN5,
+	/** ADC6 pin */
+	ADC_POSITIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXPOS_AIN6,
+	/** ADC7 pin */
+	ADC_POSITIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXPOS_AIN7,
+	/** ADC8 pin */
+	ADC_POSITIVE_INPUT_PIN8          = ADC_INPUTCTRL_MUXPOS_AIN8,
+	/** ADC9 pin */
+	ADC_POSITIVE_INPUT_PIN9          = ADC_INPUTCTRL_MUXPOS_AIN9,
+	/** ADC10 pin */
+	ADC_POSITIVE_INPUT_PIN10         = ADC_INPUTCTRL_MUXPOS_AIN10,
+	/** ADC11 pin */
+	ADC_POSITIVE_INPUT_PIN11         = ADC_INPUTCTRL_MUXPOS_AIN11,
+#if !(SAMC20) && !(SAMC21)
+	/** ADC12 pin */
+	ADC_POSITIVE_INPUT_PIN12         = ADC_INPUTCTRL_MUXPOS_AIN12,
+	/** ADC13 pin */
+	ADC_POSITIVE_INPUT_PIN13         = ADC_INPUTCTRL_MUXPOS_AIN13,
+	/** ADC14 pin */
+	ADC_POSITIVE_INPUT_PIN14         = ADC_INPUTCTRL_MUXPOS_AIN14,
+	/** ADC15 pin */
+	ADC_POSITIVE_INPUT_PIN15         = ADC_INPUTCTRL_MUXPOS_AIN15,
+	/** ADC16 pin */
+	ADC_POSITIVE_INPUT_PIN16         = ADC_INPUTCTRL_MUXPOS_AIN16,
+	/** ADC17 pin */
+	ADC_POSITIVE_INPUT_PIN17         = ADC_INPUTCTRL_MUXPOS_AIN17,
+	/** ADC18 pin */
+	ADC_POSITIVE_INPUT_PIN18         = ADC_INPUTCTRL_MUXPOS_AIN18,
+	/** ADC19 pin */
+	ADC_POSITIVE_INPUT_PIN19         = ADC_INPUTCTRL_MUXPOS_AIN19,
+#if !(SAML22 || SAMR30 || SAMR34 || SAMR35 || (WLR089))
+	/** ADC20 pin. */
+	ADC_POSITIVE_INPUT_PIN20         = ADC_INPUTCTRL_MUXPOS_AIN20,
+	/** ADC21 pin */
+	ADC_POSITIVE_INPUT_PIN21         = ADC_INPUTCTRL_MUXPOS_AIN21,
+	/** ADC22 pin */
+	ADC_POSITIVE_INPUT_PIN22         = ADC_INPUTCTRL_MUXPOS_AIN22,
+	/** ADC23 pin */
+	ADC_POSITIVE_INPUT_PIN23         = ADC_INPUTCTRL_MUXPOS_AIN23,
+#endif
+	/** Temperature reference. */
+	ADC_POSITIVE_INPUT_TEMP          = ADC_INPUTCTRL_MUXPOS_TEMP,
+#endif
+	/** Bandgap voltage */
+	ADC_POSITIVE_INPUT_BANDGAP       = ADC_INPUTCTRL_MUXPOS_BANDGAP,
+	/** 1/4 scaled core supply */
+	ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
+	/** 1/4 scaled I/O supply */
+	ADC_POSITIVE_INPUT_SCALEDIOVCC   = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
+#if !(SAML22|| SAMR30 || SAMR34 || SAMR35 || (WLR089))
+	/** DAC input */
+	ADC_POSITIVE_INPUT_DAC           = ADC_INPUTCTRL_MUXPOS_DAC,
+#endif
+
+#if (SAML21)
+	/** SCALEDVBAT */
+	ADC_POSITIVE_INPUT_SCALEDVBAT    = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT,
+	/** OPAMP01 */
+	ADC_POSITIVE_INPUT_OPAMP01       = ADC_INPUTCTRL_MUXPOS_OPAMP01,
+	/** OPAMP02 */
+	ADC_POSITIVE_INPUT_OPAMP2        = ADC_INPUTCTRL_MUXPOS_OPAMP2,
+#endif
+#if (SAML22)
+	/** SCALEDVBAT */
+	ADC_POSITIVE_INPUT_SCALEDVBAT    = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT,
+	/** CTAT. */
+	ADC_POSITIVE_INPUT_CTAT          = ADC_INPUTCTRL_MUXPOS_CTAT,
+#endif
+};
+
+/**
+ * \brief ADC negative MUX input selection enum.
+ *
+ * Enum for the possible negative MUX input selections for the ADC.
+ *
+ */
+enum adc_negative_input {
+	/** ADC0 pin */
+	ADC_NEGATIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXNEG_AIN0,
+	/** ADC1 pin */
+	ADC_NEGATIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXNEG_AIN1,
+	/** ADC2 pin */
+	ADC_NEGATIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXNEG_AIN2,
+	/** ADC3 pin */
+	ADC_NEGATIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXNEG_AIN3,
+	/** ADC4 pin */
+	ADC_NEGATIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXNEG_AIN4,
+	/** ADC5 pin */
+	ADC_NEGATIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXNEG_AIN5,
+#if !(SAMC20) && !(SAMC21) && !(SAMR30) && !(SAMR34) && !(SAMR35) && !(WLR089)
+	/** ADC6 pin */
+	ADC_NEGATIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXNEG_AIN6,
+	/** ADC7 pin */
+	ADC_NEGATIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXNEG_AIN7,
+#endif
+	/** Internal ground */
+	ADC_NEGATIVE_INPUT_GND           = ADC_INPUTCTRL_MUXNEG(0x18u),
+};
+
+/**
+ * \brief ADC number of accumulated samples enum.
+ *
+ * Enum for the possible numbers of ADC samples to accumulate.
+ * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM
+ * resolution setting is used.
+ *
+ */
+enum adc_accumulate_samples {
+	/** No averaging */
+	ADC_ACCUMULATE_DISABLE      = ADC_AVGCTRL_SAMPLENUM_1,
+	/** Average 2 samples */
+	ADC_ACCUMULATE_SAMPLES_2    = ADC_AVGCTRL_SAMPLENUM_2,
+	/** Average 4 samples */
+	ADC_ACCUMULATE_SAMPLES_4    = ADC_AVGCTRL_SAMPLENUM_4,
+	/** Average 8 samples */
+	ADC_ACCUMULATE_SAMPLES_8    = ADC_AVGCTRL_SAMPLENUM_8,
+	/** Average 16 samples */
+	ADC_ACCUMULATE_SAMPLES_16   = ADC_AVGCTRL_SAMPLENUM_16,
+	/** Average 32 samples */
+	ADC_ACCUMULATE_SAMPLES_32   = ADC_AVGCTRL_SAMPLENUM_32,
+	/** Average 64 samples */
+	ADC_ACCUMULATE_SAMPLES_64   = ADC_AVGCTRL_SAMPLENUM_64,
+	/** Average 128 samples */
+	ADC_ACCUMULATE_SAMPLES_128  = ADC_AVGCTRL_SAMPLENUM_128,
+	/** Average 256 samples */
+	ADC_ACCUMULATE_SAMPLES_256  = ADC_AVGCTRL_SAMPLENUM_256,
+	/** Average 512 samples */
+	ADC_ACCUMULATE_SAMPLES_512  = ADC_AVGCTRL_SAMPLENUM_512,
+	/** Average 1024 samples */
+	ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
+};
+
+/**
+ * \brief ADC possible dividers for the result register.
+ *
+ * Enum for the possible division factors to use when accumulating
+ * multiple samples. To keep the same resolution for the averaged
+ * result and the actual input value, the division factor must
+ * be equal to the number of samples accumulated. This setting is only
+ * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
+ */
+enum adc_divide_result {
+	/** Don't divide result register after accumulation */
+	ADC_DIVIDE_RESULT_DISABLE = 0,
+	/** Divide result register by 2 after accumulation */
+	ADC_DIVIDE_RESULT_2       = 1,
+	/** Divide result register by 4 after accumulation */
+	ADC_DIVIDE_RESULT_4       = 2,
+	/** Divide result register by 8 after accumulation */
+	ADC_DIVIDE_RESULT_8       = 3,
+	/** Divide result register by 16 after accumulation */
+	ADC_DIVIDE_RESULT_16      = 4,
+	/** Divide result register by 32 after accumulation */
+	ADC_DIVIDE_RESULT_32      = 5,
+	/** Divide result register by 64 after accumulation */
+	ADC_DIVIDE_RESULT_64      = 6,
+	/** Divide result register by 128 after accumulation */
+	ADC_DIVIDE_RESULT_128     = 7,
+};
+
+#if ADC_CALLBACK_MODE == true
+/**
+ * Enum for the possible ADC interrupt flags.
+ */
+enum adc_interrupt_flag {
+	/** ADC result ready */
+	ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
+	/** Window monitor match */
+	ADC_INTERRUPT_WINDOW       = ADC_INTFLAG_WINMON,
+	/** ADC result overwritten before read */
+	ADC_INTERRUPT_OVERRUN      = ADC_INTFLAG_OVERRUN,
+};
+#endif
+
+/**
+ * \brief ADC oversampling and decimation enum.
+ *
+ * Enum for the possible numbers of bits resolution can be increased by when
+ * using oversampling and decimation.
+ *
+ */
+enum adc_oversampling_and_decimation {
+	/** Don't use oversampling and decimation mode */
+	ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
+	/** 1-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
+	/** 2-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
+	/** 3-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
+	/** 4-bit resolution increase */
+	ADC_OVERSAMPLING_AND_DECIMATION_4BIT
+};
+
+#ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE
+/**
+ * Enum for the trigger selection in dual mode.
+ */
+enum adc_dual_mode_trigger_selection {
+	/** Start event or software trigger will start a conversion on both ADCs */
+	ADC_DUAL_MODE_BOTH         = ADC_CTRLC_DUALSEL_BOTH,
+	/** START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
+	ADC_DUAL_MODE_INTERLEAVE   = ADC_CTRLC_DUALSEL_INTERLEAVE,
+};
+#endif
+
+/**
+ * \brief Window monitor configuration structure.
+ *
+ * Window monitor configuration structure.
+ */
+struct adc_window_config {
+	/** Selected window mode */
+	enum adc_window_mode window_mode;
+	/** Lower window value */
+	int32_t window_lower_value;
+	/** Upper window value */
+	int32_t window_upper_value;
+};
+
+/**
+ * \brief ADC event enable/disable structure.
+ *
+ * Event flags for the ADC module. This is used to enable and
+ * disable events via \ref adc_enable_events() and \ref adc_disable_events().
+ */
+struct adc_events {
+	/** Enable event generation on conversion done */
+	bool generate_event_on_conversion_done;
+	/** Enable event generation on window monitor */
+	bool generate_event_on_window_monitor;
+};
+
+/**
+ * \brief Gain and offset correction configuration structure.
+ *
+ * Gain and offset correction configuration structure.
+ * Part of the \ref adc_config struct and will  be initialized by
+ * \ref adc_get_config_defaults.
+ */
+struct adc_correction_config {
+	/**
+	 * Enables correction for gain and offset based on values of gain_correction and
+	 * offset_correction if set to true
+	 */
+	bool correction_enable;
+	/**
+	 * This value defines how the ADC conversion result is compensated for gain
+	 * error before written to the result register. This is a fractional value,
+	 * 1-bit integer plus an 11-bit fraction, therefore
+	 * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
+	 * \c 0b010000000000 to \c 0b111111111111.
+	 */
+	uint16_t gain_correction;
+	/**
+	 * This value defines how the ADC conversion result is compensated for
+	 * offset error before written to the result register. This is a 12-bit
+	 * value in two's complement format.
+	 */
+	int16_t offset_correction;
+};
+
+/**
+ * \brief ADC configuration structure.
+ *
+ * Configuration structure for an ADC instance. This structure should be
+ * initialized by the \ref adc_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct adc_config {
+	/** GCLK generator used to clock the peripheral */
+	enum gclk_generator clock_source;
+	/** Voltage reference */
+	enum adc_reference reference;
+	/** Clock prescaler */
+	enum adc_clock_prescaler clock_prescaler;
+	/** Result resolution */
+	enum adc_resolution resolution;
+	/** Positive MUX input */
+	enum adc_positive_input positive_input;
+	/** Negative MUX input */
+	enum adc_negative_input negative_input;
+	/** Number of ADC samples to accumulate when using the
+	 *  \c ADC_RESOLUTION_CUSTOM mode
+	 */
+	enum adc_accumulate_samples accumulate_samples;
+	/** Division ration when using the ADC_RESOLUTION_CUSTOM mode */
+	enum adc_divide_result divide_result;
+	/** Left adjusted result */
+	bool left_adjust;
+	/** Enables differential mode if true */
+	bool differential_mode;
+	/** Enables free running mode if true */
+	bool freerunning;
+	/** ADC run in standby control */
+	bool run_in_standby;
+	/** ADC On demand control */
+	bool on_demand;
+	/**
+	 * Enables sampling period offset compensation if true
+	 */
+	bool sampling_time_compensation_enable;
+	/**
+	 * Positive input enabled mask for conversion sequence.
+	 * The sequence start from the lowest input, and go to the next enabled input
+	 * automatically when the conversion is done. If no bits are set the
+	 * sequence is disabled.
+	 */
+	uint32_t positive_input_sequence_mask_enable;
+	/**
+	 * Enables reference buffer offset compensation if true.
+	 * This will increase the accuracy of the gain stage, but decreases the input
+	 * impedance; therefore the startup time of the reference must be increased.
+	 */
+	bool reference_compensation_enable;
+	/**
+	 * This value (0-63) control the ADC sampling time in number of half ADC
+	 * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
+	 * controlling the ADC input impedance. Sampling time is set according to
+	 * the formula:
+	 * Sample time = (sample_length+1) * (ADCclk / 2).
+	 */
+	uint8_t sample_length;
+	/** Window monitor configuration structure */
+	struct adc_window_config window;
+	/** Gain and offset correction configuration structure */
+	struct adc_correction_config correction;
+	/** Event action to take on incoming event */
+	enum adc_event_action event_action;
+};
+
+/**
+ * \brief ADC software device instance structure.
+ *
+ * ADC software instance structure, used to retain software state information
+ * of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct adc_module {
+#if !defined(__DOXYGEN__)
+	/** Pointer to ADC hardware module */
+	Adc *hw;
+	/** Keep reference configuration so we know when enable is called */
+	enum adc_reference reference;
+#  if ADC_CALLBACK_MODE == true
+	/** Array to store callback functions */
+	adc_callback_t callback[ADC_CALLBACK_N];
+	/** Pointer to buffer used for ADC results */
+	volatile uint16_t *job_buffer;
+	/** Remaining number of conversions in current job */
+	volatile uint16_t remaining_conversions;
+	/** Bit mask for callbacks registered */
+	uint8_t registered_callback_mask;
+	/** Bit mask for callbacks enabled */
+	uint8_t enabled_callback_mask;
+	/** Holds the status of the ongoing or last conversion job */
+	volatile enum status_code job_status;
+	/** If software triggering is needed */
+	bool software_trigger;
+#  endif
+#endif
+};
+
+#if !defined(__DOXYGEN__)
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus. This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true if the module synchronization is ongoing
+ * \retval false if the module has completed synchronization
+ */
+static inline bool adc_is_syncing(
+	struct adc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	Adc *const adc_module = module_inst->hw;
+
+	if (adc_module->SYNCBUSY.reg) {
+		return true;
+	}
+
+	return false;
+}
+#endif
+
+/**
+ * \name  Positive Input Sequence
+ * @{
+ */
+
+/**
+ * \brief Enable positive input sequence mask for conversion.
+ *
+ * The sequence start from the lowest input, and go to the next enabled input
+ * automatically when the conversion is done. If no bits are set the
+ * sequence is disabled.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ * \param[in] eanble_seq_mask  Sequence mask
+ */
+static inline void adc_enable_positive_input_sequence(
+		struct adc_module *const module_inst,
+		uint32_t positive_input_sequence_mask_enable)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	Adc *const adc_module = module_inst->hw;
+	adc_module->SEQCTRL.reg = positive_input_sequence_mask_enable;
+}
+
+/**
+ * \brief Disable positive input in the sequence.
+ *
+ * Disable positive input in the sequence.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ */
+static inline void adc_disable_positive_input_sequence(
+		struct adc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+
+	Adc *const adc_module = module_inst->hw;
+	adc_module->SEQCTRL.reg = 0;
+}
+
+/**
+ * \brief Get ADC sequence status.
+ *
+ * Check if a sequence is done and get last conversion done in the sequence.
+ *
+ * \param[in] module_inst  Pointer to the ADC software instance struct
+ * \param[out] is_sequence_busy  Sequence busy status
+ * \param[out] sequence_state This value identifies the last conversion
+ *             done in the sequence
+ */
+static inline void adc_get_sequence_status(
+		struct adc_module *const module_inst,
+		bool  * is_sequence_busy,
+		uint8_t *sequence_state)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	uint8_t temp = false;
+	Adc *const adc_module = module_inst->hw;
+	temp = adc_module->SEQSTATUS.reg;
+	if(temp & ADC_SEQSTATUS_SEQBUSY){
+		*is_sequence_busy = true;
+	}
+	*sequence_state = temp & ADC_SEQSTATUS_SEQSTATE_Msk;
+}
+
+/** @} */
+
+#ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE
+/**
+ * \brief Set ADC master and slave mode.
+ *
+ * Enable ADC module Master-Slave Operation and select dual mode trigger.
+ *
+ * \param[in] master_inst  Pointer to the master ADC software instance struct
+ * \param[in] slave_inst   Pointer to the slave ADC software instance struct
+ * \param[in] dualsel      Dual mode trigger selection
+ *
+ */
+static inline void adc_set_master_slave_mode(
+		struct adc_module *const master_inst,
+		struct adc_module *const slave_inst,
+		enum adc_dual_mode_trigger_selection dualsel)
+{
+	/* Sanity check arguments */
+	Assert(master_inst);
+	Assert(slave_inst);
+
+	slave_inst->hw->CTRLA.reg |= ADC_CTRLA_SLAVEEN;
+	master_inst->hw->CTRLC.reg |= dualsel;
+
+};
+#endif
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_FEATURE_H_INCLUDED */
+

firmware/SendcommCmdsys/src/ASF/sam0/drivers/aes/aes.c

@@ -0,0 +1,319 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Advanced Encryption Standard driver.
+ *
+ * This file defines a useful set of functions for the AES on SAM devices.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <aes.h>
+#include <system.h>
+
+/**
+ * \brief Initializes an AES configuration structure to defaults.
+ *
+ * Initializes the specified AES configuration structure to a set of
+ * known default values.
+ *
+ * \note This function should be called to initialize <b>all</b> new instances of
+ * AES configuration structures before they are further modified by the user
+ * application.
+ *
+ *  The default configuration is as follows:
+ *  - Data encryption
+ *  - 128-bit AES key size
+ *  - 128-bit cipher feedback size
+ *  - Manual start mode
+ *  - Electronic Codebook (ECB) mode
+ *  - All countermeasures are enabled
+ *  - XRO key is disabled
+ *  - Key generation is disabled
+ *  - Last output data mode is disabled
+ *
+ *  \param[out] config Pointer to an AES configuration structure
+ */
+void aes_get_config_defaults(
+		struct aes_config *const config)
+{
+
+	/* Sanity check arguments */
+	Assert(config);
+	config->encrypt_mode = AES_ENCRYPTION;
+	config->key_size = AES_KEY_SIZE_128;
+	config->start_mode = AES_MANUAL_START;
+	config->opmode= AES_ECB_MODE;
+	config->cfb_size = AES_CFB_SIZE_128;
+	config->ctype = AES_COUNTERMEASURE_TYPE_ALL;
+	config->enable_xor_key = false;
+	config->enable_key_gen = false;
+	config->lod = false;
+}
+
+/**
+ * \brief Initialize the AES module.
+ *
+ * \param[out] module  Pointer to the software instance struct
+ * \param[in] hw Module hardware register base address pointer
+ * \param[in] config  Pointer to an AES configuration structure
+ */
+void aes_init(
+		struct aes_module *const module,
+		Aes *const hw,
+		struct aes_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(hw);
+	Assert(config);
+	Assert(module);
+
+	/* Enable clock for AES */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_AES);
+
+	/* Perform a software reset */
+	hw->CTRLA.reg = AES_CTRLA_SWRST;
+
+	/* Initialize the AES with new configurations */
+	aes_set_config(module,hw, config);
+}
+
+/**
+ * \brief Enable the AES module.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ */
+void aes_enable(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+	module->hw->CTRLA.reg |= AES_CTRLA_ENABLE;
+
+}
+
+/**
+ * \brief Disable the AES module.
+ * \param[in] module  Pointer to the software instance struct
+ */
+void aes_disable(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	/* Disbale interrupt */
+	module->hw->INTENCLR.reg = AES_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	module->hw->INTFLAG.reg = AES_INTFLAG_MASK;
+
+	module->hw->CTRLA.reg &= (~AES_CTRLA_ENABLE);
+}
+
+/**
+ * \brief Configure the AES module.
+ *
+ * \param[out] module  Pointer to the software instance struct
+ * \param[in] hw Module hardware register base address pointer
+ * \param[in] config  Pointer to an AES configuration structure
+ */
+void aes_set_config(
+		struct aes_module *const module,
+		Aes *const hw,
+		struct aes_config *const config)
+{
+	uint32_t ul_mode = 0;
+
+	/* Validate arguments. */
+	Assert(hw);
+	Assert(config);
+	Assert(module);
+
+	module->opmode = config->opmode;
+	module->hw = hw;
+	module->key_size = config->key_size;
+	module->cfb_size = config->cfb_size;
+
+	ul_mode |= (config->encrypt_mode << AES_CTRLA_CIPHER_Pos)
+			 | (config->start_mode << AES_CTRLA_STARTMODE_Pos)
+			 | (config->key_size << AES_CTRLA_KEYSIZE_Pos)
+			 | (config->opmode << AES_CTRLA_AESMODE_Pos)
+			 | (config->cfb_size << AES_CTRLA_CFBS_Pos)
+			 | (AES_CTRLA_CTYPE(config->ctype))
+			 | (config->enable_xor_key << AES_CTRLA_XORKEY_Pos)
+			 | (config->enable_key_gen << AES_CTRLA_KEYGEN_Pos)
+			 | (config->lod << AES_CTRLA_LOD_Pos);
+	if (hw->CTRLA.reg & AES_CTRLA_ENABLE) {
+		aes_disable(module);
+		hw->CTRLA.reg = ul_mode;
+		aes_enable(module);
+	} else {
+		hw->CTRLA.reg = ul_mode;
+	}
+}
+
+/**
+ * \brief Write the 128/192/256-bit cryptographic key.
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in]  key Pointer to 4/6/8 contiguous 32-bit words
+ *
+ * \note The key size depends on the current AES configuration.
+ */
+void aes_write_key(
+		struct aes_module *const module,
+		const uint32_t *key)
+{
+	uint32_t i, key_length = 0;
+
+	/* Validate arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(key);
+
+	switch (module->key_size) {
+	case AES_KEY_SIZE_128:
+		key_length = 4;
+		break;
+
+	case AES_KEY_SIZE_192:
+		key_length = 6;
+		break;
+
+	case AES_KEY_SIZE_256:
+		key_length = 8;
+		break;
+
+	default:
+		break;
+	}
+
+	for (i = 0; i < key_length; i++) {
+		module->hw->KEYWORD[i].reg = *key;
+		key++;
+	}
+}
+
+/**
+ * \brief Write the initialization vector (for the CBC, CFB, OFB, CTR, and GCM
+ * cipher modes).
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in] vector Pointer to four contiguous 32-bit words
+ */
+void aes_write_init_vector(
+		struct aes_module *const module,
+		const uint32_t *vector)
+{
+	uint32_t i;
+
+	/* Validate arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(module->opmode != AES_ECB_MODE);
+
+	for (i = 0; i < 4; i++) {
+		module->hw->INTVECTV[i].reg = *vector;
+		vector++;
+	}
+}
+
+/**
+ * \brief Write the input data (four consecutive 32-bit words).
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in] input_data_buffer Pointer to an input data buffer
+ */
+void aes_write_input_data(
+		struct aes_module *const module,
+		const uint32_t *input_data_buffer)
+{
+	uint32_t i;
+
+	/* Validate arguments. */
+	Assert(module);
+	Assert(module->hw);;
+	Assert(input_data_buffer);
+
+	module->hw->DATABUFPTR.reg = 0;
+	if (module->opmode == AES_CFB_MODE
+		&& module->cfb_size == AES_CFB_SIZE_64){
+		for (i = 0; i < 2; i++) {
+			module->hw->INDATA.reg = *input_data_buffer;
+			input_data_buffer++;
+		}
+	} else if (module->opmode == AES_CFB_MODE
+		&& (module->cfb_size == AES_CFB_SIZE_32 || module->cfb_size == AES_CFB_SIZE_16)){
+		module->hw->INDATA.reg = *input_data_buffer;
+	} else {
+		for (i = 0; i < 4; i++) {
+			module->hw->INDATA.reg = *input_data_buffer;
+			input_data_buffer++;
+		}
+	}
+}
+
+/**
+ * \brief Read the output data.
+ *
+ * \note The data buffer that holds the processed data must be large enough to hold
+ * four consecutive 32-bit words.
+ *
+ * \param[in] module  Pointer to the software instance struct
+ * \param[in] output_data_buffer Pointer to an output buffer
+ */
+void aes_read_output_data(
+		struct aes_module *const module,
+		uint32_t *output_data_buffer)
+{
+	uint32_t i;
+
+	/* Validate arguments. */
+	Assert(module);
+	Assert(module->hw);
+	Assert(output_data_buffer);
+
+	module->hw->DATABUFPTR.reg = 0;
+	if (module->opmode == AES_CFB_MODE
+		&& module->cfb_size == AES_CFB_SIZE_64){
+		for (i = 0; i < 2; i++) {
+			*output_data_buffer = module->hw->INDATA.reg;
+			output_data_buffer++;
+		}
+	} else if (module->opmode == AES_CFB_MODE
+		&& (module->cfb_size == AES_CFB_SIZE_32 || module->cfb_size == AES_CFB_SIZE_16)){
+		*output_data_buffer = module->hw->INDATA.reg;
+	} else {
+		for (i = 0; i < 4; i++) {
+			*output_data_buffer = module->hw->INDATA.reg;
+			output_data_buffer++;
+		}
+	}
+}

firmware/SendcommCmdsys/src/ASF/sam0/drivers/aes/aes.h

@@ -0,0 +1,706 @@
+/**
+ *
+ * \file
+ *
+ * \brief SAM Advanced Encryption Standard driver.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef AES_H_INCLUDED
+#define AES_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_drivers_aes_group SAM Advanced Encryption Standard (AES) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's Advanced Encryption Standard functionality. The following
+ * driver API modes are covered by this manual:
+ *
+ *  - Polled APIs
+ *  - Callback APIs
+ *
+ * The Advanced Encryption Standard module supports all five confidentiality
+ * modes of operation for symmetrical key block cipher algorithms (as specified
+ * in the NIST Special Publication 800-38A Recommendation):
+ * - Electronic Code Book (ECB)
+ * - Cipher Block Chaining (CBC)
+ * - Output Feedback (OFB)
+ * - Cipher Feedback (CFB)
+ * - Counter (CTR)
+ *
+ * The following peripheral is used by this module:
+ *  - AES (Advanced Encryption Standard)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM L21
+ *  - Atmel | SMART SAM L22
+ *  - Atmel | SMART SAM R34/R35
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_drivers_aes_prerequisites
+ *  - \ref asfdoc_sam0_drivers_aes_module_overview
+ *  - \ref asfdoc_sam0_drivers_aes_special_considerations
+ *  - \ref asfdoc_sam0_drivers_aes_extra_info
+ *  - \ref asfdoc_sam0_drivers_aes_examples
+ *  - \ref asfdoc_sam0_drivers_aes_api_overview
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_module_overview Module Overview
+ *
+ * The Advanced Encryption Standard (AES) is a specification for the encryption of
+ * electronic data established by the U.S. National Institute of Standards and
+ * Technology (NIST) in 2001. It is compliant with the American FIPS
+ * (Federal Information Processing Standard) Publication 197 specification.
+ *
+ * The AES supports all five confidentiality modes of operation for symmetrical
+ * key block cipher algorithms (as specified in the NIST Special Publication
+ * 800-38A Recommendation):
+ * - Electronic Code Book (ECB)
+ * - Cipher Block Chaining (CBC)
+ * - Output Feedback (OFB)
+ * - Cipher Feedback (CFB)
+ * - Counter (CTR)
+ *
+ * Data transfers both to and from the AES module can occur using the peripheral
+ * DMA controller channels, thus minimizing processor intervention for
+ * large data buffer transfers.
+ *
+ * As soon as the initialization vector, the input data and the key are
+ * configured, the encryption/decryption process may be started. Once the
+ * process has completed the encrypted/decrypted data can be read out via
+ * registers or through DMA channels.
+ *
+ * \subsection asfdoc_sam0_drivers_aes_module_overview_en_de Encryption and Decryption
+ * The AES is capable of using cryptographic keys of 128/192/256 bits to
+ * encrypt and decrypt data in blocks of 128 bits. In Cipher Feedback Mode (CFB),
+ * five data sizes are possible (8, 16, 32, 64, or 128 bits).
+ *
+ * The input to the encryption processes of the CBC, CFB, and OFB modes includes,
+ * in addition to the plaintext, a 128-bit data block called the Initialization
+ * Vector (IV). The Initialization Vector is used in the initial step in the
+ * encryption of a message and in the corresponding decryption of the message.
+ *
+ * There are three encryption/decryption start modes:
+ * - Manual Mode: Start encryption/decryption manually
+ * - Auto Start Mode: Once the correct number of input data registers is written,
+ * processing is automatically started, DMA operation uses this mode
+ * - Last Output Data Mode (LOD): This mode is used to generate message
+ * authentication code (MAC) on data in CCM mode of operation
+ *
+ * \subsection asfdoc_sam0_drivers_aes_module_overview_hardware_countermeasures Hardware Countermeasures
+ * The AES module features four types of hardware countermeasures that are
+ * useful for protecting data against differential power analysis attacks:
+ * - Type 1: Randomly add one cycle to data processing
+ * - Type 2: Randomly add one cycle to data processing (other version)
+ * - Type 3: Add a random number of clock cycles to data processing, subject to
+ * a maximum of 11/13/15 clock cycles for key sizes of 128/192/256 bits
+ * - Type 4: Add random spurious power consumption during data processing
+ *
+ * \subsection asfdoc_sam0_drivers_aes_module_overview_gcm Galois Counter Mode (GCM)
+ * GCM is comprised of the AES engine in CTR mode along with a universal hash
+ * function (GHASH engine) that is defined over a binary Galois field to produce
+ * a message authentication tag. The GHASH engine processes data packets after the
+ * AES operation. GCM provides assurance of the confidentiality of data through the
+ * AES Counter mode of operation for DRAFT 920 encryption. Authenticity of the
+ * confidential data is assured through the GHASH engine. Refer to the NIST Special
+ * Publication 800-38D Recommendation for more complete information.
+ *
+ * \section asfdoc_sam0_drivers_aes_special_considerations Special Considerations
+ *
+ * There are no special considerations for this module.
+ *
+ * \section asfdoc_sam0_drivers_aes_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_drivers_aes_extra. This includes:
+ *  - \ref asfdoc_sam0_drivers_aes_extra_acronyms
+ *  - \ref asfdoc_sam0_drivers_aes_extra_dependencies
+ *  - \ref asfdoc_sam0_drivers_aes_extra_errata
+ *  - \ref asfdoc_sam0_drivers_aes_extra_history
+ *
+ * \section asfdoc_sam0_drivers_aes_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_drivers_aes_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AES processing mode. */
+enum aes_encrypt_mode {
+	AES_DECRYPTION = 0,     /**< Decryption of data will be performed */
+	AES_ENCRYPTION,         /**< Encryption of data will be performed */
+};
+
+/** AES cryptographic key size. */
+enum aes_key_size {
+	AES_KEY_SIZE_128 = 0,   /**< AES key size is 128-bit */
+	AES_KEY_SIZE_192,       /**< AES key size is 192-bit */
+	AES_KEY_SIZE_256,       /**< AES key size is 256-bit */
+};
+
+/** AES start mode. */
+enum aes_start_mode {
+	AES_MANUAL_START = 0,   /**< Manual start mode */
+	AES_AUTO_START,         /**< Auto start mode */
+};
+
+/** AES operation mode. */
+enum aes_operation_mode {
+	AES_ECB_MODE = 0,       /**< Electronic Codebook (ECB) */
+	AES_CBC_MODE,           /**< Cipher Block Chaining (CBC) */
+	AES_OFB_MODE,           /**< Output Feedback (OFB) */
+	AES_CFB_MODE,           /**< Cipher Feedback (CFB) */
+	AES_CTR_MODE,           /**< Counter (CTR) */
+	AES_CCM_MODE,           /**< Counter (CCM) */
+	AES_GCM_MODE,           /**< Galois Counter Mode (GCM) */
+};
+
+/** AES Cipher FeedBack (CFB) size. */
+enum aes_cfb_size {
+	AES_CFB_SIZE_128 = 0,   /**< Cipher feedback data size is 128-bit */
+	AES_CFB_SIZE_64,        /**< Cipher feedback data size is 64-bit */
+	AES_CFB_SIZE_32,        /**< Cipher feedback data size is 32-bit */
+	AES_CFB_SIZE_16,        /**< Cipher feedback data size is 16-bit */
+	AES_CFB_SIZE_8,         /**< Cipher feedback data size is 8-bit */
+};
+
+/** AES countermeasure type */
+enum aes_countermeature_type {
+	AES_COUNTERMEASURE_TYPE_disabled = 0x0,    /**< Countermeasure type all disabled */
+	AES_COUNTERMEASURE_TYPE_1 = 0x01,          /**< Countermeasure1 enabled */
+	AES_COUNTERMEASURE_TYPE_2 = 0x02,          /**< Countermeasure2 enabled */
+	AES_COUNTERMEASURE_TYPE_3 = 0x04,          /**< Countermeasure3 enabled */
+	AES_COUNTERMEASURE_TYPE_4 = 0x08,          /**< Countermeasure4 enabled */
+	AES_COUNTERMEASURE_TYPE_ALL = 0x0F,        /**< Countermeasure type all enabled */
+};
+
+/**
+ * \name Module Status Flags
+ *
+ * AES status flags, returned by \ref aes_get_status() and cleared by
+ * \ref aes_clear_status().
+ *
+ * @{
+ */
+
+/** AES encryption complete.
+ */
+#define AES_ENCRYPTION_COMPLETE  (1UL << 0)
+
+/** AES GF multiplication complete.
+ */
+#define AES_GF_MULTI_COMPLETE    (1UL << 1)
+/** @} */
+
+
+/** AES Configuration structure. */
+struct aes_config {
+	/** AES data mode (decryption or encryption) */
+	enum aes_encrypt_mode encrypt_mode;
+	/** AES key size */
+	enum aes_key_size key_size;
+	/** Start mode */
+	enum aes_start_mode start_mode;
+	/** AES cipher operation mode*/
+	enum aes_operation_mode opmode;
+	/** Cipher feedback data size */
+	enum aes_cfb_size cfb_size;
+	/** Countermeasure type */
+	enum aes_countermeature_type ctype;
+	/** Enable XOR key */
+	bool enable_xor_key;
+	/** Enable key generation */
+	bool enable_key_gen;
+	/** Last output data mode enable/disable */
+	bool lod;
+};
+
+#if !defined(__DOXYGEN__)
+/**
+ * \brief Device structure.
+ */
+struct aes_module {
+	/** AES hardware module. */
+	Aes *hw;
+	/** AES cipher operation mode.*/
+	enum aes_operation_mode opmode;
+	/** AES key size. */
+	enum aes_key_size key_size;
+	/** Cipher feedback data size. */
+	enum aes_cfb_size cfb_size;
+};
+#endif
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+void aes_get_config_defaults(struct aes_config *const config);
+
+void aes_set_config(struct aes_module *const module,
+					Aes *const hw,
+					struct aes_config *const config);
+
+void aes_init(struct aes_module *const module,
+				Aes *const hw,
+				struct aes_config *const config);
+
+/** @} */
+
+/**
+ * \name Start, Enable, and Write
+ * @{
+ */
+
+/**
+ * \brief Start a manual encryption/decryption process.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ */
+static inline void aes_start(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->CTRLB.reg |= AES_CTRLB_START;
+}
+/**
+ * \brief Notifies the module that the next input data block
+ * is the beginning of a new message.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ *
+ */
+static inline void aes_set_new_message(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+	module->hw->CTRLB.reg |= AES_CTRLB_NEWMSG;
+}
+/**
+ * \brief Clear the indication of the beginning for a new message
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ *
+ */
+static inline void aes_clear_new_message(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+	module->hw->CTRLB.reg &= ~AES_CTRLB_NEWMSG;
+}
+
+void aes_enable(struct aes_module *const module);
+
+void aes_disable(struct aes_module *const module);
+
+void aes_write_key(struct aes_module *const module, const uint32_t *key);
+
+void aes_write_init_vector(struct aes_module *const module, const uint32_t *vector);
+
+void aes_write_input_data(struct aes_module *const module,
+		const uint32_t *p_input_data_buffer);
+
+void aes_read_output_data(struct aes_module *const module,
+		uint32_t *p_output_data_buffer);
+
+/**
+ * \brief Write AES random seed.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] seed Seed for the random number generator
+ */
+static inline void aes_write_random_seed(struct aes_module *const module,
+										uint32_t seed)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->RANDSEED.reg = seed;
+}
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+
+/**
+ * \brief Retrieves the current module status.
+ *
+ * Retrieves the status of the module, giving overall state information.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ *
+ * \retval AES_ENCRYPTION_COMPLETE   AES encryption complete
+ * \retval AES_GF_MULTI_COMPLETE   AES GF multiplication complete
+ */
+static inline uint32_t aes_get_status(struct aes_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	uint32_t int_flags = module->hw->INTFLAG.reg;
+	uint32_t status_flags = 0;
+
+	if (int_flags & AES_INTFLAG_ENCCMP) {
+		status_flags |= AES_ENCRYPTION_COMPLETE;
+	}
+
+	if (int_flags & AES_INTFLAG_GFMCMP) {
+		status_flags |= AES_GF_MULTI_COMPLETE;
+	}
+
+	return status_flags;
+}
+
+/**
+ * \brief Clears a module status flag.
+ *
+ * Clears the given status flag of the module.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] status_flags Bitmask flags to clear
+ */
+static inline void aes_clear_status(
+		struct aes_module *const module,
+		const uint32_t status_flags)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	uint32_t int_flags = 0;
+
+	if (status_flags & AES_ENCRYPTION_COMPLETE) {
+		int_flags |= AES_INTENCLR_ENCCMP;
+	}
+
+	if (status_flags & AES_GF_MULTI_COMPLETE) {
+		int_flags |= AES_INTENCLR_GFMCMP;
+	}
+
+	/* Clear interrupt flag */
+	module->hw->INTFLAG.reg = int_flags;
+}
+
+/** @} */
+
+/**
+ * \name Galois Counter Mode
+ * @{
+ */
+
+/**
+ * \brief  Get the AES GCM Hash Value.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] id Index into the GHASH array (range 0 to 3)
+ *
+ * \return The content of the GHASHRx[x = 0...3] value.
+ */
+static inline uint32_t aes_gcm_read_ghash(struct aes_module *const module, uint32_t id)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	return module->hw->GHASH[id].reg;
+}
+
+/**
+ * \brief  Set the AES GCM Hash Value.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] id Index into the GHASHx array (range 0 to 3)
+ * \param[in] ghash GCM hash value
+ */
+static inline void aes_gcm_write_ghash(struct aes_module *const module,
+									uint32_t id,uint32_t ghash)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->GHASH[id].reg = ghash;
+}
+
+
+/**
+ * \brief  Get AES GCM Hash key.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in]  id    Index into the Hash key array (range 0 to 3)
+ *
+ * \return The contents of the HASHKEYx[x = 0...3] specified.
+ */
+static inline uint32_t aes_gcm_read_hash_key(struct aes_module *const module,
+											uint32_t id)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	return module->hw->HASHKEY[id].reg;
+}
+
+/**
+ * \brief  Set the AES GCM Hash key.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] id Index into the Hash key array (range 0 to 3)
+ * \param[in] key GCM Hash key
+ */
+static inline void aes_gcm_write_hash_key(struct aes_module *const module,
+										uint32_t id, uint32_t key)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->HASHKEY[id].reg = key;
+}
+
+/**
+ * \brief  Get the AES GCM cipher length.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ *
+ * \return The contents of the HASHKEYx[x = 0...3] specified.
+ */
+static inline uint32_t aes_gcm_read_cipher_len(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	return (module->hw->CIPLEN.reg);
+}
+
+/**
+ * \brief  Set the AES GCM cipher length.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ * \param[in] len Cipher length
+ */
+static inline void aes_gcm_write_cipher_len(struct aes_module *const module,
+										uint32_t len)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->CIPLEN.reg = len;
+}
+
+/**
+ * \brief  Set GCM end of input message status.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ */
+static inline void aes_gcm_set_end_message_status(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->CTRLB.reg |= AES_CTRLB_EOM;
+}
+
+/**
+ * \brief  Clear GCM end of input message status.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ */
+static inline void aes_gcm_clear_end_message_status(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->CTRLB.reg &= ~AES_CTRLB_EOM;
+}
+
+/**
+ * \brief  Set GF multiplication of GCM mode.
+ *
+ * \param[in] module Pointer to the AES software instance struct
+ */
+static inline void aes_gcm_set_gf_multiplication(struct aes_module *const module)
+{
+	Assert(module);
+	Assert(module->hw);
+
+	module->hw->CTRLB.reg |= AES_CTRLB_GFMUL;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+ /** @} */
+
+/**
+ * \page asfdoc_sam0_drivers_aes_extra Extra Information for Advanced Encryption Standard
+ *
+ * \section asfdoc_sam0_drivers_aes_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>AAD</td>
+ *      <td>Additional Authenticated Data</td>
+ * </tr>
+ *  <tr>
+ *      <td>CBC</td>
+ *      <td>Cipher Block Chaining</td>
+ * </tr>
+ *  <tr>
+ *      <td>CFB</td>
+ *      <td>Cipher Feedback</td>
+ * </tr>
+ *  <tr>
+ *      <td>CTR</td>
+ *      <td> Counter</td>
+ * </tr>
+ *  <tr>
+ *      <td>DMA</td>
+ *      <td>Direct Memory Access</td>
+ * </tr>
+ *  <tr>
+ *      <td>DMAC</td>
+ *      <td>DMA Controller</td>
+ * </tr>
+ *  <tr>
+ *      <td>ECB</td>
+ *      <td>Electronic Codebook</td>
+ * </tr>
+ *  <tr>
+ *      <td>GCM</td>
+ *      <td>Galois Counter Mode</td>
+ * </tr>
+ *  <tr>
+ *      <td>OFB</td>
+ *      <td>Output Feedback</td>
+ * </tr>
+ *  <tr>
+ *      <td>QSG</td>
+ *      <td>Quick Start Guide</td>
+ * </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_drivers_aes_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_drivers_aes_exqsg Examples for Advanced Encryption Standard
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_drivers_aes_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_aes_basic_use_case
+ *  - \subpage asfdoc_sam0_aes_callback_use_case
+ *  - \subpage asfdoc_sam0_aes_dma_use_case
+ *
+ * \page asfdoc_sam0_drivers_aes_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *      <th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *      <td>42445B</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L22</td>
+ *	</tr>
+ *	<tr>
+ *      <td>42445A</td>
+ *		<td>06/2015</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ *
+ */
+
+ #ifdef __cplusplus
+}
+#endif
+
+#endif  /* AES_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/extint/extint.h

@@ -0,0 +1,699 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (c) 2012-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef EXTINT_H_INCLUDED
+#define EXTINT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_extint_group SAM External Interrupt (EXTINT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of external interrupts
+ * generated by the physical device pins, including edge detection.
+ * The following driver API modes are covered by this
+ * manual:
+ *
+ *  - Polled APIs
+ * \if EXTINT_CALLBACK_MODE
+ *  - Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ *  - EIC (External Interrupt Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R34/R35
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_extint_prerequisites
+ *  - \ref asfdoc_sam0_extint_module_overview
+ *  - \ref asfdoc_sam0_extint_special_considerations
+ *  - \ref asfdoc_sam0_extint_extra_info
+ *  - \ref asfdoc_sam0_extint_examples
+ *  - \ref asfdoc_sam0_extint_api_overview
+ *
+ *
+ * \section asfdoc_sam0_extint_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_extint_module_overview Module Overview
+ *
+ * The External Interrupt (EXTINT) module provides a method of asynchronously
+ * detecting rising edge, falling edge, or specific level detection on individual
+ * I/O pins of a device. This detection can then be used to trigger a software
+ * interrupt or event, or polled for later use if required. External interrupts
+ * can also optionally be used to automatically wake up the device from sleep
+ * mode, allowing the device to conserve power while still being able to react
+ * to an external stimulus in a timely manner.
+ *
+ * \subsection asfdoc_sam0_extint_logical_channels Logical Channels
+ * The External Interrupt module contains a number of logical channels, each of
+ * which is capable of being individually configured for a given pin routing,
+ * detection mode, and filtering/wake up characteristics.
+ *
+ * Each individual logical external interrupt channel may be routed to a single
+ * physical device I/O pin in order to detect a particular edge or level of the
+ * incoming signal.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_nmi_chanel NMI Channels
+ *
+ * One or more Non Maskable Interrupt (NMI) channels are provided within each
+ * physical External Interrupt Controller module, allowing a single physical pin
+ * of the device to fire a single NMI interrupt in response to a particular
+ * edge or level stimulus. An NMI cannot, as the name suggests, be disabled in
+ * firmware and will take precedence over any in-progress interrupt sources.
+ *
+ * NMIs can be used to implement critical device features such as forced
+ * software reset or other functionality where the action should be executed in
+ * preference to all other running code with a minimum amount of latency.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_filtering Input Filtering and Detection
+ *
+ * To reduce the possibility of noise or other transient signals causing
+ * unwanted device wake-ups, interrupts, and/or events via an external interrupt
+ * channel. A hardware signal filter can be enabled on individual channels. This
+ * filter provides a Majority-of-Three voter filter on the incoming signal, so
+ * that the input state is considered to be the majority vote of three
+ * subsequent samples of the pin input buffer. The possible sampled input and
+ * resulting filtered output when the filter is enabled is shown in
+ * \ref asfdoc_sam0_extint_filter_table "the table below".
+ *
+ * \anchor asfdoc_sam0_extint_filter_table
+ * <table>
+ *  <caption>Sampled Input and Resulting Filtered Output</caption>
+ *  <tr>
+ *      <th>Input Sample 1</th>
+ *      <th>Input Sample 2</th>
+ *      <th>Input Sample 3</th>
+ *      <th>Filtered Output</th>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>0</td> <td>0</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>0</td> <td>1</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>1</td> <td>0</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>0</td> <td>1</td> <td>1</td> <td>1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>0</td> <td>0</td> <td>0</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>0</td> <td>1</td> <td>1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>1</td> <td>0</td> <td>1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>1</td> <td>1</td> <td>1</td> <td>1</td>
+ *  </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_events Events and Interrupts
+ *
+ * Channel detection states may be polled inside the application for synchronous
+ * detection, or events and interrupts may be used for asynchronous behavior.
+ * Each channel can be configured to give an asynchronous hardware event (which
+ * may in turn trigger actions in other hardware modules) or an asynchronous
+ * software interrupt.
+ *
+ * \note The connection of events between modules requires the use of the
+ *       \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
+ *       to route output event of one module to the input event of another.
+ *       For more information on event routing, refer to the event driver
+ *       documentation.
+ *
+ * \subsection asfdoc_sam0_extint_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_extint_int_connections "The diagram below" shows how this
+ * module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_extint_int_connections
+ * \dot
+ * digraph overview {
+ *   node [label="Port Pad" shape=square] pad;
+ *
+ *   subgraph driver {
+ *     node [label="Peripheral MUX" shape=trapezium] pinmux;
+ *     node [label="EIC Module" shape=ellipse] eic;
+ *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ *   }
+ *
+ *   pinmux -> eic;
+ *   pad    -> pinmux;
+ *   pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ * \section asfdoc_sam0_extint_special_considerations Special Considerations
+ *
+ * Not all devices support disabling of the NMI channel(s) detection mode - see
+ * your device datasheet.
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_extint_extra. This includes:
+ *  - \ref asfdoc_sam0_extint_extra_acronyms
+ *  - \ref asfdoc_sam0_extint_extra_dependencies
+ *  - \ref asfdoc_sam0_extint_extra_errata
+ *  - \ref asfdoc_sam0_extint_extra_history
+ *
+ *
+ * \section asfdoc_sam0_extint_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_extint_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_extint_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <pinmux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief External interrupt edge detection configuration enum.
+ *
+ * Enum for the possible signal edge detection modes of the External
+ * Interrupt Controller module.
+ */
+enum extint_detect {
+	/** No edge detection. Not allowed as a NMI detection mode on some
+	 *  devices. */
+	EXTINT_DETECT_NONE    = 0,
+	/** Detect rising signal edges */
+	EXTINT_DETECT_RISING  = 1,
+	/** Detect falling signal edges */
+	EXTINT_DETECT_FALLING = 2,
+	/** Detect both signal edges */
+	EXTINT_DETECT_BOTH    = 3,
+	/** Detect high signal levels */
+	EXTINT_DETECT_HIGH    = 4,
+	/** Detect low signal levels */
+	EXTINT_DETECT_LOW     = 5,
+};
+
+/**
+ * \brief External interrupt internal pull configuration enum.
+ *
+ * Enum for the possible pin internal pull configurations.
+ *
+ * \note Disabling the internal pull resistor is not recommended if the driver
+ *       is used in interrupt (callback) mode, due the possibility of floating
+ *       inputs generating continuous interrupts.
+ */
+enum extint_pull {
+	/** Internal pull-up resistor is enabled on the pin */
+	EXTINT_PULL_UP        = SYSTEM_PINMUX_PIN_PULL_UP,
+	/** Internal pull-down resistor is enabled on the pin */
+	EXTINT_PULL_DOWN      = SYSTEM_PINMUX_PIN_PULL_DOWN,
+	/** Internal pull resistor is disconnected from the pin */
+	EXTINT_PULL_NONE      = SYSTEM_PINMUX_PIN_PULL_NONE,
+};
+
+/** The EIC is clocked by GCLK_EIC. */
+#define EXTINT_CLK_GCLK   0
+/** The EIC is clocked by CLK_ULP32K. */
+#define EXTINT_CLK_ULP32K 1
+
+/**
+ * \brief External Interrupt Controller channel configuration structure.
+ *
+ *  Configuration structure for the edge detection mode of an external
+ *  interrupt channel.
+ */
+struct extint_chan_conf {
+	/** GPIO pin the NMI should be connected to */
+	uint32_t gpio_pin;
+	/** MUX position the GPIO pin should be configured to */
+	uint32_t gpio_pin_mux;
+	/** Internal pull to enable on the input pin */
+	enum extint_pull gpio_pin_pull;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	/** Enable asynchronous edge detection. */
+	bool enable_async_edge_detection;
+#else
+	/** Wake up the device if the channel interrupt fires during sleep mode */
+	bool wake_if_sleeping;
+#endif
+	/** Filter the raw input signal to prevent noise from triggering an
+	 *  interrupt accidentally, using a three sample majority filter */
+	bool filter_input_signal;
+	/** Edge detection mode to use */
+	enum extint_detect detection_criteria;
+};
+
+/**
+ * \brief External Interrupt event enable/disable structure.
+ *
+ * Event flags for the \ref extint_enable_events() and
+ * \ref extint_disable_events().
+ */
+struct extint_events {
+	/** If \c true, an event will be generated when an external interrupt
+	 *  channel detection state changes */
+	bool generate_event_on_detect[32 * EIC_INST_NUM];
+};
+
+/**
+ * \brief External Interrupt Controller NMI configuration structure.
+ *
+ *  Configuration structure for the edge detection mode of an external
+ *  interrupt NMI channel.
+ */
+struct extint_nmi_conf {
+	/** GPIO pin the NMI should be connected to */
+	uint32_t gpio_pin;
+	/** MUX position the GPIO pin should be configured to */
+	uint32_t gpio_pin_mux;
+	/** Internal pull to enable on the input pin */
+	enum extint_pull gpio_pin_pull;
+	/** Filter the raw input signal to prevent noise from triggering an
+	 *  interrupt accidentally, using a three sample majority filter */
+	bool filter_input_signal;
+	/** Edge detection mode to use. Not all devices support all possible
+	 *  detection modes for NMIs.
+	 */
+	enum extint_detect detection_criteria;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	/** Enable asynchronous edge detection. */
+	bool enable_async_edge_detection;
+#endif
+};
+
+#if EXTINT_CALLBACK_MODE == true
+/** Type definition for an EXTINT module callback function */
+typedef void (*extint_callback_t)(void);
+
+#ifndef EIC_NUMBER_OF_INTERRUPTS
+#  define EIC_NUMBER_OF_INTERRUPTS 16
+#endif
+#endif
+
+#if !defined(__DOXYGEN__)
+/** \internal
+ *  Internal EXTINT module device instance structure definition.
+ */
+struct _extint_module
+{
+#  if EXTINT_CALLBACK_MODE == true
+	/** Asynchronous channel callback table, for user-registered handlers */
+	extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS];
+#  else
+	/** Dummy value to ensure the struct has at least one member */
+	uint8_t _dummy;
+#  endif
+};
+
+/**
+ * \brief Retrieves the base EIC module address from a given channel number.
+ *
+ * Retrieves the base address of a EIC hardware module associated with the
+ * given external interrupt channel.
+ *
+ * \param[in] channel  External interrupt channel index to convert
+ *
+ * \return Base address of the associated EIC module.
+ */
+static inline Eic * _extint_get_eic_from_channel(
+		const uint8_t channel)
+{
+	uint8_t eic_index = (channel / 32);
+
+	if (eic_index < EIC_INST_NUM) {
+		/* Array of available EICs */
+		Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+		return eics[eic_index];
+	} else {
+		Assert(false);
+		return NULL;
+	}
+}
+
+/**
+ * \brief Retrieves the base EIC module address from a given NMI channel number.
+ *
+ * Retrieves the base address of a EIC hardware module associated with the
+ * given non-maskable external interrupt channel.
+ *
+ * \param[in] nmi_channel  Non-Maskable interrupt channel index to convert
+ *
+ * \return Base address of the associated EIC module.
+ */
+static inline Eic * _extint_get_eic_from_nmi(
+		const uint8_t nmi_channel)
+{
+	uint8_t eic_index = nmi_channel;
+
+	if (eic_index < EIC_INST_NUM) {
+		/* Array of available EICs */
+		Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+		return eics[eic_index];
+	} else {
+		Assert(false);
+		return NULL;
+	}
+}
+#endif
+
+/** \name Event Management
+ * @{
+ */
+
+void extint_enable_events(
+		struct extint_events *const events);
+
+void extint_disable_events(
+		struct extint_events *const events);
+
+/** @} */
+
+/** \name Configuration and Initialization (Channel)
+ * @{
+ */
+
+void extint_chan_get_config_defaults(
+		struct extint_chan_conf *const config);
+
+void extint_chan_set_config(
+		const uint8_t channel,
+		const struct extint_chan_conf *const config);
+
+/** @} */
+
+/** \name Configuration and Initialization (NMI)
+ * @{
+ */
+
+/**
+ * \brief Initializes an External Interrupt NMI channel configuration structure to defaults.
+ *
+ * Initializes a given External Interrupt NMI channel configuration structure
+ * to a set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Input filtering disabled
+ * \li Detect falling edges of a signal
+ * \li Asynchronous edge detection is disabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void extint_nmi_get_config_defaults(
+		struct extint_nmi_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->gpio_pin            = 0;
+	config->gpio_pin_mux        = 0;
+	config->gpio_pin_pull       = EXTINT_PULL_UP;
+	config->filter_input_signal = false;
+	config->detection_criteria  = EXTINT_DETECT_FALLING;
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	 config->enable_async_edge_detection = false;
+#endif
+
+}
+
+enum status_code extint_nmi_set_config(
+		const uint8_t nmi_channel,
+		const struct extint_nmi_conf *const config);
+
+/** @} */
+
+/** \name Detection testing and clearing (channel)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the edge detection state of a configured channel.
+ *
+ *  Reads the current state of a configured channel, and determines
+ *  if the detection criteria of the channel has been met.
+ *
+ *  \param[in] channel  External Interrupt channel index to check
+ *
+ *  \return Status of the requested channel's edge detection state.
+ *  \retval true   If the channel's edge/level detection criteria was met
+ *  \retval false  If the channel has not detected its configured criteria
+ */
+static inline bool extint_chan_is_detected(
+		const uint8_t channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_channel(channel);
+	uint32_t eic_mask   = (1UL << (channel % 32));
+
+	return (eic_module->INTFLAG.reg & eic_mask);
+}
+
+/**
+ * \brief Clears the edge detection state of a configured channel.
+ *
+ *  Clears the current state of a configured channel, readying it for
+ *  the next level or edge detection.
+ *
+ *  \param[in] channel  External Interrupt channel index to check
+ */
+static inline void extint_chan_clear_detected(
+		const uint8_t channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_channel(channel);
+	uint32_t eic_mask   = (1UL << (channel % 32));
+
+	eic_module->INTFLAG.reg = eic_mask;
+}
+
+/** @} */
+
+/** \name Detection Testing and Clearing (NMI)
+ * @{
+ */
+
+/**
+ * \brief Retrieves the edge detection state of a configured NMI channel.
+ *
+ *  Reads the current state of a configured NMI channel, and determines
+ *  if the detection criteria of the NMI channel has been met.
+ *
+ *  \param[in] nmi_channel  External Interrupt NMI channel index to check
+ *
+ *  \return Status of the requested NMI channel's edge detection state.
+ *  \retval true   If the NMI channel's edge/level detection criteria was met
+ *  \retval false  If the NMI channel has not detected its configured criteria
+ */
+static inline bool extint_nmi_is_detected(
+		const uint8_t nmi_channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
+
+	return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI);
+}
+
+/**
+ * \brief Clears the edge detection state of a configured NMI channel.
+ *
+ *  Clears the current state of a configured NMI channel, readying it for
+ *  the next level or edge detection.
+ *
+ *  \param[in] nmi_channel  External Interrupt NMI channel index to check
+ */
+static inline void extint_nmi_clear_detected(
+		const uint8_t nmi_channel)
+{
+	Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
+
+	eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#if EXTINT_CALLBACK_MODE == true
+#  include "extint_callback.h"
+#endif
+
+/**
+ * \page asfdoc_sam0_extint_extra Extra Information for EXTINT Driver
+ *
+ * \section asfdoc_sam0_extint_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>EIC</td>
+ *      <td>External Interrupt Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MUX</td>
+ *      <td>Multiplexer</td>
+ *  </tr>
+ *  <tr>
+ *      <td>NMI</td>
+ *      <td>Non-Maskable Interrupt</td>
+ *  </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_extint_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>
+ *      \li Driver updated to follow driver type convention
+ *      \li Removed \c %extint_reset(), \c %extint_disable() and
+ *          \c extint_enable() functions. Added internal function
+ *          \c %_system_extint_init().
+ *      \li Added configuration EXTINT_CLOCK_SOURCE in conf_extint.h
+ *      \li Removed configuration EXTINT_CALLBACKS_MAX in conf_extint.h, and
+ *          added channel parameter in the register functions
+ *         \c %extint_register_callback() and \c %extint_unregister_callback()
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>Updated interrupt handler to clear interrupt flag before calling
+ *          callback function</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Updated initialization function to also enable the digital interface
+ *          clock to the module if it is disabled</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_extint_exqsg Examples for EXTINT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_extint_group.
+ * QSGs are simple examples with step-by-step instructions to configure and
+ * use this driver in a selection of use cases. Note that a QSG can be compiled
+ * as a standalone application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_extint_basic_use_case
+ * \if EXTINT_CALLBACK_MODE
+ *  - \subpage asfdoc_sam0_extint_callback_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_extint_document_revision_history Document Revision History
+ *
+ * <table>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42112E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM C21, SAM D09, and SAM DA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112B</td>
+ *      <td>06/2013</td>
+ *      <td>Added additional documentation on the event system. Corrected
+ *          documentation typos.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42112A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
+ * </table>
+ */
+
+#endif

firmware/SendcommCmdsys/src/ASF/sam0/drivers/extint/extint_callback.c

@@ -0,0 +1,222 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "extint.h"
+#include "extint_callback.h"
+
+/**
+ * \internal
+ * Internal driver device instance struct, declared in the main module driver.
+ */
+extern struct _extint_module _extint_dev;
+
+/**
+ * \internal
+ * This is the number of the channel whose callback is currently running.
+ */
+uint8_t _current_channel;
+
+/**
+ * \brief Registers an asynchronous callback function with the driver.
+ *
+ * Registers an asynchronous callback with the EXTINT driver, fired when a
+ * channel detects the configured channel detection criteria
+ * (e.g. edge or level). Callbacks are fired once for each detected channel.
+ *
+ * \note NMI channel callbacks cannot be registered via this function; the
+ *       device's NMI interrupt should be hooked directly in the user
+ *       application and the NMI flags manually cleared via
+ *       \ref extint_nmi_clear_detected().
+ *
+ * \param[in] callback  Pointer to the callback function to register
+ * \param[in] channel   Logical channel to register callback for
+ * \param[in] type      Type of callback function to register
+ *
+ * \return Status of the registration operation.
+ * \retval STATUS_OK               The callback was registered successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ * \retval STATUS_ERR_ALREADY_INITIALIZED    Callback function has been
+ *                                  registered, need unregister first
+ */
+enum status_code extint_register_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	/* Sanity check arguments */
+	Assert(callback);
+
+	if (type != EXTINT_CALLBACK_TYPE_DETECT) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (_extint_dev.callbacks[channel] == NULL) {
+		_extint_dev.callbacks[channel] = callback;
+		return STATUS_OK;
+	} else if (_extint_dev.callbacks[channel] == callback) {
+		return STATUS_OK;
+	}
+
+	return STATUS_ERR_ALREADY_INITIALIZED;
+}
+
+/**
+ * \brief Unregisters an asynchronous callback function with the driver.
+ *
+ * Unregisters an asynchronous callback with the EXTINT driver, removing it
+ * from the internal callback registration table.
+ *
+ * \param[in] callback  Pointer to the callback function to unregister
+ * \param[in] channel   Logical channel to unregister callback for
+ * \param[in] type      Type of callback function to unregister
+ *
+ * \return Status of the de-registration operation.
+ * \retval STATUS_OK               The callback was unregistered successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ * \retval STATUS_ERR_BAD_ADDRESS  No matching entry was found in the
+ *                                 registration table
+ */
+enum status_code extint_unregister_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	/* Sanity check arguments */
+	Assert(callback);
+
+	if (type != EXTINT_CALLBACK_TYPE_DETECT) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	if (_extint_dev.callbacks[channel] == callback) {
+		_extint_dev.callbacks[channel] = NULL;
+		return STATUS_OK;
+	}
+
+	return STATUS_ERR_BAD_ADDRESS;
+}
+
+/**
+ * \brief Enables asynchronous callback generation for a given channel and type.
+ *
+ * Enables asynchronous callbacks for a given logical external interrupt channel
+ * and type. This must be called before an external interrupt channel will
+ * generate callback events.
+ *
+ * \param[in] channel  Logical channel to enable callback generation for
+ * \param[in] type     Type of callback function callbacks to enable
+ *
+ * \return Status of the callback enable operation.
+ * \retval STATUS_OK               The callback was enabled successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+enum status_code extint_chan_enable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	if (type == EXTINT_CALLBACK_TYPE_DETECT) {
+		Eic *const eic = _extint_get_eic_from_channel(channel);
+
+		eic->INTENSET.reg = (1UL << channel);
+	}
+	else {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Disables asynchronous callback generation for a given channel and type.
+ *
+ * Disables asynchronous callbacks for a given logical external interrupt
+ * channel and type.
+ *
+ * \param[in] channel  Logical channel to disable callback generation for
+ * \param[in] type     Type of callback function callbacks to disable
+ *
+ * \return Status of the callback disable operation.
+ * \retval STATUS_OK               The callback was disabled successfully
+ * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
+ */
+enum status_code extint_chan_disable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type)
+{
+	if (type == EXTINT_CALLBACK_TYPE_DETECT) {
+		Eic *const eic = _extint_get_eic_from_channel(channel);
+
+		eic->INTENCLR.reg = (1UL << channel);
+	}
+	else {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Find what channel caused the callback.
+ *
+ * Can be used in an EXTINT callback function to find what channel caused
+ * the callback in case the same callback is used by multiple channels.
+ *
+ * \return Channel number.
+ */
+uint8_t extint_get_current_channel(void)
+{
+	return _current_channel;
+}
+
+/** Handler for the EXTINT hardware module interrupt. */
+void EIC_Handler(void)
+{
+	/* Find any triggered channels, run associated callback handlers */
+	for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) {
+		if (extint_chan_is_detected(_current_channel)) {
+			/* Clear flag */
+			extint_chan_clear_detected(_current_channel);
+			/* Find any associated callback entries in the callback table */
+			if (_extint_dev.callbacks[_current_channel] != NULL) {
+				/* Run the registered callback */
+				_extint_dev.callbacks[_current_channel]();
+			}
+		}
+	}
+}

firmware/SendcommCmdsys/src/ASF/sam0/drivers/extint/extint_callback.h

@@ -0,0 +1,98 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef EXTINT_CALLBACK_H_INCLUDED
+#define EXTINT_CALLBACK_H_INCLUDED
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_extint_group
+ *
+ * @{
+ */
+
+/** \name Callback Configuration and Initialization
+ * @{
+ */
+
+/** Enum for the possible callback types for the EXTINT module. */
+enum extint_callback_type
+{
+	/** Callback type for when an external interrupt detects the configured
+	 *  channel criteria (i.e. edge or level detection)
+	 */
+	EXTINT_CALLBACK_TYPE_DETECT,
+};
+
+enum status_code extint_register_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+enum status_code extint_unregister_callback(
+	const extint_callback_t callback,
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+uint8_t extint_get_current_channel(void);
+
+/** @} */
+
+/** \name Callback Enabling and Disabling (Channel)
+ * @{
+ */
+
+enum status_code extint_chan_enable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+enum status_code extint_chan_disable_callback(
+	const uint8_t channel,
+	const enum extint_callback_type type);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

firmware/SendcommCmdsys/src/ASF/sam0/drivers/extint/extint_sam_l_c/extint.c

@@ -0,0 +1,481 @@
+/**
+ * \file
+ *
+ * \brief SAM External Interrupt Driver
+ *
+ * Copyright (c) 2014-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include <system.h>
+#include <system_interrupt.h>
+#include <extint.h>
+#include <conf_extint.h>
+
+#if !defined(EXTINT_CLOCK_SELECTION) || defined(__DOXYGEN__)
+#  warning  EXTINT_CLOCK_SELECTION is not defined, assuming EXTINT_CLK_GCLK.
+
+/** Configuration option, setting the EIC clock source which can be used for
+ *  EIC edge detection or filtering. This option may be overridden in the module
+ *  configuration header file \c conf_extint.h.
+ */
+#  define EXTINT_CLOCK_SELECTION EXTINT_CLK_GCLK
+#endif
+
+#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__)
+#  warning  EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0.
+
+/** Configuration option, setting the EIC clock source which can be used for
+ *  EIC edge detection or filtering. This option may be overridden in the module
+ *  configuration header file \c conf_extint.h.
+ */
+#  define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
+#endif
+#endif
+
+/**
+ * \internal
+ * Internal driver device instance struct.
+ */
+struct _extint_module _extint_dev;
+
+/**
+ * \brief Determin if the general clock is required.
+ *
+ * \param[in] filter_input_signal Filter the raw input signal to prevent noise
+ * \param[in] detection_criteria  Edge detection mode to use (\ref extint_detect)
+ */
+#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \
+		((filter_input_signal) ? true : (\
+			(EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\
+			(EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\
+			(EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false))))
+
+static void _extint_enable(void);
+static void _extint_disable(void);
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true  If the module synchronization is ongoing
+ * \retval false If the module has completed synchronization
+ */
+static inline bool extint_is_syncing(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		if((eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE)
+		 || (eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST)){
+			return true;
+		}
+	}
+	return false;
+}
+
+/**
+ * \internal
+ * \brief Initializes and enables the External Interrupt driver.
+ *
+ * Enable the clocks used by External Interrupt driver.
+ *
+ * Resets the External Interrupt driver, resetting all hardware
+ * module registers to their power-on defaults, then enable it for further use.
+ *
+ * Reset the callback list if callback mode is used.
+ *
+ * This function must be called before attempting to use any NMI or standard
+ * external interrupt channel functions.
+ *
+ * \note When SYSTEM module is used, this function will be invoked by
+ * \ref system_init() automatically if the module is included.
+ */
+void _system_extint_init(void);
+void _system_extint_init(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_EIC);
+
+#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+	/* Configure the generic clock for the module and enable it */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE;
+	system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf);
+
+	/* Enable the clock anyway, since when needed it will be requested
+	 * by External Interrupt driver */
+	system_gclk_chan_enable(EIC_GCLK_ID);
+#endif
+
+	/* Reset all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRLA.reg |= EIC_CTRLA_SWRST;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+
+#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK;
+	}
+#else
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K;
+	}
+#endif
+
+	/* Reset the software module */
+#if EXTINT_CALLBACK_MODE == true
+	/* Clear callback registration table */
+	for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) {
+		_extint_dev.callbacks[j] = NULL;
+	}
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC);
+#endif
+
+	/* Enables the driver for further use */
+	_extint_enable();
+}
+
+/**
+ * \internal
+ * \brief Enables the External Interrupt driver.
+ *
+ * Enables EIC modules.
+ * Registered callback list will not be affected if callback mode is used.
+ */
+void _extint_enable(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Enable all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRLA.reg |= EIC_CTRLA_ENABLE;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+}
+
+/**
+ * \internal
+ * \brief Disables the External Interrupt driver.
+ *
+ * Disables EIC modules that were previously started via a call to
+ * \ref _extint_enable().
+ * Registered callback list will not be affected if callback mode is used.
+ */
+void _extint_disable(void)
+{
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	/* Disable all EIC hardware modules. */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		eics[i]->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
+	}
+
+	while (extint_is_syncing()) {
+		/* Wait for all hardware modules to complete synchronization */
+	}
+}
+
+/**
+ * \brief Initializes an External Interrupt channel configuration structure to defaults.
+ *
+ * Initializes a given External Interrupt channel configuration structure to a
+ * set of known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ * \li Input filtering disabled
+ * \li Internal pull-up enabled
+ * \li Detect falling edges of a signal
+ * \li Asynchronous edge detection is disabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+void extint_chan_get_config_defaults(
+		struct extint_chan_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->gpio_pin            = 0;
+	config->gpio_pin_mux        = 0;
+	config->gpio_pin_pull       = EXTINT_PULL_UP;
+	config->filter_input_signal = false;
+	config->detection_criteria  = EXTINT_DETECT_FALLING;
+	config->enable_async_edge_detection = false;
+}
+
+/**
+ * \brief Writes an External Interrupt channel configuration to the hardware module.
+ *
+ * Writes out a given configuration of an External Interrupt channel
+ * configuration to the hardware module. If the channel is already configured,
+ * the new configuration will replace the existing one.
+ *
+ * \param[in] channel   External Interrupt channel to configure
+ * \param[in] config    Configuration settings for the channel
+
+ */
+void extint_chan_set_config(
+		const uint8_t channel,
+		const struct extint_chan_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+	_extint_disable();
+#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+	/* Sanity check clock requirements */
+	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+		_extint_is_gclk_required(config->filter_input_signal,
+			config->detection_criteria)));
+#endif
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = config->gpio_pin_mux;
+	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+	/* Get a pointer to the module hardware instance */
+	Eic *const EIC_module = _extint_get_eic_from_channel(channel);
+
+	uint32_t config_pos = (4 * (channel % 8));
+	uint32_t new_config;
+
+	/* Determine the channel's new edge detection configuration */
+	new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos);
+
+	/* Enable the hardware signal filter if requested in the config */
+	if (config->filter_input_signal) {
+		new_config |= EIC_CONFIG_FILTEN0;
+	}
+
+	/* Clear the existing and set the new channel configuration */
+	EIC_module->CONFIG[channel / 8].reg
+		= (EIC_module->CONFIG[channel / 8].reg &
+			~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) |
+			(new_config << config_pos);
+#if (SAML22) || (SAML21XXXB) || (SAMC20) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	/* Config asynchronous edge detection */
+	if (config->enable_async_edge_detection) {
+		EIC_module->ASYNCH.reg |= (1UL << channel);
+	} else {
+		EIC_module->ASYNCH.reg &= (EIC_ASYNCH_MASK & (~(1UL << channel)));
+	}
+#endif
+#if (SAMC21)
+	/* Config asynchronous edge detection */
+	if (config->enable_async_edge_detection) {
+		EIC_module->EIC_ASYNCH.reg |= (1UL << channel);
+	} else {
+		EIC_module->EIC_ASYNCH.reg &= (EIC_EIC_ASYNCH_MASK & (~(1UL << channel)));
+	}
+#endif
+	_extint_enable();
+}
+
+/**
+ * \brief Writes an External Interrupt NMI channel configuration to the hardware module.
+ *
+ *  Writes out a given configuration of an External Interrupt NMI channel
+ *  configuration to the hardware module. If the channel is already configured,
+ *  the new configuration will replace the existing one.
+ *
+ *  \param[in] nmi_channel   External Interrupt NMI channel to configure
+ *  \param[in] config        Configuration settings for the channel
+ *
+ * \returns Status code indicating the success or failure of the request.
+ * \retval  STATUS_OK                   Configuration succeeded
+ * \retval  STATUS_ERR_PIN_MUX_INVALID  An invalid pin mux value was supplied
+ * \retval  STATUS_ERR_BAD_FORMAT       An invalid detection mode was requested
+ */
+enum status_code extint_nmi_set_config(
+		const uint8_t nmi_channel,
+		const struct extint_nmi_conf *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Sanity check clock requirements */
+	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+		_extint_is_gclk_required(config->filter_input_signal,
+			config->detection_criteria)));
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = config->gpio_pin_mux;
+	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pinmux_config.input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+	/* Get a pointer to the module hardware instance */
+	Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel);
+
+	uint32_t new_config;
+
+	/* Determine the NMI's new edge detection configuration */
+	new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos);
+
+	/* Enable the hardware signal filter if requested in the config */
+	if (config->filter_input_signal) {
+		new_config |= EIC_NMICTRL_NMIFILTEN;
+	}
+
+#if (SAML21XXXB) || (SAML22) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	/* Enable asynchronous edge detection if requested in the config */
+	if (config->enable_async_edge_detection) {
+		new_config |= EIC_NMICTRL_NMIASYNCH;
+	}
+#endif
+	
+	/* Disable EIC and general clock to configure NMI */
+	_extint_disable();
+#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+	system_gclk_chan_disable(EIC_GCLK_ID);
+#else
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++){
+		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK;
+		system_gclk_chan_disable(EIC_GCLK_ID);
+	}
+#endif
+
+	EIC_module->NMICTRL.reg = new_config;
+
+	/* Enable the EIC clock and EIC after configure NMI */
+#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
+	system_gclk_chan_enable(EIC_GCLK_ID);
+#else
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++){
+		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K;
+	}
+#endif
+	_extint_enable();
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Enables an External Interrupt event output.
+ *
+ *  Enables one or more output events from the External Interrupt module. See
+ *  \ref extint_events "here" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] events    Struct containing flags of events to enable
+ */
+void extint_enable_events(
+		struct extint_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(events);
+
+	/* Array of available EICs. */
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	_extint_disable();
+
+	/* Update the event control register for each physical EIC instance */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		uint32_t event_mask = 0;
+
+		/* Create an enable mask for the current EIC module */
+		for (uint32_t j = 0; j < 32; j++) {
+			if (events->generate_event_on_detect[(32 * i) + j]) {
+				event_mask |= (1UL << j);
+			}
+		}
+
+		/* Enable the masked events */
+		eics[i]->EVCTRL.reg |= event_mask;
+	}
+	_extint_enable();
+}
+
+/**
+ * \brief Disables an External Interrupt event output.
+ *
+ *  Disables one or more output events from the External Interrupt module. See
+ *  \ref extint_events "here" for a list of events this module supports.
+ *
+ *  \note Events cannot be altered while the module is enabled.
+ *
+ *  \param[in] events    Struct containing flags of events to disable
+ */
+void extint_disable_events(
+		struct extint_events *const events)
+{
+	/* Sanity check arguments */
+	Assert(events);
+
+	/* Array of available EICs. */
+	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+	_extint_disable();
+
+	/* Update the event control register for each physical EIC instance */
+	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
+		uint32_t event_mask = 0;
+
+		/* Create a disable mask for the current EIC module */
+		for (uint32_t j = 0; j < 32; j++) {
+			if (events->generate_event_on_detect[(32 * i) + j]) {
+				event_mask |= (1UL << j);
+			}
+		}
+
+		/* Disable the masked events */
+		eics[i]->EVCTRL.reg &= ~event_mask;
+	}
+	_extint_enable();
+}

firmware/SendcommCmdsys/src/ASF/sam0/drivers/nvm/nvm.h

@@ -0,0 +1,937 @@
+/**
+ * \file
+ *
+ * \brief SAM Non-Volatile Memory driver
+ *
+ * Copyright (c) 2012-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef NVM_H_INCLUDED
+#define NVM_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_nvm_group SAM Non-Volatile Memory (NVM) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of non-volatile memories
+ * within the device, for partitioning, erasing, reading, and writing of data.
+ *
+ * The following peripheral is used by this module:
+ *  - NVM (Non-Volatile Memory)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34/R35
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_nvm_prerequisites
+ *  - \ref asfdoc_sam0_nvm_module_overview
+ *  - \ref asfdoc_sam0_nvm_special_considerations
+ *  - \ref asfdoc_sam0_nvm_extra_info
+ *  - \ref asfdoc_sam0_nvm_examples
+ *  - \ref asfdoc_sam0_nvm_api_overview
+ *
+ *
+ * \section asfdoc_sam0_nvm_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_nvm_module_overview Module Overview
+ *
+ * The Non-Volatile Memory (NVM) module provides an interface to the device's
+ * Non-Volatile Memory controller, so that memory pages can be written, read,
+ * erased, and reconfigured in a standardized manner.
+ *
+ * \subsection asfdoc_sam0_nvm_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver feature macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_NVM_RWWEE</td>
+ *    <td>SAM L21/L22, SAM D21-64K, SAM DA1, SAM C20/C21, SAM R30 , SAM R34/R35</td>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_BOD12</td>
+ *    <td>SAM L21, SAMR30/R34</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_nvm_module_overview_regions Memory Regions
+ * The NVM memory space of the SAM devices is divided into two sections:
+ * a Main Array section, and an Auxiliary space section. The Main Array space
+ * can be configured to have an (emulated) EEPROM and/or boot loader section.
+ * The memory layout with the EEPROM and bootloader partitions is shown in
+ * \ref asfdoc_sam0_nvm_module_mem_layout "the figure below".
+ *
+ * \anchor asfdoc_sam0_nvm_module_mem_layout
+ * \dot
+ * digraph memory_layout {
+ *  size="5,5"
+ *  node [shape=plaintext, fontname=arial]
+ *  memory [label=<
+ *   <table border="0" cellborder="1" cellspacing="0" >
+ *    <tr>
+ *     <td align="right" border="0"> End of NVM Memory </td>
+ *     <td rowspan="3" align="center"> Reserved EEPROM Section </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> Start of EEPROM Memory </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> End of Application Memory </td>
+ *     <td rowspan="3" align="center"> Application Section </td>
+ *    </tr>
+ *    <tr>
+ *     <td height="300" align="right" border="0"> </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> Start of Application Memory </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> End of Bootloader Memory </td>
+ *     <td rowspan="3" align="center"> BOOT Section </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border="0"> Start of NVM Memory</td>
+ *    </tr>
+ *   </table>
+ *  >]
+ * }
+ * \enddot
+ *
+ * The Main Array is divided into rows and pages, where each row contains four
+ * pages. The size of each page may vary from 8-1024 bytes dependent of the
+ * device. Device specific parameters such as the page size and total number of
+ * pages in the NVM memory space are available via the \ref nvm_get_parameters()
+ * function.
+ *
+ * An NVM page number and address can be computed via the following equations:
+ *
+ * \f[ PageNum = (RowNum \times 4) + PagePosInRow \f]
+ * \f[ PageAddr = PageNum \times PageSize \f]
+ *
+ * \ref asfdoc_sam0_nvm_module_row_layout "The figure below" shows an example
+ * of the memory page and address values associated with logical row 7 of the
+ * NVM memory space.
+ *
+ * \anchor asfdoc_sam0_nvm_module_row_layout
+ * \dot
+ * digraph row_layout {
+ *  size="4,4"
+ *  node [shape=plaintext, fontname=arial]
+ *  row [label=<
+ *   <table border="0" cellborder="1" cellspacing="0">
+ *    <tr>
+ *     <td align="right" border ="0"> Row 0x07 </td>
+ *     <td > Page 0x1F </td>
+ *     <td > Page 0x1E </td>
+ *     <td > Page 0x1D </td>
+ *     <td > Page 0x1C </td>
+ *    </tr>
+ *    <tr>
+ *     <td align="right" border ="0"> Address </td>
+ *     <td border="0"> 0x7C0 </td>
+ *     <td border="0"> 0x780 </td>
+ *     <td border="0"> 0x740 </td>
+ *     <td border="0"> 0x700 </td>
+ *    </tr>
+ *   </table>
+ *  >]
+ * }
+ * \enddot
+ *
+ * \subsection asfdoc_sam0_nvm_module_overview_locking_regions Region Lock Bits
+ * As mentioned in \ref asfdoc_sam0_nvm_module_overview_regions, the main
+ * block of the NVM memory is divided into a number of individually addressable
+ * pages. These pages are grouped into 16 equal sized regions, where each region
+ * can be locked separately issuing an \ref NVM_COMMAND_LOCK_REGION command or
+ * by writing the LOCK bits in the User Row. Rows reserved for the EEPROM
+ * section are not affected by the lock bits or commands.
+ *
+ * \note By using the \ref NVM_COMMAND_LOCK_REGION or
+ *       \ref NVM_COMMAND_UNLOCK_REGION commands the settings will remain in
+ *       effect until the next device reset. By changing the default lock
+ *       setting for the regions, the auxiliary space must to be written,
+ *       however the adjusted configuration will not take effect until the next
+ *       device reset.
+ *
+ * \note If the \ref asfdoc_sam0_nvm_special_consideration_security_bit is
+ *       set, the auxiliary space cannot be written to. Clearing of the security
+ *       bit can only be performed by a full chip erase.
+ *
+ * \subsection asfdoc_sam0_nvm_module_overview_sub_rw Read/Write
+ * Reading from the NVM memory can be performed using direct addressing into the
+ * NVM memory space, or by calling the \ref nvm_read_buffer() function.
+ *
+ * Writing to the NVM memory must be performed by the \ref nvm_write_buffer()
+ * function - additionally, a manual page program command must be issued if
+ * the NVM controller is configured in manual page writing mode.
+ *
+ * Before a page can be updated, the associated NVM memory row must be erased
+ * first via the \ref nvm_erase_row() function. Writing to a non-erased page
+ * will result in corrupt data being stored in the NVM memory space.
+ *
+ * \section asfdoc_sam0_nvm_special_considerations Special Considerations
+ *
+ * \subsection asfdoc_sam0_nvm_special_consideration_pageerase Page Erasure
+ * The granularity of an erase is per row, while the granularity of a write is
+ * per page. Thus, if the user application is modifying only one page of a row,
+ * the remaining pages in the row must be buffered and the row erased, as an
+ * erase is mandatory before writing to a page.
+ *
+ * \subsection asfdoc_sam0_nvm_special_consideration_clocks Clocks
+ * The user must ensure that the driver is configured with a proper number of
+ * wait states when the CPU is running at high frequencies.
+ *
+ * \subsection asfdoc_sam0_nvm_special_consideration_security_bit Security Bit
+ * The User Row in the Auxiliary Space cannot be read or written when
+ * the Security Bit is set. The Security Bit can be set by using passing
+ * \ref NVM_COMMAND_SET_SECURITY_BIT to the \ref nvm_execute_command() function,
+ * or it will be set if one tries to access a locked region. See
+ * \ref asfdoc_sam0_nvm_module_overview_locking_regions.
+ *
+ * The Security Bit can only be cleared by performing a chip erase.
+ *
+ *
+ * \section asfdoc_sam0_nvm_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_nvm_extra. This includes:
+ *  - \ref asfdoc_sam0_nvm_extra_acronyms
+ *  - \ref asfdoc_sam0_nvm_extra_dependencies
+ *  - \ref asfdoc_sam0_nvm_extra_errata
+ *  - \ref asfdoc_sam0_nvm_extra_history
+ *
+ *
+ * \section asfdoc_sam0_nvm_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_nvm_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_nvm_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <status_codes.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define SAMD21-64K devices */
+#if defined(SAMD21E15L) || defined(SAMD21E16L) || defined(__SAMD21E15L__) || defined(__SAMD21E16L__) \
+	|| defined(SAMD21E15B) || defined(SAMD21E16B) || defined(__SAMD21E15B__) || defined(__SAMD21E16B__) \
+	|| defined(SAMD21E15BU) || defined(SAMD21E16BU) || defined(__SAMD21E15BU__) || defined(__SAMD21E16BU__) \
+	|| defined(SAMD21G15L) || defined(SAMD21G16L) || defined(__SAMD21G15L__) || defined(__SAMD21G16L__) \
+	|| defined(SAMD21G15B) || defined(SAMD21G16B) || defined(__SAMD21G15B__) || defined(__SAMD21G16B__) \
+	|| defined(SAMD21J15B) || defined(SAMD21J16B) || defined(__SAMD21J15B__) || defined(__SAMD21J16B__)
+
+#  define SAMD21_64K
+
+#endif
+
+/**
+ * \name Driver Feature Definition
+ *
+ * Define NVM features set according to the different device families.
+ * @{
+*/
+#if (SAML21) || (SAML22) || (SAMDA1) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || defined(SAMD21_64K) || (SAMHA1) || (WLR089) || (SAMR34) \
+	|| defined(__DOXYGEN__)
+/** Read while write EEPROM emulation feature. */
+#  define FEATURE_NVM_RWWEE
+#endif
+#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089) || defined(__DOXYGEN__)
+/** Brown-out detector internal to the voltage regulator for VDDCORE. */
+#define FEATURE_BOD12
+#endif
+/*@}*/
+
+#if !defined(__DOXYGEN__)
+/**
+ * \brief Mask for the error flags in the status register.
+ */
+#  define NVM_ERRORS_MASK (NVMCTRL_STATUS_PROGE | \
+                           NVMCTRL_STATUS_LOCKE | \
+                           NVMCTRL_STATUS_NVME)
+#endif
+
+/**
+ * \brief NVM error flags.
+ *
+ * Possible NVM controller error codes, which can be returned by the NVM
+ * controller after a command is issued.
+ */
+enum nvm_error {
+	/** No errors */
+	NVM_ERROR_NONE = 0,
+	/** Lock error, a locked region was attempted accessed */
+	NVM_ERROR_LOCK = NVMCTRL_STATUS_NVME | NVMCTRL_STATUS_LOCKE,
+	/** Program error, invalid command was executed */
+	NVM_ERROR_PROG = NVMCTRL_STATUS_NVME | NVMCTRL_STATUS_PROGE,
+};
+
+/**
+ * \brief NVM controller commands.
+ */
+enum nvm_command {
+	/** Erases the addressed memory row */
+	NVM_COMMAND_ERASE_ROW                  = NVMCTRL_CTRLA_CMD_ER,
+
+	/** Write the contents of the page buffer to the addressed memory page */
+	NVM_COMMAND_WRITE_PAGE                 = NVMCTRL_CTRLA_CMD_WP,
+
+	/** Erases the addressed auxiliary memory row.
+	 *
+	 *  \note This command can only be given when the security bit is not set.
+	 */
+	NVM_COMMAND_ERASE_AUX_ROW              = NVMCTRL_CTRLA_CMD_EAR,
+
+	/** Write the contents of the page buffer to the addressed auxiliary memory
+	 *  row.
+	 *
+	 *  \note This command can only be given when the security bit is not set.
+	 */
+	NVM_COMMAND_WRITE_AUX_ROW              = NVMCTRL_CTRLA_CMD_WAP,
+
+	/** Locks the addressed memory region, preventing further modifications
+	 *  until the region is unlocked or the device is erased
+	 */
+	NVM_COMMAND_LOCK_REGION                = NVMCTRL_CTRLA_CMD_LR,
+
+	/** Unlocks the addressed memory region, allowing the region contents to be
+	 *  modified
+	 */
+	NVM_COMMAND_UNLOCK_REGION              = NVMCTRL_CTRLA_CMD_UR,
+
+	/** Clears the page buffer of the NVM controller, resetting the contents to
+	 *  all zero values
+	 */
+	NVM_COMMAND_PAGE_BUFFER_CLEAR          = NVMCTRL_CTRLA_CMD_PBC,
+
+	/** Sets the device security bit, disallowing the changing of lock bits and
+	 *  auxiliary row data until a chip erase has been performed
+	 */
+	NVM_COMMAND_SET_SECURITY_BIT           = NVMCTRL_CTRLA_CMD_SSB,
+
+	/** Enter power reduction mode in the NVM controller to reduce the power
+	 *  consumption of the system
+	 */
+	NVM_COMMAND_ENTER_LOW_POWER_MODE       = NVMCTRL_CTRLA_CMD_SPRM,
+
+	/** Exit power reduction mode in the NVM controller to allow other NVM
+	 *  commands to be issued
+	 */
+	NVM_COMMAND_EXIT_LOW_POWER_MODE        = NVMCTRL_CTRLA_CMD_CPRM,
+#ifdef FEATURE_NVM_RWWEE
+	/** Read while write (RWW) EEPROM area erase row */
+	NVM_COMMAND_RWWEE_ERASE_ROW            = NVMCTRL_CTRLA_CMD_RWWEEER,
+	/** RWW EEPROM write page */
+	NVM_COMMAND_RWWEE_WRITE_PAGE           = NVMCTRL_CTRLA_CMD_RWWEEWP,
+#endif
+};
+
+/**
+ * \brief NVM controller power reduction mode configurations.
+ *
+ * Power reduction modes of the NVM controller, to conserve power while the
+ * device is in sleep.
+ */
+enum nvm_sleep_power_mode {
+	/** NVM controller exits low-power mode on first access after sleep */
+	NVM_SLEEP_POWER_MODE_WAKEONACCESS  = NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val,
+	/** NVM controller exits low-power mode when the device exits sleep mode */
+	NVM_SLEEP_POWER_MODE_WAKEUPINSTANT = NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val,
+	/** Power reduction mode in the NVM controller disabled */
+	NVM_SLEEP_POWER_MODE_ALWAYS_AWAKE  = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val,
+};
+
+/**
+ * \brief NVM controller cache readmode configuration.
+ *
+ * Control how the NVM cache prefetch data from flash.
+ *
+ */
+enum nvm_cache_readmode {
+	/** The NVM Controller (cache system) does not insert wait states on
+	 *  a cache miss. Gives the best system performance.
+	 */
+	NVM_CACHE_READMODE_NO_MISS_PENALTY,
+	/** Reduces power consumption of the cache system, but inserts a
+	 *  wait state each time there is a cache miss
+	 */
+	NVM_CACHE_READMODE_LOW_POWER,
+	/** The cache system ensures that a cache hit or miss takes the same
+	 *  amount of time, determined by the number of programmed flash
+	 *  wait states
+	 */
+	NVM_CACHE_READMODE_DETERMINISTIC,
+};
+
+/**
+ * \brief NVM controller configuration structure.
+ *
+ * Configuration structure for the NVM controller within the device.
+ */
+struct nvm_config {
+	/** Power reduction mode during device sleep */
+	enum nvm_sleep_power_mode sleep_power_mode;
+	/** Manual write mode; if enabled, pages loaded into the NVM buffer will
+	 *  not be written until a separate write command is issued. If disabled,
+	 *  writing to the last byte in the NVM page buffer will trigger an automatic
+	 *  write.
+	 *
+	 *  \note If a partial page is to be written, a manual write command must be
+	 *        executed in either mode.
+	 */
+	bool manual_page_write;
+	/** Number of wait states to insert when reading from flash, to prevent
+	 *  invalid data from being read at high clock frequencies
+	 */
+	uint8_t wait_states;
+
+	/**
+	 * Setting this to true will disable the pre-fetch cache in front of the
+	 * NVM controller
+	 */
+	bool disable_cache;
+#if (SAMC20) || (SAMC21)
+	/**
+	 * Setting this to true will disable the pre-fetch RWW cache in front of the
+	 * NVM controller.
+	 * If RWW cache is enabled, NVM cache will also be enabled.
+	 */
+	bool disable_rww_cache;
+#endif
+	/**
+	 * Select the mode for  how the cache will pre-fetch data from the flash
+	 */
+	enum nvm_cache_readmode cache_readmode;
+};
+
+/**
+ * \brief NVM memory parameter structure.
+ *
+ * Structure containing the memory layout parameters of the NVM module.
+ */
+struct nvm_parameters {
+	/** Number of bytes per page */
+	uint8_t  page_size;
+	/** Number of pages in the main array */
+	uint16_t nvm_number_of_pages;
+	/** Size of the emulated EEPROM memory section configured in the NVM
+	 *  auxiliary memory space */
+	uint32_t eeprom_number_of_pages;
+	/** Size of the Bootloader memory section configured in the NVM auxiliary
+	 *  memory space */
+	uint32_t bootloader_number_of_pages;
+#ifdef FEATURE_NVM_RWWEE
+	/** Number of pages in read while write EEPROM (RWWEE) emulation area */
+	uint16_t rww_eeprom_number_of_pages;
+#endif
+};
+
+/**
+ * \brief Bootloader size.
+ *
+ * Available bootloader protection sizes in kilobytes.
+ *
+ */
+enum nvm_bootloader_size {
+	/** Boot Loader Size is 32768 bytes */
+	NVM_BOOTLOADER_SIZE_128,
+	/** Boot Loader Size is 16384 bytes */
+	NVM_BOOTLOADER_SIZE_64,
+	/** Boot Loader Size is 8192 bytes */
+	NVM_BOOTLOADER_SIZE_32,
+	/** Boot Loader Size is 4096 bytes */
+	NVM_BOOTLOADER_SIZE_16,
+	/** Boot Loader Size is 2048 bytes */
+	NVM_BOOTLOADER_SIZE_8,
+	/** Boot Loader Size is 1024 bytes */
+	NVM_BOOTLOADER_SIZE_4,
+	/** Boot Loader Size is 512 bytes */
+	NVM_BOOTLOADER_SIZE_2,
+	/** Boot Loader Size is 0 bytes */
+	NVM_BOOTLOADER_SIZE_0,
+};
+
+/**
+ * \brief EEPROM emulator size.
+ *
+ * Available space in flash dedicated for EEPROM emulator in bytes.
+ *
+ */
+enum nvm_eeprom_emulator_size {
+	/** EEPROM Size for EEPROM emulation is 16384 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_16384,
+	/** EEPROM Size for EEPROM emulation is 8192 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_8192,
+	/** EEPROM Size for EEPROM emulation is 4096 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_4096,
+	/** EEPROM Size for EEPROM emulation is 2048 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_2048,
+	/** EEPROM Size for EEPROM emulation is 1024 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_1024,
+	/** EEPROM Size for EEPROM emulation is 512 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_512,
+	/** EEPROM Size for EEPROM emulation is 256 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_256,
+	/** EEPROM Size for EEPROM emulation is 0 bytes */
+	NVM_EEPROM_EMULATOR_SIZE_0,
+};
+
+/**
+ * \brief BOD33 Action.
+ *
+ * What action should be triggered when BOD33 is detected.
+ *
+ */
+enum nvm_bod33_action {
+	/** No action */
+	NVM_BOD33_ACTION_NONE,
+	/** The BOD33 generates a reset */
+	NVM_BOD33_ACTION_RESET,
+	/** The BOD33 generates an interrupt */
+	NVM_BOD33_ACTION_INTERRUPT,
+};
+
+#ifdef FEATURE_BOD12
+/**
+ * \brief BOD12 Action.
+ *
+ * What action should be triggered when BOD12 is detected.
+ *
+ */
+enum nvm_bod12_action {
+	/** No action */
+	NVM_BOD12_ACTION_NONE,
+	/** The BOD12 generates a reset */
+	NVM_BOD12_ACTION_RESET,
+	/** The BOD12 generates an interrupt */
+	NVM_BOD12_ACTION_INTERRUPT,
+};
+#endif
+
+/**
+ * \brief WDT Window time-out period.
+ *
+ * Window mode time-out period in clock cycles.
+ *
+ */
+enum nvm_wdt_window_timeout {
+	/** 8 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_8,
+	/** 16 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_16,
+	/** 32 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_32,
+	/** 64 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_64,
+	/** 128 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_128,
+	/** 256 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_256,
+	/** 512 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_512,
+	/** 1024 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_1024,
+	/** 2048 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_2048,
+	/** 4096 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_4096,
+	/** 8192 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_8192,
+	/** 16384 clock cycles */
+	NVM_WDT_WINDOW_TIMEOUT_PERIOD_16384,
+};
+
+/**
+ * \brief WDT Early warning offset.
+ *
+ * This setting determine how many GCLK_WDT cycles before a watchdog time-out period
+ * an early warning interrupt should be triggered.
+ *
+ */
+enum nvm_wdt_early_warning_offset {
+	/** 8 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_8,
+	/** 16 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_16,
+	/** 32 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_32,
+	/** 64 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_64,
+	/** 128 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_128,
+	/** 256 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_256,
+	/** 512 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_512,
+	/** 1024 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_1024,
+	/** 2048 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_2048,
+	/** 4096 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_4096,
+	/** 8192 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_8192,
+	/** 16384 clock cycles */
+	NVM_WDT_EARLY_WARNING_OFFSET_16384,
+};
+
+/**
+ * \brief NVM user row fuse setting structure.
+ *
+ * This structure contain the layout of the first 64 bits of the user row
+ * which contain the fuse settings.
+ */
+struct nvm_fusebits {
+	/** Bootloader size */
+	enum nvm_bootloader_size          bootloader_size;
+	/** EEPROM emulation area size */
+	enum nvm_eeprom_emulator_size     eeprom_size;
+#if (SAMC20) || (SAMC21)
+	/** BODVDD Threshold level at power on */
+	uint8_t                           bodvdd_level;
+	/** BODVDD Enable at power on */
+	bool                              bodvdd_enable;
+	/** BODVDD Action at power on */
+	enum nvm_bod33_action             bodvdd_action;
+	/* BODVDD Hysteresis at power on */
+	bool                              bodvdd_hysteresis;
+#else
+	/** BOD33 Threshold level at power on */
+	uint8_t                           bod33_level;
+	/** BOD33 Enable at power on */
+	bool                              bod33_enable;
+	/** BOD33 Action at power on */
+	enum nvm_bod33_action             bod33_action;
+	/* BOD33 Hysteresis at power on */
+	bool                              bod33_hysteresis;
+#endif
+	/** WDT Enable at power on */
+	bool                              wdt_enable;
+	/** WDT Always-on at power on */
+	bool                              wdt_always_on;
+	/** WDT Period at power on */
+	uint8_t                           wdt_timeout_period;
+	/** WDT Window mode time-out at power on */
+	enum nvm_wdt_window_timeout       wdt_window_timeout;
+	/** WDT Early warning interrupt time offset at power on */
+	enum nvm_wdt_early_warning_offset wdt_early_warning_offset;
+	/** WDT Window mode enabled at power on */
+	bool                              wdt_window_mode_enable_at_poweron;
+	/** NVM Lock bits */
+	uint16_t                          lockbits;
+#ifdef FEATURE_BOD12
+	/** BOD12 Threshold level at power on */
+	uint8_t                           bod12_level;
+	/** BOD12 Enable at power on */
+	bool                              bod12_enable;
+	/** BOD12 Action at power on */
+	enum nvm_bod12_action             bod12_action;
+	/* BOD12 Hysteresis at power on */
+	bool                              bod12_hysteresis;
+#endif
+};
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes an NVM controller configuration structure to defaults.
+ *
+ * Initializes a given NVM controller configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li Power reduction mode enabled after sleep mode until first NVM access
+ *  \li Automatic page write mode disabled
+ *  \li Number of FLASH wait states left unchanged
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ *
+ */
+static inline void nvm_get_config_defaults(
+		struct nvm_config *const config)
+{
+	/* Sanity check the parameters */
+	Assert(config);
+
+	/* Write the default configuration for the NVM configuration */
+	config->sleep_power_mode  = NVM_SLEEP_POWER_MODE_WAKEONACCESS;
+	config->manual_page_write = true;
+	config->wait_states       = NVMCTRL->CTRLB.bit.RWS;
+	config->disable_cache     = false;
+#if (SAMC20) || (SAMC21)
+	config->disable_rww_cache = false;
+#endif
+	config->cache_readmode    = NVM_CACHE_READMODE_NO_MISS_PENALTY;
+}
+
+enum status_code nvm_set_config(
+		const struct nvm_config *const config);
+
+/**
+ * \brief Checks if the NVM controller is ready to accept a new command.
+ *
+ * Checks the NVM controller to determine if it is currently busy execution an
+ * operation, or ready for a new command.
+ *
+ * \return Busy state of the NVM controller.
+ *
+ * \retval true   If the hardware module is ready for a new command
+ * \retval false  If the hardware module is busy executing a command
+ *
+ */
+static inline bool nvm_is_ready(void)
+{
+	/* Get a pointer to the module hardware instance */
+	Nvmctrl *const nvm_module = NVMCTRL;
+
+	return nvm_module->INTFLAG.reg & NVMCTRL_INTFLAG_READY;
+}
+
+/** @} */
+
+/**
+ * \name NVM Access Management
+ * @{
+ */
+
+void nvm_get_parameters(
+		struct nvm_parameters *const parameters);
+
+enum status_code nvm_write_buffer(
+		const uint32_t destination_address,
+		const uint8_t *buffer,
+		uint16_t length);
+
+enum status_code nvm_read_buffer(
+		const uint32_t source_address,
+		uint8_t *const buffer,
+		uint16_t length);
+
+enum status_code nvm_update_buffer(
+		const uint32_t destination_address,
+		uint8_t *const buffer,
+		uint16_t offset,
+		uint16_t length);
+
+enum status_code nvm_erase_row(
+		const uint32_t row_address);
+
+enum status_code nvm_execute_command(
+		const enum nvm_command command,
+		const uint32_t address,
+		const uint32_t parameter);
+
+enum status_code nvm_get_fuses(struct nvm_fusebits *fusebits);
+enum status_code nvm_set_fuses(struct nvm_fusebits *fb);
+
+bool nvm_is_page_locked(uint16_t page_number);
+
+/**
+ * \brief Retrieves the error code of the last issued NVM operation.
+ *
+ * Retrieves the error code from the last executed NVM operation. Once
+ * retrieved, any error state flags in the controller are cleared.
+ *
+ * \note The \ref nvm_is_ready() function is an exception. Thus, errors
+ *       retrieved after running this function should be valid for the function
+ *       executed before \ref nvm_is_ready().
+ *
+ * \return Error caused by the last NVM operation.
+ *
+ * \retval NVM_ERROR_NONE  No error occurred in the last NVM operation
+ *
+ * \retval NVM_ERROR_LOCK  The last NVM operation attempted to access a locked
+ *                         region
+ * \retval NVM_ERROR_PROG  An invalid NVM command was issued
+ */
+static inline enum nvm_error nvm_get_error(void)
+{
+	enum nvm_error ret_val;
+
+	/* Get a pointer to the module hardware instance */
+	Nvmctrl *const nvm_module = NVMCTRL;
+
+	/* Mask out non-error bits */
+	ret_val = (enum nvm_error)(nvm_module->STATUS.reg & NVM_ERRORS_MASK);
+
+	/* Clear error flags */
+	nvm_module->STATUS.reg = NVM_ERRORS_MASK;
+
+	/* Return error code from the NVM controller */
+	return ret_val;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_nvm_extra Extra Information for NVM Driver
+ *
+ * \section asfdoc_sam0_nvm_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *  <tr>
+ *   <th>Acronym</th>
+ *   <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *   <td>NVM</td>
+ *   <td>Non-Volatile Memory</td>
+ *  </tr>
+ *  <tr>
+ *   <td>EEPROM</td>
+ *   <td>Electrically Erasable Programmable Read-Only Memory</td>
+ *  </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_nvm_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_nvm_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_nvm_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Removed BOD12 reference, removed nvm_set_fuses() API</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added functions to read/write fuse settings</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added support for NVM cache configuration</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Updated initialization function to also enable the digital interface
+ *          clock to the module if it is disabled</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_nvm_exqsg Examples for NVM Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_nvm_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_nvm_basic_use_case
+ *
+ * \page asfdoc_sam0_nvm_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42114E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30/R34 and SAM DA1</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42114D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42114C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42114B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42114A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif /* NVM_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/nvm/quick_start_basic/qs_nvm_basic.h

@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief SAM Non Volatile Memory Driver Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_nvm_basic_use_case Quick Start Guide for NVM - Basic
+ *
+ * In this use case, the NVM module is configured for:
+ *  \li Power reduction mode enabled after sleep mode until first NVM access
+ *  \li Automatic page write commands issued to commit data as pages are written
+ *      to the internal buffer
+ *  \li Zero wait states when reading FLASH memory
+ *  \li No memory space for the EEPROM
+ *  \li No protected bootloader section
+ *
+ * This use case sets up the NVM controller to write a page of data to flash,
+ * and then read it back into the same buffer.
+ *
+ * \section asfdoc_sam0_nvm_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_nvm_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_nvm_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_nvm_basic.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_nvm_basic.c setup_init
+ *
+ * \subsection asfdoc_sam0_nvm_basic_use_case_setup_flow Workflow
+ * -# Create an NVM module configuration struct, which can be filled
+ *    out to adjust the configuration of the NVM controller.
+ *    \snippet qs_nvm_basic.c setup_1
+ * -# Initialize the NVM configuration struct with the module's default
+ *    values.
+ *    \snippet qs_nvm_basic.c setup_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ * -# Enable automatic page write mode. The new data will be written to NVM automaticly.
+ *    \snippet qs_nvm_basic.c setup_3
+ *    \note If automatic page write mode is disabled, the data will not write to NVM
+ *          until the NVM write command has been invoked. For safe use of the NVM module,
+ *          disable automatic page write mode and use write command to commit data is
+ *          recommended.
+ *
+ * -# Configure NVM controller with the created configuration struct settings.
+ *    \snippet qs_nvm_basic.c setup_4
+ *
+ * \section asfdoc_sam0_nvm_basic_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_nvm_basic_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_nvm_basic.c main
+ *
+ * \subsection asfdoc_sam0_nvm_basic_use_case_main_flow Workflow
+ * -# Set up a buffer, one NVM page in size, to hold data to read or write into
+ *    NVM memory.
+ *    \snippet qs_nvm_basic.c main_1
+ * -# Fill the buffer with a pattern of data.
+ *    \snippet qs_nvm_basic.c main_2
+ * -# Create a variable to hold the error status from the called NVM functions.
+ *    \snippet qs_nvm_basic.c main_3
+ * -# Erase a page of NVM data. As the NVM could be busy initializing or
+ *    completing a previous operation, a loop is used to retry the command while
+ *    the NVM controller is busy.
+ *    \snippet qs_nvm_basic.c main_4
+ *    \note This must be performed before writing new data into an NVM page.
+ *
+ * -# Write the data buffer to the previously erased page of the NVM.
+ *    \snippet qs_nvm_basic.c main_5
+ *    \note The new data will be written to NVM memory automatically, as the
+ *          NVM controller is configured in automatic page write mode.
+ *
+ * -# Read back the written page of page from the NVM into the buffer.
+ *    \snippet qs_nvm_basic.c main_6
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+

firmware/SendcommCmdsys/src/ASF/sam0/drivers/port/port.c

@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include <port.h>
+
+/**
+ *  \brief Writes a Port pin configuration to the hardware module.
+ *
+ *  Writes out a given configuration of a Port pin configuration to the hardware
+ *  module.
+ *
+ *  \note If the pin direction is set as an output, the pull-up/pull-down input
+ *        configuration setting is ignored.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to configure
+ *  \param[in] config    Configuration settings for the pin
+ */
+void port_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+	pinmux_config.powersave    = config->powersave;
+
+	system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
+}
+
+/**
+ *  \brief Writes a Port group configuration group to the hardware module.
+ *
+ *  Writes out a given configuration of a Port group configuration to the
+ *  hardware module.
+ *
+ *  \note If the pin direction is set as an output, the pull-up/pull-down input
+ *        configuration setting is ignored.
+ *
+ *  \param[out] port    Base of the PORT module to write to
+ *  \param[in]  mask    Mask of the port pin(s) to configure
+ *  \param[in]  config  Configuration settings for the pin group
+ */
+void port_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(port);
+	Assert(config);
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+	pinmux_config.powersave    = config->powersave;
+
+	system_pinmux_group_set_config(port, mask, &pinmux_config);
+}

firmware/SendcommCmdsys/src/ASF/sam0/drivers/port/port.h

@@ -0,0 +1,785 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (c) 2012-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef PORT_H_INCLUDED
+#define PORT_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_port_group SAM Port (PORT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's General
+ * Purpose Input/Output (GPIO) pin functionality, for manual pin state reading
+ * and writing.
+ *
+ * The following peripheral is used by this module:
+ *  - PORT (GPIO Management)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34
+ *  - Atmel | SMART SAM R35
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_port_prerequisites
+ *  - \ref asfdoc_sam0_port_module_overview
+ *  - \ref asfdoc_sam0_port_special_considerations
+ *  - \ref asfdoc_sam0_port_extra_info
+ *  - \ref asfdoc_sam0_port_examples
+ *  - \ref asfdoc_sam0_port_api_overview
+ *
+ *
+ * \section asfdoc_sam0_port_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_port_module_overview Module Overview
+ *
+ * The device GPIO (PORT) module provides an interface between the user
+ * application logic and external hardware peripherals, when general pin state
+ * manipulation is required. This driver provides an easy-to-use interface to
+ * the physical pin input samplers and output drivers, so that pins can be read
+ * from or written to for general purpose external hardware control.
+ *
+ * \subsection asfdoc_sam0_port_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_PORT_INPUT_EVENT</td>
+ *    <td>SAM L21/L22/C20/C21/R30/R34/R35</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_port_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how
+ * this module is interconnected within the device.
+ *
+ * \anchor asfdoc_sam0_port_module_int_connections
+ * \dot
+ * digraph overview {
+ *   node [label="Port Pad" shape=square] pad;
+ *
+ *   subgraph driver {
+ *     node [label="Peripheral MUX" shape=trapezium] pinmux;
+ *     node [label="GPIO Module" shape=ellipse] gpio;
+ *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ *   }
+ *
+ *   pinmux -> gpio;
+ *   pad    -> pinmux;
+ *   pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ *
+ * \section asfdoc_sam0_port_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampler can be disabled when the pin is configured
+ * in pure output mode to save power; reading the pin state of a pin configured
+ * in output-only mode will read the logical output state that was last set.
+ *
+ * \section asfdoc_sam0_port_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_port_extra. This includes:
+ *  - \ref asfdoc_sam0_port_extra_acronyms
+ *  - \ref asfdoc_sam0_port_extra_dependencies
+ *  - \ref asfdoc_sam0_port_extra_errata
+ *  - \ref asfdoc_sam0_port_extra_history
+ *
+ *
+ * \section asfdoc_sam0_port_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_port_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_port_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <pinmux.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Driver Feature Definition
+ * Define port features set according to different device family.
+ * @{
+*/
+#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089) || defined(__DOXYGEN__)
+/** Event input control feature support for PORT group. */
+#  define FEATURE_PORT_INPUT_EVENT
+#endif
+/*@}*/
+
+/** \name PORT Alias Macros
+ * @{
+ */
+
+/** Convenience definition for GPIO module group A on the device (if
+ *  available). */
+#if (PORT_GROUPS > 0) || defined(__DOXYGEN__)
+#  define PORTA             PORT->Group[0]
+#endif
+
+#if (PORT_GROUPS > 1) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group B on the device (if
+ *  available). */
+#  define PORTB             PORT->Group[1]
+#endif
+
+#if (PORT_GROUPS > 2) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group C on the device (if
+ *  available). */
+#  define PORTC             PORT->Group[2]
+#endif
+
+#if (PORT_GROUPS > 3) || defined(__DOXYGEN__)
+/** Convenience definition for GPIO module group D on the device (if
+ *  available). */
+#  define PORTD             PORT->Group[3]
+#endif
+
+/** @} */
+
+/**
+ *  \brief Port pin direction configuration enum.
+ *
+ *  Enum for the possible pin direction settings of the port pin configuration
+ *  structure, to indicate the direction the pin should use.
+ */
+enum port_pin_dir {
+	/** The pin's input buffer should be enabled, so that the pin state can
+	 *  be read */
+	PORT_PIN_DIR_INPUT               = SYSTEM_PINMUX_PIN_DIR_INPUT,
+	/** The pin's output buffer should be enabled, so that the pin state can
+	 *  be set */
+	PORT_PIN_DIR_OUTPUT              = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+	/** The pin's output and input buffers should be enabled, so that the pin
+	 *  state can be set and read back */
+	PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ *  \brief Port pin input pull configuration enum.
+ *
+ *  Enum for the possible pin pull settings of the port pin configuration
+ *  structure, to indicate the type of logic level pull the pin should use.
+ */
+enum port_pin_pull {
+	/** No logical pull should be applied to the pin */
+	PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
+	/** Pin should be pulled up when idle */
+	PORT_PIN_PULL_UP   = SYSTEM_PINMUX_PIN_PULL_UP,
+	/** Pin should be pulled down when idle */
+	PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+#ifdef FEATURE_PORT_INPUT_EVENT
+/**
+ *  \brief Port input event action.
+ *
+ *  List of port input events action on pin.
+ */
+enum port_input_event_action {
+	/** Event out to pin */
+	PORT_INPUT_EVENT_ACTION_OUT = 0,
+	/** Set output register of pin on event */
+	PORT_INPUT_EVENT_ACTION_SET,
+	/** Clear output register pin on event */
+	PORT_INPUT_EVENT_ACTION_CLR,
+	/** Toggle output register pin on event */
+	PORT_INPUT_EVENT_ACTION_TGL,
+};
+
+/**
+ *  \brief Port input event.
+ *
+ *  List of port input events.
+ */
+enum port_input_event{
+	/** Port input event 0 */
+	PORT_INPUT_EVENT_0 = 0,
+	/** Port input event 1 */
+	PORT_INPUT_EVENT_1 = 1,
+	/** Port input event 2 */
+	PORT_INPUT_EVENT_2 = 2,
+	/** Port input event 3 */
+	PORT_INPUT_EVENT_3 = 3,
+};
+
+/**
+ *  \brief Port input event configuration structure.
+ *
+ *  Configuration structure for a port input event.
+ */
+struct port_input_event_config{
+	/** Port input event action */
+	enum port_input_event_action  action;
+	/** GPIO pin */
+	uint8_t gpio_pin;
+};
+#endif
+
+/**
+ *  \brief Port pin configuration structure.
+ *
+ *  Configuration structure for a port pin instance. This structure should be
+ *  initialized by the \ref port_get_config_defaults() function before being
+ *  modified by the user application.
+ */
+struct port_config {
+	/** Port buffer input/output direction */
+	enum port_pin_dir  direction;
+
+	/** Port pull-up/pull-down for input pins */
+	enum port_pin_pull input_pull;
+
+	/** Enable lowest possible powerstate on the pin
+	 *
+	 *  \note All other configurations will be ignored, the pin will be disabled.
+	 */
+	bool powersave;
+};
+
+/** \name State Reading/Writing (Physical Group Orientated)
+ * @{
+ */
+
+/**
+ *  \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ *  Retrieves the PORT module group instance associated with a given logical
+ *  GPIO pin number.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to convert
+ *
+ *  \return Base address of the associated PORT module.
+ */
+static inline PortGroup* port_get_group_from_gpio_pin(
+		const uint8_t gpio_pin)
+{
+	return system_pinmux_get_group_from_gpio_pin(gpio_pin);
+}
+
+/**
+ *  \brief Retrieves the state of a group of port pins that are configured as inputs.
+ *
+ *  Reads the current logic level of a port module's pins and returns the
+ *  current levels as a bitmask.
+ *
+ *  \param[in] port  Base of the PORT module to read from
+ *  \param[in] mask  Mask of the port pin(s) to read
+ *
+ *  \return Status of the port pin(s) input buffers.
+ */
+static inline uint32_t port_group_get_input_level(
+		const PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	return (port->IN.reg & mask);
+}
+
+/**
+ *  \brief Retrieves the state of a group of port pins that are configured as outputs.
+ *
+ *  Reads the current logical output level of a port module's pins and returns
+ *  the current levels as a bitmask.
+ *
+ *  \param[in] port  Base of the PORT module to read from
+ *  \param[in] mask  Mask of the port pin(s) to read
+ *
+ *  \return Status of the port pin(s) output buffers.
+ */
+static inline uint32_t port_group_get_output_level(
+		const PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	return (port->OUT.reg & mask);
+}
+
+/**
+ *  \brief Sets the state of a group of port pins that are configured as outputs.
+ *
+ *  Sets the current output level of a port module's pins to a given logic
+ *  level.
+ *
+ *  \param[out] port        Base of the PORT module to write to
+ *  \param[in]  mask        Mask of the port pin(s) to change
+ *  \param[in]  level_mask  Mask of the port level(s) to set
+ */
+static inline void port_group_set_output_level(
+		PortGroup *const port,
+		const uint32_t mask,
+		const uint32_t level_mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	port->OUTSET.reg = (mask &  level_mask);
+	port->OUTCLR.reg = (mask & ~level_mask);
+}
+
+/**
+ *  \brief Toggles the state of a group of port pins that are configured as an outputs.
+ *
+ *  Toggles the current output levels of a port module's pins.
+ *
+ *  \param[out] port  Base of the PORT module to write to
+ *  \param[in]  mask  Mask of the port pin(s) to toggle
+ */
+static inline void port_group_toggle_output_level(
+		PortGroup *const port,
+		const uint32_t mask)
+{
+	/* Sanity check arguments */
+	Assert(port);
+
+	port->OUTTGL.reg = mask;
+}
+
+/** @} */
+
+/** \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ *  \brief Initializes a Port pin/group configuration structure to defaults.
+ *
+ *  Initializes a given Port pin/group configuration structure to a set of
+ *  known default values. This function should be called on all new
+ *  instances of these configuration structures before being modified by the
+ *  user application.
+ *
+ *  The default configuration is as follows:
+ *   \li Input mode with internal pull-up enabled
+ *
+ *  \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void port_get_config_defaults(
+		struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->direction  = PORT_PIN_DIR_INPUT;
+	config->input_pull = PORT_PIN_PULL_UP;
+	config->powersave  = false;
+}
+
+void port_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct port_config *const config);
+
+void port_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct port_config *const config);
+
+/** @} */
+
+/** \name State Reading/Writing (Logical Pin Orientated)
+ * @{
+ */
+
+/**
+ *  \brief Retrieves the state of a port pin that is configured as an input.
+ *
+ *  Reads the current logic level of a port pin and returns the current
+ *  level as a Boolean value.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to read
+ *
+ *  \return Status of the port pin's input buffer.
+ */
+static inline bool port_pin_get_input_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	return (port_base->IN.reg & pin_mask);
+}
+
+/**
+ *  \brief Retrieves the state of a port pin that is configured as an output.
+ *
+ *  Reads the current logical output level of a port pin and returns the current
+ *  level as a Boolean value.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to read
+ *
+ *  \return Status of the port pin's output buffer.
+ */
+static inline bool port_pin_get_output_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	return (port_base->OUT.reg & pin_mask);
+}
+
+/**
+ *  \brief Sets the state of a port pin that is configured as an output.
+ *
+ *  Sets the current output level of a port pin to a given logic level.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to write to
+ *  \param[in] level     Logical level to set the given pin to
+ */
+static inline void port_pin_set_output_level(
+		const uint8_t gpio_pin,
+		const bool level)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	/* Set the pin to high or low atomically based on the requested level */
+	if (level) {
+		port_base->OUTSET.reg = pin_mask;
+	} else {
+		port_base->OUTCLR.reg = pin_mask;
+	}
+}
+
+/**
+ *  \brief Toggles the state of a port pin that is configured as an output.
+ *
+ *  Toggles the current output level of a port pin.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to toggle
+ */
+static inline void port_pin_toggle_output_level(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+	/* Toggle pin output level */
+	port_base->OUTTGL.reg = pin_mask;
+}
+
+/** @} */
+
+#ifdef FEATURE_PORT_INPUT_EVENT
+
+/** \name Port Input Event
+ * @{
+ */
+
+/**
+ *  \brief Enable the port event input.
+ *
+ *  Enable the port event input with the given pin and event.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin
+ *  \param[in] n  Port input event
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+static inline enum status_code port_enable_input_event(
+		const uint8_t gpio_pin,
+		const enum port_input_event n)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ *  \brief Disable the port event input.
+ *
+ *  Disable the port event input with the given pin and event.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin
+ *  \param[in] gpio_pin  Port input event
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+static inline enum status_code port_disable_input_event(
+		const uint8_t gpio_pin,
+		const enum port_input_event n)
+{
+	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieve the default configuration for port input event.
+ *
+ * Fills a configuration structure with the default configuration for port input event:
+ *   - Event output to pin
+ *   - Event action to be executed on PIN 0
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void port_input_event_get_config_defaults(
+		struct port_input_event_config *const config)
+{
+	Assert(config);
+	config->action   = PORT_INPUT_EVENT_ACTION_OUT;
+	config->gpio_pin = 0;
+}
+
+/**
+ * \brief Configure port input event.
+ *
+ * Configures port input event with the given configuration settings.
+ *
+ * \param[in] config  Port input even configuration structure containing the new config
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+
+static inline enum status_code port_input_event_set_config(
+		const enum port_input_event n,
+		struct port_input_event_config *const config)
+{
+	Assert(config);
+	PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin);
+	uint8_t pin_index = config->gpio_pin % 32;
+	struct port_config pin_conf;
+
+	port_get_config_defaults(&pin_conf);
+	/* Configure the GPIO pin as outputs*/
+	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+	port_pin_set_config(config->gpio_pin, &pin_conf);
+
+	switch (n) {
+		case PORT_INPUT_EVENT_0:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
+									| PORT_EVCTRL_PID0(pin_index);
+			break;
+		case PORT_INPUT_EVENT_1:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action)
+						   		   | PORT_EVCTRL_PID1(pin_index);
+			break;
+		case PORT_INPUT_EVENT_2:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action)
+						   		   | PORT_EVCTRL_PID2(pin_index);
+			break;
+		case PORT_INPUT_EVENT_3:
+			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action)
+						   		   | PORT_EVCTRL_PID3(pin_index);
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+	return STATUS_OK;
+}
+
+/** @} */
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_port_extra Extra Information for PORT Driver
+ *
+ * \section asfdoc_sam0_port_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>GPIO</td>
+ *		<td>General Purpose Input/Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MUX</td>
+ *		<td>Multiplexer</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_port_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_port_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_port_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Added input event feature</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_port_exqsg Examples for PORT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_port_basic_use_case
+ *
+ * \page asfdoc_sam0_port_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113E</td>
+ *		<td>12/2015</td>
+ *		<td>Added input event feature.
+ *			Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30/R34 and SAM DA1.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42113A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial document release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif

firmware/SendcommCmdsys/src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h

@@ -0,0 +1,98 @@
+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_port_basic_use_case Quick Start Guide for PORT - Basic
+ *
+ * In this use case, the PORT module is configured for:
+ *  \li One pin in input mode, with pull-up enabled
+ *  \li One pin in output mode
+ *
+ * This use case sets up the PORT to read the current state of a GPIO pin set as
+ * an input, and mirrors the opposite logical state on a pin configured as an
+ * output.
+ *
+ * \section asfdoc_sam0_port_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_port_basic.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_port_basic.c setup_init
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_flow Workflow
+ * -# Create a PORT module pin configuration struct, which can be filled out to
+ *    adjust the configuration of a single port pin.
+ *    \snippet qs_port_basic.c setup_1
+ * -# Initialize the pin configuration struct with the module's default values.
+ *    \snippet qs_port_basic.c setup_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Adjust the configuration struct to request an input pin.
+ *    \snippet qs_port_basic.c setup_3
+ * -# Configure push button pin with the initialized pin configuration struct, to enable
+ *    the input sampler on the pin.
+ *    \snippet qs_port_basic.c setup_4
+ * -# Adjust the configuration struct to request an output pin.
+ *    \snippet qs_port_basic.c setup_5
+ *    \note The existing configuration struct may be re-used, as long as any
+ *          values that have been altered from the default settings are taken
+ *          into account by the user application.
+ *
+ * -# Configure LED pin with the initialized pin configuration struct, to enable
+ *    the output driver on the pin.
+ *    \snippet qs_port_basic.c setup_6
+ *
+ * \section asfdoc_sam0_port_basic_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_port_basic.c main
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_flow Workflow
+ * -# Read in the current input sampler state of push button pin, which has been
+ *    configured as an input in the use-case setup code.
+ *    \snippet qs_port_basic.c main_1
+ * -# Write the inverted pin level state to LED pin, which has been configured as
+ *    an output in the use-case setup code.
+ *    \snippet qs_port_basic.c main_2
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/rtc/rtc_count_interrupt.h

@@ -0,0 +1,80 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Interrupt Mode)
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef RTC_COUNT_INTERRUPT_H_INCLUDED
+#define RTC_COUNT_INTERRUPT_H_INCLUDED
+
+#include "rtc_count.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_rtc_count_group
+ * @{
+ */
+
+ /**
+ * \name Callbacks
+ * @{
+ */
+enum status_code rtc_count_register_callback(
+		struct rtc_module *const module,
+		rtc_count_callback_t callback,
+		enum rtc_count_callback callback_type);
+
+enum status_code rtc_count_unregister_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type);
+
+void rtc_count_enable_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type);
+
+void rtc_count_disable_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type);
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTC_COUNT_INTERRUPT_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/rtc/rtc_sam_l_c/rtc_count.c

@@ -0,0 +1,941 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Mode)
+ *
+ * Copyright (c) 2012-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "rtc_count.h"
+#include <clock.h>
+#include <gclk.h>
+#include "conf_rtc.h"
+
+#if !defined(__DOXYGEN__)
+struct rtc_module *_rtc_instance[RTC_INST_NUM];
+#endif
+
+#if !defined(RTC_CLOCK_SOURCE)
+#  warning  RTC_CLOCK_SOURCE is not defined, assuming RTC_CLOCK_SELECTION_ULP1K.
+#  define RTC_CLOCK_SOURCE RTC_CLOCK_SELECTION_ULP1K
+#endif
+
+/**
+ * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+ *
+ * Checks to see if the underlying hardware peripheral module(s) are currently
+ * synchronizing across multiple clock domains to the hardware bus, This
+ * function can be used to delay further operations on a module until such time
+ * that it is ready, to prevent blocking delays for synchronization in the
+ * user application.
+ *
+ * \param[in]  module  RTC hardware module
+ *
+ * \return Synchronization status of the underlying hardware module(s).
+ *
+ * \retval true  if the module synchronization is ongoing
+ * \retval false if the module has completed synchronization
+ */
+static bool rtc_count_is_syncing(struct rtc_module *const module)
+{
+ 	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	if (rtc_module->MODE0.SYNCBUSY.reg) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * \brief Enables the RTC module.
+ *
+ * Enables the RTC module once it has been configured, ready for use. Most
+ * module configuration parameters cannot be altered while the module is enabled.
+ *
+ * \param[in,out]  module  RTC hardware module
+ */
+void rtc_count_enable(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if RTC_COUNT_ASYNC == true
+	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Enable RTC module. */
+	rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Disables the RTC module.
+ *
+ * Disables the RTC module.
+ *
+ * \param[in,out]  module  RTC hardware module
+ */
+void rtc_count_disable(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if RTC_COUNT_ASYNC == true
+	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
+#endif
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Disbale interrupt */
+	rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_MASK;
+
+	/* Disable RTC module. */
+	rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \brief Resets the RTC module.
+ * Resets the RTC to hardware defaults.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ */
+void rtc_count_reset(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Disable module before reset. */
+	rtc_count_disable(module);
+
+#if RTC_COUNT_ASYNC == true
+	module->registered_callback = 0;
+	module->enabled_callback    = 0;
+#endif
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Initiate software reset. */
+	rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+}
+
+/**
+ * \internal Applies the given configuration.
+ *
+ * Sets the configurations given from the configuration structure to the
+ * hardware module
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in] config  Pointer to the configuration structure
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               RTC configurations was set successfully
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were given
+ */
+static enum status_code _rtc_count_set_config(
+		struct rtc_module *const module,
+		const struct rtc_count_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+#if SAML21 || SAMR30 || (SAMR34) || (SAMR35) || (WLR089)
+	rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0)
+#if (SAML21XXXB) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+				    | (config->enable_read_sync << RTC_MODE0_CTRLA_COUNTSYNC_Pos)
+#endif
+				    | config->prescaler;
+#endif
+#if (SAMC20) || (SAMC21) || (SAML22)
+	rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0) | config->prescaler
+			| (config->enable_read_sync << RTC_MODE0_CTRLA_COUNTSYNC_Pos);
+#endif
+
+	/* Set mode and clear on match if applicable. */
+	switch (config->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Set 32-bit mode and clear on match if applicable. */
+			rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(0);
+
+			/* Check if clear on compare match should be set. */
+			if (config->clear_on_match) {
+				/* Set clear on match. */
+				rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR;
+			}
+			/* Set compare values. */
+			for (uint8_t i = 0; i < RTC_COMP32_NUM; i++) {
+				rtc_count_set_compare(module, config->compare_values[i],
+						(enum rtc_count_compare)i);
+			}
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Set 16bit mode. */
+			rtc_module->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(1);
+
+			/* Check if match on clear is set, and return invalid
+			 * argument if set. */
+			if (config->clear_on_match) {
+				Assert(false);
+				return STATUS_ERR_INVALID_ARG;
+			}
+			/* Set compare values. */
+			for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
+				rtc_count_set_compare(module, config->compare_values[i],
+						(enum rtc_count_compare)i);
+			}
+			break;
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Return status OK if everything was configured. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the RTC module with given configurations.
+ *
+ * Initializes the module, setting up all given configurations to provide
+ * the desired functionality of the RTC.
+ *
+ * \param[out] module  Pointer to the software instance struct
+ * \param[in]   hw      Pointer to hardware instance
+ * \param[in] config  Pointer to the configuration structure
+ *
+ * \return Status of the initialization procedure.
+ * \retval STATUS_OK               If the initialization was run stressfully
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were given
+ */
+enum status_code rtc_count_init(
+		struct rtc_module *const module,
+		Rtc *const hw,
+		const struct rtc_count_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	/* Initialize device instance */
+	module->hw = hw;
+
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_RTC);
+
+	/* Select RTC clock */
+	OSC32KCTRL->RTCCTRL.reg = RTC_CLOCK_SOURCE;
+
+	/* Reset module to hardware defaults. */
+	rtc_count_reset(module);
+
+	/* Save conf_struct internally for continued use. */
+	module->mode                = config->mode;
+
+#  if (RTC_INST_NUM == 1)
+	_rtc_instance[0] = module;
+#  else
+	/* Register this instance for callbacks*/
+	_rtc_instance[_rtc_get_inst_index(hw)] = module;
+#  endif
+
+	/* Set config and return status. */
+	return _rtc_count_set_config(module, config);
+}
+
+/**
+ * \brief Set the current count value to desired value.
+ *
+ * Sets the value of the counter to the specified value.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] count_value  The value to be set in count register
+ *
+ * \return Status of setting the register.
+ * \retval STATUS_OK               If everything was executed correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_count_set_count(
+		struct rtc_module *const module,
+		const uint32_t count_value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set count according to mode */
+	switch(module->mode){
+		case RTC_COUNT_MODE_32BIT:
+			/* Write value to register. */
+			rtc_module->MODE0.COUNT.reg = count_value;
+			break;
+		case RTC_COUNT_MODE_16BIT:
+			/* Check if 16-bit value is provided. */
+			if(count_value > 0xffff){
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Write value to register. */
+			rtc_module->MODE1.COUNT.reg = (uint32_t)count_value;
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the current count value.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ *
+ * Returns the current count value.
+ *
+ * \return The current counter value as a 32-bit unsigned integer.
+ */
+uint32_t rtc_count_get_count(struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Initialize return value. */
+	uint32_t ret_val;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Read value based on mode. */
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Return count value in 32-bit mode. */
+			ret_val = rtc_module->MODE0.COUNT.reg;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Return count value in 16-bit mode. */
+			ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg;
+
+			break;
+
+		default:
+			Assert(false);
+			/* Counter not initialized. Assume counter value 0.*/
+			ret_val = 0;
+			break;
+	}
+
+	return ret_val;
+}
+
+/**
+ * \brief Set the compare value for the specified compare.
+ *
+ * Sets the value specified by the implementer to the requested compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] comp_value  The value to be written to the compare
+ * \param[in] comp_index  Index of the compare to set
+ *
+ * \return Status indicating if compare was successfully set.
+ * \retval STATUS_OK               If compare was successfully set
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
+ */
+enum status_code rtc_count_set_compare(
+		struct rtc_module *const module,
+		const uint32_t comp_value,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set compare values based on operation mode. */
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_COMP32_NUM) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Set compare value for COMP. */
+			rtc_module->MODE0.COMP[comp_index].reg = comp_value;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Check that 16-bit value is provided. */
+			if (comp_value > 0xffff) {
+				Assert(false);
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Set compare value for COMP. */
+			rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff;
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_BAD_FORMAT;
+	}
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Return status if everything is OK. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the current compare value of specified compare.
+ *
+ * Retrieves the current value of the specified compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[out] comp_value  Pointer to 32-bit integer that will be populated with
+ *                         the current compare value
+ * \param[in]  comp_index  Index of compare to check
+ *
+ * \return Status of the reading procedure.
+ * \retval STATUS_OK               If the value was read correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
+ */
+enum status_code rtc_count_get_compare(
+		struct rtc_module *const module,
+		uint32_t *const comp_value,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_COMP32_NUM) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Get compare value for COMP. */
+			*comp_value = rtc_module->MODE0.COMP[comp_index].reg;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity of comp_index. */
+			if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			/* Get compare value for COMP. */
+			*comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg;
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_BAD_FORMAT;
+	}
+	/* Return status showing everything is OK. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Retrieves the value of period.
+ *
+ * Retrieves the value of the period for the 16-bit mode counter.
+ *
+ * \note Only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[out] period_value  Pointer to value for return argument
+ *
+ * \return Status of getting the period value.
+ * \retval STATUS_OK                   If the period value was read correctly
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If incorrect mode was set
+ */
+enum status_code rtc_count_get_period(
+		struct rtc_module *const module,
+		uint16_t *const period_value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Check that correct mode is set. */
+	if (module->mode != RTC_COUNT_MODE_16BIT) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	/* Returns the value. */
+	*period_value = rtc_module->MODE1.PER.reg;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Set the given value to the period.
+ *
+ * Sets the given value to the period.
+ *
+ * \note Only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] period_value  The value to set to the period
+ *
+ * \return Status of setting the period value.
+ * \retval STATUS_OK                   If the period was set correctly
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  If module is not operated in 16-bit mode
+ */
+enum status_code rtc_count_set_period(
+		struct rtc_module *const module,
+		const uint16_t period_value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check that correct mode is set. */
+	if (module->mode != RTC_COUNT_MODE_16BIT) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Write value to register. */
+	rtc_module->MODE1.PER.reg = period_value;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Check if RTC compare match has occurred.
+ *
+ * Checks the compare flag to see if a match has occurred. The compare flag is
+ * set when there is a compare match between counter and the compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] comp_index  Index of compare to check current flag
+ */
+bool rtc_count_is_compare_match(
+		struct rtc_module *const module,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check sanity. */
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (comp_index > RTC_COMP32_NUM) {
+				return false;
+			}
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (comp_index > RTC_NUM_OF_COMP16) {
+				return false;
+			}
+
+			break;
+
+		default:
+			Assert(false);
+			return false;
+	}
+
+	/* Set status of INTFLAG as return argument. */
+	return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP(1 << comp_index)) ? true : false;
+}
+
+/**
+ * \brief Clears RTC compare match flag.
+ *
+ * Clears the compare flag. The compare flag is set when there is a compare
+ * match between the counter and the compare.
+ *
+ * \note Compare 4 and 5 are only available in 16-bit mode.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] comp_index  Index of compare to check current flag
+ *
+ * \return Status indicating if flag was successfully cleared.
+ * \retval STATUS_OK               If flag was successfully cleared
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
+ */
+enum status_code rtc_count_clear_compare_match(
+		struct rtc_module *const module,
+		const enum rtc_count_compare comp_index)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check sanity. */
+	switch (module->mode){
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (comp_index > RTC_COMP32_NUM) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (comp_index > RTC_NUM_OF_COMP16) {
+				return STATUS_ERR_INVALID_ARG;
+			}
+
+			break;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_BAD_FORMAT;
+	}
+
+	/* Clear INTFLAG. */
+	rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index);
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Calibrate for too-slow or too-fast oscillator.
+ *
+ * When used, the RTC will compensate for an inaccurate oscillator. The
+ * RTC module will add or subtract cycles from the RTC prescaler to adjust the
+ * frequency in approximately 1 PPM steps. The provided correction value should
+ * be between 0 and 127, allowing for a maximum 127 PPM correction.
+ *
+ * If no correction is needed, set value to zero.
+ *
+ * \note Can only be used when the RTC is operated in 1Hz.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ * \param[in] value  Ranging from -127 to 127 used for the correction
+ *
+ * \return Status of the calibration procedure.
+ * \retval STATUS_OK               If calibration was executed correctly
+ * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
+ */
+enum status_code rtc_count_frequency_correction(
+		struct rtc_module *const module,
+		const int8_t value)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Check if valid argument. */
+	if (abs(value) > 0x7F) {
+		/* Value bigger than allowed, return invalid argument. */
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	uint32_t new_correction_value;
+
+	/* Load the new correction value as a positive value, sign added later */
+	new_correction_value = abs(value);
+
+	/* Convert to positive value and adjust register sign bit. */
+	if (value < 0) {
+		new_correction_value |= RTC_FREQCORR_SIGN;
+	}
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Set value. */
+	rtc_module->MODE0.FREQCORR.reg = new_correction_value;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	return STATUS_OK;
+}
+
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+/**
+ * \brief Applies the given configuration.
+ *
+ * Sets the configurations given from the configuration structure to the
+ * RTC tamper and it should be called before RTC module enable. 
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in] config  Pointer to the configuration structure
+ *
+ * \return Status of the configuration procedure.
+ * \retval STATUS_OK               RTC configurations was set successfully
+ * \note If tamper input configured as active layer protection, RTC prescaler
+ *       output automatically enabled in the function.
+ */
+enum status_code rtc_tamper_set_config ( 
+		struct rtc_module *const module,
+		struct rtc_tamper_config *const tamper_cfg)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(tamper_cfg);
+
+	Rtc *const rtc_module = module->hw;
+	uint16_t ctrl_b = 0;
+
+	/* Configure enable backup and GP register reset on tamper or not. */
+	if(tamper_cfg->bkup_reset_on_tamper) {
+		rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
+	} else {
+		rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
+	}
+	
+	if (tamper_cfg->gp_reset_on_tamper) {
+		rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
+	} else {
+		rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
+	}
+
+	/* Configure tamper detection of frequency and debounce setting. */
+	ctrl_b = tamper_cfg->actl_freq_div | tamper_cfg->deb_freq_div;
+	if(tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_ASYNC) {
+		ctrl_b |= RTC_MODE0_CTRLB_DEBASYNC;
+	} else if (tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_MAJORITY) {
+		ctrl_b |= RTC_MODE0_CTRLB_DEBMAJ;
+	}
+	if(tamper_cfg->dma_tamper_enable) {
+		ctrl_b |= RTC_MODE0_CTRLB_DMAEN;
+	}
+	if (tamper_cfg->gp0_enable) {
+		ctrl_b |= RTC_MODE0_CTRLB_GP0EN;
+	}
+
+	/* Configure tamper input. */
+	volatile RTC_TAMPCTRL_Type *tamper_ctrl = &(rtc_module->MODE0.TAMPCTRL);
+
+	struct rtc_tamper_input_config in_cfg;
+	for (uint8_t tamper_id = 0; tamper_id < RTC_TAMPER_NUM; tamper_id++) {
+		in_cfg = tamper_cfg->in_cfg[tamper_id];
+
+		if(in_cfg.action == RTC_TAMPER_INPUT_ACTION_ACTL) {
+			ctrl_b |= RTC_MODE0_CTRLB_RTCOUT;
+		}
+	
+		switch(tamper_id) {
+			case 0:
+				tamper_ctrl->bit.IN0ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL0 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC0 = in_cfg.debounce_enable;
+				break;
+			case 1:
+				tamper_ctrl->bit.IN1ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL1 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC1 = in_cfg.debounce_enable;
+				break;
+			case 2:
+				tamper_ctrl->bit.IN2ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL2 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC2 = in_cfg.debounce_enable;
+				break;
+			case 3:
+				tamper_ctrl->bit.IN3ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL3 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC3 = in_cfg.debounce_enable;
+				break;
+			case 4:
+				tamper_ctrl->bit.IN4ACT = in_cfg.action;
+				tamper_ctrl->bit.TAMLVL4 = in_cfg.level;
+				tamper_ctrl->bit.DEBNC4 = in_cfg.debounce_enable;
+				break;
+			default:
+				Assert(false);
+				break;
+		}
+	}
+
+	rtc_module->MODE0.CTRLB.reg = ctrl_b;
+
+	/* Return status OK if everything was configured. */
+	return STATUS_OK;
+}
+
+/**
+ * \brief Get the tamper stamp value.
+ *
+ * \param[in,out] module  Pointer to the software instance struct
+ *
+ * \return The current tamper stamp value as a 32-bit unsigned integer.
+ */
+uint32_t rtc_tamper_get_stamp (struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Initialize return value. */
+	uint32_t tamper_stamp = 0;
+
+	while (rtc_count_is_syncing(module)) {
+		/* Wait for synchronization */
+	}
+
+	/* Read value based on mode. */
+	switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Return stamp value in 32-bit mode. */
+			tamper_stamp = rtc_module->MODE0.TIMESTAMP.reg;
+
+			break;
+
+		case RTC_COUNT_MODE_16BIT:
+			/* Return stamp value in 16-bit mode. */
+			tamper_stamp = (uint32_t)rtc_module->MODE1.TIMESTAMP.reg;
+
+			break;
+
+		default:
+			Assert(false);
+			break;
+	}
+
+	return tamper_stamp;
+}
+
+#endif

firmware/SendcommCmdsys/src/ASF/sam0/drivers/rtc/rtc_sam_l_c/rtc_count_interrupt.c

@@ -0,0 +1,355 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Count Interrupt Mode)
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "rtc_count_interrupt.h"
+
+extern struct rtc_module *_rtc_instance[RTC_INST_NUM];
+
+/**
+ * \brief Registers callback for the specified callback type.
+ *
+ * Associates the given callback function with the
+ * specified callback type.
+ * To enable the callback, the \ref rtc_count_enable_callback function
+ * must be used.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]  callback      Pointer to the function desired for the specified
+ *                           callback
+ * \param[in]  callback_type Callback type to register
+ *
+ * \return                        Status of registering callback.
+ * \retval STATUS_OK              Registering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to register a callback not available
+ */
+enum status_code rtc_count_register_callback(
+		struct rtc_module *const module,
+		rtc_count_callback_t callback,
+		enum rtc_count_callback callback_type)
+{
+
+	enum status_code status = STATUS_OK;
+
+	/* Overflow callback */
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+		|| callback_type == RTC_COUNT_CALLBACK_TAMPER
+#endif
+		|| (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7)) {
+		status = STATUS_OK;
+	} else {
+		/* Make sure callback type can be registered */
+		switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (callback_type > (RTC_COMP32_NUM + RTC_PER_NUM)) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+
+			break;
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (callback_type > (RTC_NUM_OF_COMP16 + RTC_PER_NUM)) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		default:
+			status = STATUS_ERR_INVALID_ARG;
+		}
+	}
+
+	if (status == STATUS_OK) {
+		/* Register callback */
+		module->callbacks[callback_type] = callback;
+		/* Set corresponding bit to set callback as registered */
+		module->registered_callback |= (1 << callback_type);
+	}
+
+	return status;
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type.
+ *
+ * When called, the currently registered callback for the given callback type
+ * will be removed.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type  Specifies the callback type to unregister
+ *
+ * \return                        Status of unregistering callback.
+ * \retval STATUS_OK              Unregistering was done successfully
+ * \retval STATUS_ERR_INVALID_ARG If trying to unregister a callback not available
+ */
+enum status_code rtc_count_unregister_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type)
+{
+	enum status_code status = STATUS_OK;
+
+	/* Overflow callback */
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+		|| callback_type == RTC_COUNT_CALLBACK_TAMPER
+#endif
+		|| (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7)) {
+		status = STATUS_OK;
+	} else {
+		/* Make sure callback type can be unregistered */
+		switch (module->mode) {
+		case RTC_COUNT_MODE_32BIT:
+			/* Check sanity for 32-bit mode. */
+			if (callback_type > (RTC_COMP32_NUM + RTC_PER_NUM)) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		case RTC_COUNT_MODE_16BIT:
+			/* Check sanity for 16-bit mode. */
+			if (callback_type > (RTC_NUM_OF_COMP16 + RTC_PER_NUM)) {
+				status = STATUS_ERR_INVALID_ARG;
+			}
+			break;
+		default:
+			status = STATUS_ERR_INVALID_ARG;
+		}
+	}
+	if (status == STATUS_OK) {
+		/* Unregister callback */
+		module->callbacks[callback_type] = NULL;
+
+		/* Clear corresponding bit to set callback as unregistered */
+		module->registered_callback &= ~(1 << callback_type);
+	}
+	return status;
+}
+
+/**
+ * \brief Enables callback.
+ *
+ * Enables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type Callback type to enable
+ */
+void rtc_count_enable_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+		rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_OVF;
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	} else if (callback_type == RTC_COUNT_CALLBACK_TAMPER) {
+		rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_TAMPER;
+#endif
+	} else if (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7) {
+		rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_PER(1 << callback_type);
+	}else {
+		rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_CMP(1 << (callback_type - RTC_PER_NUM));
+	}
+	/* Mark callback as enabled. */
+	module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback.
+ *
+ * Disables the callback specified by the callback_type.
+ *
+ * \param[in,out]  module  Pointer to the software instance struct
+ * \param[in]     callback_type Callback type to disable
+ */
+void rtc_count_disable_callback(
+		struct rtc_module *const module,
+		enum rtc_count_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Disable interrupt */
+	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
+		rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_OVF;
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	} else if (callback_type == RTC_COUNT_CALLBACK_TAMPER) {
+		rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_TAMPER;
+#endif
+	} else if(callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7){
+		rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_PER(1 << callback_type);;
+	}else {
+		rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_CMP(1 << (callback_type - RTC_PER_NUM));
+	}
+
+	/* Mark callback as disabled. */
+	module->enabled_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \internal Interrupt handler for RTC
+ *
+ * \param [in] instance_index  Default value 0
+ */
+static void _rtc_interrupt_handler(const uint32_t instance_index)
+{
+	struct rtc_module *module = _rtc_instance[instance_index];
+
+	Rtc *const rtc_module = module->hw;
+
+	/* Combine callback registered and enabled masks */
+	uint16_t callback_mask = module->enabled_callback;
+	callback_mask &= module->registered_callback;
+
+	/* Read and mask interrupt flag register */
+	uint16_t interrupt_status = rtc_module->MODE0.INTFLAG.reg;
+	interrupt_status &= rtc_module->MODE0.INTENSET.reg;
+
+	if (interrupt_status & RTC_MODE0_INTFLAG_OVF) {
+		/* Overflow interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_OVERFLOW)) {
+			module->callbacks[RTC_COUNT_CALLBACK_OVERFLOW]();
+		}
+
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+#ifdef FEATURE_RTC_TAMPER_DETECTION
+	} else if (interrupt_status & RTC_MODE0_INTFLAG_TAMPER) {
+		/* Tamper interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_TAMPER)) {
+			module->callbacks[RTC_COUNT_CALLBACK_TAMPER]();
+		}
+
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_PER(0xff)) {
+		uint8_t i  = 0;
+		for ( i = 0;i < RTC_PER_NUM;i++) {
+			if ((interrupt_status & RTC_MODE1_INTFLAG_PER(1 << i))
+			  && (callback_mask & (1 << i))) {
+				module->callbacks[i]();
+			}
+
+			/* Clear interrupt flag */
+			rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_PER(1<<i);
+		}
+	}else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 0)) {
+		/* Compare 0 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_0)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_0]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 0);
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 1)) {
+		#if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
+		/* Compare 1 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_1)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_1]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 1);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 2)) {
+		#if (RTC_NUM_OF_COMP16 > 2)	|| defined(__DOXYGEN__)
+		/* Compare 2 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_2)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_2]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 2);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 3)) {
+		#if (RTC_NUM_OF_COMP16 > 3)	|| defined(__DOXYGEN__)
+		/* Compare 3 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_3)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_3]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 3);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 4)) {
+		#if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
+		/* Compare 4 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_4)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_4]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 4);
+		#endif
+
+	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 5)) {
+		#if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
+		/* Compare 5 interrupt */
+		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_5)) {
+			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_5]();
+		}
+		/* Clear interrupt flag */
+		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 5);
+		#endif
+	}
+}
+
+/**
+ * \internal ISR handler for RTC
+ */
+#if (RTC_INST_NUM == 1)
+void RTC_Handler(void)
+{
+	_rtc_interrupt_handler(0);
+}
+#elif (RTC_INST_NUM > 1)
+#  define _RTC_INTERRUPT_HANDLER(n, unused) \
+		void RTC##n##_Handler(void) \
+		{ \
+			_rtc_interrupt_handler(n); \
+		}
+
+MREPEAT(RTC_INST_NUM, _RTC_INTERRUPT_HANDLER, ~)
+#endif /* (RTC_INST_NUM > 1) */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/rtc/rtc_tamper.h

@@ -0,0 +1,368 @@
+/**
+ * \file
+ *
+ * \brief SAM RTC Driver (Tamper)
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef RTC_TAMPER_H_INCLUDED
+#define RTC_TAMPER_H_INCLUDED
+
+/**
+ *
+ * \section asfdoc_sam0_rtc_tamper_detect RTC Tamper Detect
+ * The RTC provides several selectable polarity external inputs (INn) that can be
+ * used for tamper detection. When detect, tamper inputs support the four actions:
+ *   - Off
+ *   - Wake
+ *   - Capture
+ *   - Active layer protection
+ *
+ * \note The Active Layer Protection is a means of detecting broken traces on the
+ * PCB provided by RTC. In this mode an RTC output signal is routed over critical
+ * components on the board and fed back to one of the RTC inputs. The input and
+ * output signals are compared and a tamper condition is detected when they do not match.
+ *
+ *
+ * Separate debouncers are embedded for each external input. The detection time 
+ * depends on whether the debouncer operates synchronously or asynchronously, 
+ * and whether majority detection is enabled or not. For details, refer to the section
+ * "Tamper Detection" of datasheet.
+ * \if RTC_COUNT_CALLBACK_MODE
+ *  \addtogroup asfdoc_sam0_rtc_count_group
+ * \else
+ * \if RTC_CALENDAR_CALLBACK_MODE
+ *  \addtogroup asfdoc_sam0_rtc_calendar_group
+ * \endif
+ * \endif
+ * @{
+ */
+
+#if defined(FEATURE_RTC_TAMPER_DETECTION) || defined(__DOXYGEN__)
+
+/** RTC tamper ID0 detection bitmask. */
+#define RTC_TAMPER_DETECT_ID0    (1UL << 0)
+/** RTC tamper ID1 detection bitmask. */
+#define RTC_TAMPER_DETECT_ID1    (1UL << 1)
+/** RTC tamper ID2 detection bitmask. */
+#define RTC_TAMPER_DETECT_ID2    (1UL << 2)
+/** RTC tamper ID3 detection bitmask. */
+#define RTC_TAMPER_DETECT_ID3    (1UL << 3)
+/** RTC tamper ID4 detection bitmask. */
+#define RTC_TAMPER_DETECT_ID4    (1UL << 4)
+/** RTC tamper input event detection bitmask. */
+#define RTC_TAMPER_DETECT_EVT    (1UL << 5)
+
+
+
+/**
+ * \brief RTC tamper active layer frequency divider.
+ *
+ * The available prescaler factor for the RTC clock output used during active
+ * layer protection.
+ */
+enum rtc_tamper_active_layer_freq_divider {
+	/** RTC active layer frequency is prescaled by a factor of 2 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_2    = RTC_MODE0_CTRLB_ACTF_DIV2,
+	/** RTC active layer frequency is prescaled by a factor of 4 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_4    = RTC_MODE0_CTRLB_ACTF_DIV4,
+	/** RTC active layer frequency is prescaled by a factor of 8 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_8    = RTC_MODE0_CTRLB_ACTF_DIV8,
+	/** RTC active layer frequency is prescaled by a factor of 16 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_16   = RTC_MODE0_CTRLB_ACTF_DIV16,
+	/** RTC active layer frequency is prescaled by a factor of 32 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_32   = RTC_MODE0_CTRLB_ACTF_DIV32,
+	/** RTC active layer frequency is prescaled by a factor of 64 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_64   = RTC_MODE0_CTRLB_ACTF_DIV64,
+	/** RTC active layer frequency is prescaled by a factor of 128 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_128  = RTC_MODE0_CTRLB_ACTF_DIV128,
+	/** RTC active layer frequency is prescaled by a factor of 256 */
+	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_256  = RTC_MODE0_CTRLB_ACTF_DIV256,
+};
+
+/**
+ * \brief RTC tamper debounce frequency divider.
+ *
+ * The available prescaler factor for the input debouncers.
+ */
+enum rtc_tamper_debounce_freq_divider {
+	/** RTC debounce frequency is prescaled by a factor of 2 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_2    = RTC_MODE0_CTRLB_DEBF_DIV2,
+	/** RTC debounce frequency is prescaled by a factor of 4 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_4    = RTC_MODE0_CTRLB_DEBF_DIV4,
+	/** RTC debounce frequency is prescaled by a factor of 8 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_8    = RTC_MODE0_CTRLB_DEBF_DIV8,
+	/** RTC debounce frequency is prescaled by a factor of 16 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_16   = RTC_MODE0_CTRLB_DEBF_DIV16,
+	/** RTC debounce frequency is prescaled by a factor of 32 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_32   = RTC_MODE0_CTRLB_DEBF_DIV32,
+	/** RTC debounce frequency is prescaled by a factor of 64 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_64   = RTC_MODE0_CTRLB_DEBF_DIV64,
+	/** RTC debounce frequency is prescaled by a factor of 128 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_128  = RTC_MODE0_CTRLB_DEBF_DIV128,
+	/** RTC debounce frequency is prescaled by a factor of 256 */
+	RTC_TAMPER_DEBOUNCE_FREQ_DIV_256  = RTC_MODE0_CTRLB_DEBF_DIV256,
+};
+
+/**
+ * \brief RTC tamper input action.
+ *
+ * The available action taken by the tamper input.
+ */
+enum rtc_tamper_input_action {
+	/** RTC tamper input action is disabled */
+	RTC_TAMPER_INPUT_ACTION_OFF     = RTC_TAMPCTRL_IN0ACT_OFF,
+	/** RTC tamper input action is wake and set tamper flag */
+	RTC_TAMPER_INPUT_ACTION_WAKE    = RTC_TAMPCTRL_IN0ACT_WAKE,
+	/** RTC tamper input action is capture timestamp and set tamper flag */
+	RTC_TAMPER_INPUT_ACTION_CAPTURE = RTC_TAMPCTRL_IN0ACT_CAPTURE,
+	/** RTC tamper input action is compare IN to OUT, when a mismatch occurs,
+	 *  capture timestamp and set tamper flag */
+	RTC_TAMPER_INPUT_ACTION_ACTL    = RTC_TAMPCTRL_IN0ACT_ACTL,
+};
+
+/**
+ * \brief RTC tamper input level select.
+ *
+ * The available edge condition for tamper INn level select.
+ */
+enum rtc_tamper_level_sel {
+	/** A falling edge condition will be detected on Tamper input */
+	RTC_TAMPER_LEVEL_FALLING = (0),
+	/** A rising edge condition will be detected on Tamper input */
+	RTC_TAMPER_LEVEL_RISING  = (1),
+};
+
+/**
+ * \brief RTC tamper debounce sequential.
+ *
+ * The available sequential for tamper debounce.
+ */
+enum rtc_tamper_debounce_seq {
+	/** Tamper input detect edge with synchronous stability debounce */
+	RTC_TAMPER_DEBOUNCE_SYNC,
+	/** Tamper input detect edge with asynchronous stability debounce */
+	RTC_TAMPER_DEBOUNCE_ASYNC,
+	/** Tamper input detect edge with majority debounce */
+	RTC_TAMPER_DEBOUNCE_MAJORITY,
+};
+
+/**
+ * \brief RTC tamper input configuration structure.
+ *
+ * The configuration structure for tamper INn.
+ */
+struct rtc_tamper_input_config {
+	/** Debounce enable */
+	bool debounce_enable;
+	/** Tamper level select */
+	enum rtc_tamper_level_sel level;
+	/** Tamper input action */
+	enum rtc_tamper_input_action action;
+};
+
+/**
+ * \brief RTC Tamper configuration structure.
+ *
+ * The configuration structure for the RTC tamper. This structure should
+ * be initialized using the \ref rtc_tamper_get_config_defaults() before any
+ * user configurations are set.
+ */
+struct rtc_tamper_config {
+	/** Backup register reset on tamper enable */
+	bool bkup_reset_on_tamper;
+	/** GP register reset on tamper enable */
+	bool gp_reset_on_tamper;
+	/** Active layer frequency */
+	enum rtc_tamper_active_layer_freq_divider actl_freq_div;
+	/** Debounce frequency */
+	enum rtc_tamper_debounce_freq_divider deb_freq_div;
+	/** Debounce sequential */
+	enum rtc_tamper_debounce_seq deb_seq;
+	/** DMA on tamper enable */
+	bool dma_tamper_enable;
+	/** General Purpose 0/1 Enable */
+	bool gp0_enable;
+	/** Tamper IN configuration */
+	struct rtc_tamper_input_config in_cfg[RTC_TAMPER_NUM];
+};
+
+/**
+ * \name RTC Tamper Detection
+ * @{
+ */
+
+/**
+ *  \brief Gets the RTC tamper default configurations.
+ *
+ *  Initializes the configuration structure to default values. 
+ *
+ *  The default configuration is as follows:
+ *  - Disable backup register reset on tamper
+ *  - Disable GP register reset on tamper
+ *  - Active layer clock divided by a factor of 8
+ *  - Debounce clock divided by a factor of 8
+ *  - Detect edge on INn with synchronous stability debouncing
+ *  - Disable DMA on  tamper
+ *  - Enable GP register
+ *  - Disable debouce, detect on falling edge and no action on INn
+ *
+ *  \param[out] config Configuration structure to be initialized to default values.
+ */
+static inline void rtc_tamper_get_config_defaults(
+		struct rtc_tamper_config *const config)
+{
+	/* Sanity check argument */
+	Assert(config);
+
+	config->bkup_reset_on_tamper= false;
+	config->gp_reset_on_tamper  = false;
+	config->actl_freq_div       = RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_8;
+	config->deb_freq_div        = RTC_TAMPER_DEBOUNCE_FREQ_DIV_8;
+	config->deb_seq             = RTC_TAMPER_DEBOUNCE_SYNC;
+	config->dma_tamper_enable   = false;
+	config->gp0_enable          = true;
+
+	for (uint8_t id = 0; id < RTC_TAMPER_NUM; id++) {
+		config->in_cfg[id].debounce_enable = false;
+		config->in_cfg[id].level = RTC_TAMPER_LEVEL_FALLING;
+		config->in_cfg[id].action = RTC_TAMPER_INPUT_ACTION_OFF;
+	}
+}
+enum status_code rtc_tamper_set_config (struct rtc_module *const module,
+		struct rtc_tamper_config *const tamper_cfg);
+
+/**
+ * \brief Retrieves the RTC tamper detection status.
+ *
+ * Retrieves the detection status of each input pin and the input event.
+ *
+ * \param[in] module  Pointer to the RTC software instance struct
+ *
+ * \return Bitmask of detection flags.
+ *
+ * \retval RTC_TAMPER_DETECT_ID0   Tamper condition on IN0 has been detected
+ * \retval RTC_TAMPER_DETECT_ID1   Tamper condition on IN1 has been detected
+ * \retval RTC_TAMPER_DETECT_ID2   Tamper condition on IN2 has been detected
+ * \retval RTC_TAMPER_DETECT_ID3   Tamper condition on IN3 has been detected
+ * \retval RTC_TAMPER_DETECT_ID4   Tamper condition on IN4 has been detected
+ * \retval RTC_TAMPER_DETECT_EVT   Tamper input event has been detected
+ */
+static inline uint32_t rtc_tamper_get_detect_flag (struct rtc_module *const module)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	uint32_t tamper_id = module->hw->MODE0.TAMPID.reg;
+	uint32_t detect_flags = 0;
+
+	if (tamper_id & RTC_TAMPID_TAMPID0) {
+		detect_flags |= RTC_TAMPER_DETECT_ID0;
+	}
+
+	if (tamper_id & RTC_TAMPID_TAMPID1) {
+		detect_flags |= RTC_TAMPER_DETECT_ID1;
+	}
+
+	if (tamper_id & RTC_TAMPID_TAMPID2) {
+		detect_flags |= RTC_TAMPER_DETECT_ID2;
+	}
+
+	if (tamper_id & RTC_TAMPID_TAMPID3) {
+		detect_flags |= RTC_TAMPER_DETECT_ID3;
+	}
+
+	if (tamper_id & RTC_TAMPID_TAMPID4) {
+		detect_flags |= RTC_TAMPER_DETECT_ID4;
+	}
+
+	if (tamper_id & RTC_TAMPID_TAMPEVT) {
+		detect_flags |= RTC_TAMPER_DETECT_EVT;
+	}
+
+	return detect_flags;
+}
+
+/**
+ * \brief Clears RTC tamper detection flag.
+ *
+ * Clears the given detection flag of the module.
+ *
+ * \param[in] module   Pointer to the TC software instance struct
+ * \param[in] detect_flags  Bitmask of detection flags
+ */
+static inline void rtc_tamper_clear_detect_flag(
+		struct rtc_module *const module,
+		const uint32_t detect_flags)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	uint32_t tamper_id = 0;
+
+	if (detect_flags & RTC_TAMPER_DETECT_ID0) {
+		tamper_id |= RTC_TAMPID_TAMPID0;
+	}
+
+	if (detect_flags & RTC_TAMPER_DETECT_ID1) {
+		tamper_id |= RTC_TAMPID_TAMPID1;
+	}
+
+	if (detect_flags & RTC_TAMPER_DETECT_ID2) {
+		tamper_id |= RTC_TAMPID_TAMPID2;
+	}
+
+	if (detect_flags & RTC_TAMPER_DETECT_ID3) {
+		tamper_id |= RTC_TAMPID_TAMPID3;
+	}
+
+	if (detect_flags & RTC_TAMPER_DETECT_ID4) {
+		tamper_id |= RTC_TAMPID_TAMPID4;
+	}
+
+	if (detect_flags & RTC_TAMPER_DETECT_EVT) {
+		tamper_id |= RTC_TAMPID_TAMPEVT;
+	}
+
+	module->hw->MODE0.TAMPID.reg = tamper_id;
+
+}
+
+/** @} */
+
+#endif
+/** @} */
+
+
+#endif /* RTC_TAMPER_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/i2c/i2c_common.h

@@ -0,0 +1,607 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Common Driver
+ *
+ * Copyright (c) 2012-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef I2C_COMMON_H_INCLUDED
+#define I2C_COMMON_H_INCLUDED
+
+#include <compiler.h>
+#include <sercom.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \if (I2C_MASTER_MODE && I2C_SLAVE_MODE)
+ *   \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C (SERCOM I2C) Driver
+ * \elseif I2C_MASTER_MODE
+ *   \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Master Mode (SERCOM I2C) Driver
+ * \elseif I2C_SLAVE_MODE
+ *   \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Slave Mode (SERCOM I2C) Driver
+ * \endif
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's SERCOM
+ * I<SUP>2</SUP>C module, for the transfer of data via an I<SUP>2</SUP>C bus.
+ * The following driver API modes are covered by this manual:
+ *
+ * \if I2C_MASTER_MODE
+ * - Master Mode Polled APIs
+ * \endif
+ * \if I2C_MASTER_CALLBACK_MODE
+ * - Master Mode Callback APIs
+ * \endif
+ * \if I2C_SLAVE_MODE
+ * - Slave Mode Polled APIs
+ * \endif
+ * \if I2C_SLAVE_CALLBACK_MODE
+ * - Slave Mode Callback APIs
+ * \endif
+ *
+ * The following peripheral is used by this module:
+ * - SERCOM (Serial Communication Interface)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34
+ *  - Atmel | SMART SAM R35
+ *
+ * The outline of this documentation is as follows:
+ * - \ref asfdoc_sam0_sercom_i2c_prerequisites
+ * - \ref asfdoc_sam0_sercom_i2c_overview
+ * - \ref asfdoc_sam0_sercom_i2c_special_considerations
+ * - \ref asfdoc_sam0_sercom_i2c_extra
+ * - \ref asfdoc_sam0_sercom_i2c_examples
+ * - \ref asfdoc_sam0_sercom_i2c_api_overview
+ *
+ * \section asfdoc_sam0_sercom_i2c_prerequisites Prerequisites
+ * There are no prerequisites.
+ *
+ * \section asfdoc_sam0_sercom_i2c_overview Module Overview
+ * The outline of this section is as follows:
+ * - \ref asfdoc_sam0_sercom_i2c_module_features
+ * - \ref asfdoc_sam0_sercom_i2c_functional_desc
+ * - \ref asfdoc_sam0_sercom_i2c_bus_topology
+ * - \ref asfdoc_sam0_sercom_i2c_transactions
+ * - \ref asfdoc_sam0_sercom_i2c_multi_master
+ * - \ref asfdoc_sam0_sercom_i2c_bus_states
+ * - \ref asfdoc_sam0_sercom_i2c_timeout
+ * - \ref asfdoc_sam0_sercom_i2c_sleep_modes
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_module_features Driver Feature Macro Definition
+ * <table>
+ *	<tr>
+ *		<th>Driver Feature Macro</th>
+ *		<th>Supported devices</th>
+ *	</tr>
+ *	<tr>
+ *		<td>FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED</td>
+ *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1/R34/R35</td>
+ *	</tr>
+ *	<tr>
+ *		<td>FEATURE_I2C_10_BIT_ADDRESS</td>
+ *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1/R34/R35</td>
+ *	</tr>
+ *	<tr>
+ *		<td>FEATURE_I2C_SCL_STRETCH_MODE</td>
+ *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1/R34/R35</td>
+ *	</tr>
+ *	<tr>
+ *		<td>FEATURE_I2C_SCL_EXTEND_TIMEOUT</td>
+ *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1/R34/R35</td>
+ *	</tr>
+ * </table>
+ * \note The specific features are only available in the driver when the selected
+ * device supports those features.
+ * \note When using the I2C high-speed mode for off-board communication,
+ * there are various high frequency interference, which can lead to distortion of the signals
+ * and communication failure. When using Xplained Pro boards in order to test I2C high-speed
+ * communication, the following recommendation should be followed:
+ * - Use the SDA-line on PA08 and SCL-line on PA09 for both boards. This will provide stronger
+ * pull-ups on both SDA and SCL.
+ * - The SCL should not be higher than 1.5MHz.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_functional_desc Functional Description
+ * The I<SUP>2</SUP>C provides a simple two-wire bidirectional bus consisting of a
+ * wired-AND type serial clock line (SCL) and a wired-AND type serial data line
+ * (SDA).
+ *
+ * The I<SUP>2</SUP>C bus provides a simple, but efficient method of interconnecting
+ * multiple master and slave devices. An arbitration mechanism is provided for
+ * resolving bus ownership between masters, as only one master device may own
+ * the bus at any given time. The arbitration mechanism relies on the wired-AND
+ * connections to avoid bus drivers short-circuiting.
+ *
+ * A unique address is assigned to all slave devices connected to the bus. A
+ * device can contain both master and slave logic, and can emulate multiple
+ * slave devices by responding to more than one address.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_bus_topology Bus Topology
+ * The I<SUP>2</SUP>C bus topology is illustrated in
+ * \ref asfdoc_sam0_sercom_i2c_bus_topology_figure "the figure below". The pull-up
+ * resistors (Rs) will provide a high level on the bus lines when none of the
+ * I<SUP>2</SUP>C devices are driving the bus. These are optional, and can be
+ * replaced with a constant current source.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_bus_topology_figure
+ * \image html bus_topology.svg "I2C Bus Topology" Width=100%
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_transactions Transactions
+ * The I<SUP>2</SUP>C standard defines three fundamental transaction formats:
+ * - Master Write
+ *   - The master transmits data packets to the slave after addressing it
+ * - Master Read
+ *   - The slave transmits data packets to the master after being addressed
+ * - Combined Read/Write
+ *   - A combined transaction consists of several write and read transactions
+ *
+ * A data transfer starts with the master issuing a \b Start condition on the
+ * bus, followed by the address of the slave together with a bit to indicate
+ * whether the master wants to read from or write to the slave.
+ * The addressed slave must respond to this by sending an \b ACK back to the
+ * master.
+ *
+ * After this, data packets are sent from the master or slave, according to the
+ * read/write bit. Each packet must be acknowledged (ACK) or not
+ * acknowledged (NACK) by the receiver.
+ *
+ * If a slave responds with a NACK, the master must assume that the slave
+ * cannot receive any more data and cancel the write operation.
+ *
+ * The master completes a transaction by issuing a \b Stop condition.
+ *
+ * A master can issue multiple \b Start conditions during a transaction; this
+ * is then called a \b Repeated \b Start condition.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_address_packets Address Packets
+ * The slave address consists of seven bits. The 8<SUP>th</SUP> bit in the transfer
+ * determines the data direction (read or write). An address packet always
+ * succeeds a \b Start or \b Repeated \b Start condition. The 8<SUP>th</SUP> bit is handled
+ * in the driver, and the user will only have to provide the 7-bit address.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_data_packets Data Packets
+ * Data packets are nine bits long, consisting of one 8-bit data byte, and an
+ * acknowledgement bit. Data packets follow either an address packet or another
+ * data packet on the bus.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_trans_examples Transaction Examples
+ * The gray bits in the following examples are sent from master to slave, and
+ * the white bits are sent from slave to master.
+ * Example of a read transaction is shown in
+ * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_read "the figure below". Here, the
+ * master first issues a \b Start condition and gets ownership of the bus. An
+ * address packet with the direction flag set to read is then sent and
+ * acknowledged by the slave. Then the slave sends one data packet which is
+ * acknowledged by the master. The slave sends another packet, which is not
+ * acknowledged by the master and indicates that the master will terminate the
+ * transaction. In the end, the transaction is terminated by the master issuing
+ * a \b Stop condition.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_read
+ * \image html i2c_read.svg "I2C Packet Read" Width=100%
+ *
+ * Example of a write transaction is shown in
+ * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_write "the figure below". Here, the
+ * master first issues a \b Start condition and gets ownership of the bus. An
+ * address packet with the dir flag set to write is then sent and acknowledged
+ * by the slave. Then the master sends two data packets, each acknowledged by
+ * the slave. In the end, the transaction is terminated by the master issuing
+ * a \b Stop condition.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_write
+ * \image html i2c_write.svg "I2C Packet Write" Width=100%
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_packet_timeout Packet Timeout
+ * When a master sends an I<SUP>2</SUP>C packet, there is no way of
+ * being sure that a slave will acknowledge the packet. To avoid stalling the
+ * device forever while waiting for an acknowledge, a user selectable timeout
+ * is provided in the \ref i2c_master_config struct which
+ * lets the driver exit a read or write operation after the specified time.
+ * The function will then return the STATUS_ERR_TIMEOUT flag.
+ *
+ * This is also the case for the slave when using the functions postfixed
+ * \c _wait.
+ *
+ * The time before the timeout occurs, will be the same as
+ * for \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "unknown bus state" timeout.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_repeated_start Repeated Start
+ * To issue a \b Repeated \b Start, the functions postfixed \c _no_stop must be
+ * used.
+ * These functions will not send a \b Stop condition when the transfer is done,
+ * thus the next transfer will start with a \b Repeated \b Start. To end the
+ * transaction, the functions without the \c _no_stop postfix must be used
+ * for the last read/write.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_multi_master Multi Master
+ * In a multi master environment, arbitration of the bus is important, as only
+ * one master can own the bus at any point.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_arbitration Arbitration
+ *
+ * \par Clock stretching
+ * The serial clock line is always driven by a master device. However, all
+ * devices connected to the bus are allowed stretch the low period of the clock
+ * to slow down the overall clock frequency or to insert wait states while
+ * processing data.
+ * Both master and slave can randomly stretch the clock, which will force the
+ * other device into a wait-state until the clock line goes high again.
+ *
+ * \par Arbitration on the data line
+ * If two masters start transmitting at the same time, they will both transmit
+ * until one master detects that the other master is pulling the data line low.
+ * When this is detected, the master not pulling the line low, will stop the
+ * transmission and wait until the bus is idle.
+ * As it is the master trying to contact the slave with the lowest address that
+ * will get the bus ownership, this will create an arbitration scheme always
+ * prioritizing the slaves with the lowest address in case of a bus collision.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_clock_sync Clock Synchronization
+ * In situations where more than one master is trying to control the bus clock
+ * line at the same time, a clock synchronization algorithm based on the same
+ * principles used for clock stretching is necessary.
+ *
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_bus_states Bus States
+ * As the I<SUP>2</SUP>C bus is limited to one transaction at the time,
+ * a master that wants to perform a bus transaction must wait until the bus is
+ * free.
+ * Because of this, it is necessary for all masters in a multi-master system to
+ * know the current status of the bus to be able to avoid conflicts and to
+ * ensure data integrity.
+ * \li \b IDLE No activity on the bus (between a \b Stop and a new \b Start
+ * condition)
+ * \li \b OWNER If the master initiates a transaction successfully
+ * \li \b BUSY If another master is driving the bus
+ * \li \b UNKNOWN If the master has recently been enabled or connected to
+ * the bus. Is forced to \b IDLE after given
+ * \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" when
+ * the master module is enabled
+ *
+ * The bus state diagram can be seen in
+ * \ref asfdoc_sam0_sercom_i2c_bus_states_figure "the figure below".
+ * \li S: Start condition
+ * \li P: Stop condition
+ * \li Sr: Repeated start condition
+ * \anchor asfdoc_sam0_sercom_i2c_bus_states_figure
+ * \image html bus_state_diagram.svg "I2C Bus State Diagram" Width=100%
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_timeout Bus Timing
+ * Inactive bus timeout for the master and SDA hold time is configurable in the
+ * drivers.
+ *
+ * \subsubsection asfdoc_sam0_sercom_i2c_unknown_bus_timeout Unknown Bus State Timeout
+ * When a master is enabled or connected to the bus, the bus state will be
+ * unknown until either a given timeout or a stop command has occurred. The
+ * timeout is configurable in the \ref i2c_master_config struct.
+ * The timeout time will depend on toolchain and optimization level used, as
+ * the timeout is a loop incrementing a value until it reaches the specified
+ * timeout value.
+ *
+ * \subsubsection sda_hold SDA Hold Timeout
+ * When using the I<SUP>2</SUP>C in slave mode, it will be important to
+ * set a SDA hold time which assures that the master will be able to pick up
+ * the bit sent from the slave. The SDA hold time makes sure that this is the
+ * case by holding the data line low for a given period after the negative edge
+ * on the clock.
+ *
+ * The SDA hold time is also available for the master driver, but is not a
+ * necessity.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_sleep_modes Operation in Sleep Modes
+ * The I<SUP>2</SUP>C module can operate in all sleep modes by setting
+ * the run_in_standby Boolean in the \ref i2c_master_config or
+ * \ref i2c_slave_config struct.
+ * The operation in slave and master mode is shown in
+ * \ref asfdoc_sam0_sercom_i2c_sleep_modes_table "the table below".
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_sleep_modes_table
+ * <table>
+ *   <caption>I2C Standby Operations</caption>
+ *   <tr>
+ *      <th>Run in standby</th>
+ *      <th>Slave</th>
+ *      <th>Master</th>
+ *   </tr>
+ *   <tr>
+ *      <td>false</td>
+ *      <td>Disabled, all reception is dropped</td>
+ *      <td>Generic Clock (GCLK) disabled when master is idle</td>
+ *   </tr>
+ *   <tr>
+ *      <td>true</td>
+ *      <td>Wake on address match when enabled</td>
+ *      <td>GCLK enabled while in sleep modes</td>
+ *   </tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_sercom_i2c_special_considerations Special Considerations
+ *
+ * \if (I2C_MASTER_CALLBACK_MODE || I2C_SLAVE_CALLBACK_MODE)
+ *   \subsection asfdoc_sam0_sercom_i2c_common_interrupt Interrupt-driven Operation
+ *   While an interrupt-driven operation is in progress, subsequent calls to a
+ *   write or read operation will return the STATUS_BUSY flag, indicating that
+ *   only one operation is allowed at any given time.
+ *
+ *   To check if another transmission can be initiated, the user can either call
+ *   another transfer operation, or use the
+ *   \ref i2c_master_get_job_status/\ref i2c_slave_get_job_status functions
+ *   depending on mode.
+ *
+ *   If the user would like to get callback from operations while using the
+ *   interrupt-driven driver, the callback must be registered and then enabled
+ *   using the "register_callback" and "enable_callback" functions.
+ * \else
+ *   There are no special considerations for this driver for the APIs listed in
+ *   this document.
+ * \endif
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra Extra Information
+ * For extra information, see \ref asfdoc_sam0_sercom_i2c_extra_info_page.
+ * This includes:
+ *  - \ref asfdoc_sam0_sercom_i2c_acronyms
+ *  - \ref asfdoc_sam0_sercom_i2c_extra_dependencies
+ *  - \ref asfdoc_sam0_sercom_i2c_extra_errata
+ *  - \ref asfdoc_sam0_sercom_i2c_extra_history
+ *
+ * \section asfdoc_sam0_sercom_i2c_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_sercom_i2c_exqsg.
+ *
+ * \section asfdoc_sam0_sercom_i2c_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \name Driver Feature Definition
+ * Define SERCOM I<SUP>2</SUP>C driver features set according to different device family.
+ *
+ * @{
+ */
+#if (SAMD21) || (SAMR21) || (SAMD10) || (SAMD11) || (SAML21) || (SAMDA1) || \
+	(SAMHA1) || (SAMHA0) || (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089) || defined(__DOXYGEN__)
+/** Fast mode plus and high speed support. */
+#  define FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+/** 10-bit address support */
+#  define FEATURE_I2C_10_BIT_ADDRESS
+/** SCL stretch mode support */
+#  define FEATURE_I2C_SCL_STRETCH_MODE
+/** SCL extend timeout support */
+#  define FEATURE_I2C_SCL_EXTEND_TIMEOUT
+#  define FEATURE_I2C_DMA_SUPPORT
+#endif
+/*@}*/
+
+/** \brief Transfer direction
+ *
+ * For master: transfer direction or setting direction bit in address.
+ * For slave: direction of request from master.
+ */
+enum i2c_transfer_direction {
+	/** Master write operation is in progress */
+	I2C_TRANSFER_WRITE = 0,
+	/** Master read operation is in progress */
+	I2C_TRANSFER_READ  = 1,
+};
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * \page asfdoc_sam0_sercom_i2c_extra_info_page  Extra Information for SERCOM I2C Driver
+ *
+ * \section asfdoc_sam0_sercom_i2c_acronyms Acronyms
+ * \ref asfdoc_sam0_sercom_i2c_acronyms_table "Below" is a table listing the acronyms
+ * used in this module, along with their intended meanings.
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_acronyms_table
+ * <table>
+ *  <caption>Acronyms</caption>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>SDA</td>
+ *		<td>Serial Data Line</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SCL</td>
+ *		<td>Serial Clock Line</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SERCOM</td>
+ *		<td>Serial Communication Interface</td>
+ *	</tr>
+ *	<tr>
+ *		<td>DMA</td>
+ *		<td>Direct Memory Access</td>
+ *	</tr>
+ * </table>
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra_dependencies Dependencies
+ * The I<SUP>2</SUP>C driver has the following dependencies:
+ * \li \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
+ *
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ * \section asfdoc_sam0_sercom_i2c_extra_history Module History
+ * \ref asfdoc_sam0_sercom_i2c_extra_history_table "Below" is an overview of the
+ * module history, detailing enhancements and fixes made to the module since
+ * its first release. The current version of this corresponds to the newest
+ * version listed in
+ * \ref asfdoc_sam0_sercom_i2c_extra_history_table "the table below".
+ *
+ * \anchor asfdoc_sam0_sercom_i2c_extra_history_table
+ * <table>
+ *  <caption>Module History</caption>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *		\li Added 10-bit addressing and high speed support in SAM D21
+ *		\li Separate structure i2c_packet into i2c_master_packet and i2c_slave packet
+ *		</td>
+ *	</tr>
+ *	<tr>
+ *		<td>
+ *		\li Added support for SCL stretch and extended timeout hardware features in SAM D21
+ *		\li Added fast mode plus support in SAM D21
+ *		</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Fixed incorrect logical mask for determining if a bus error has
+ *          occurred in I<SUP>2</SUP>C Slave mode
+ *      </td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_i2c_exqsg Examples for SERCOM I2C Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_sercom_i2c_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ * \if I2C_MASTER_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_master_basic_use_case "Quick Start Guide for the I2C Master module - Basic Use Case"
+ * \endif
+ * \if I2C_MASTER_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_master_callback_use_case "Quick Start Guide for the I2C Master module - Callback Use Case"
+ * - \subpage asfdoc_sam0_sercom_i2c_master_dma_use_case "Quick Start Guide for the I2C Master module - DMA Use Case"
+ * \endif
+ * \if I2C_SLAVE_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_slave_basic_use_case "Quick Start Guide for the I2C Slave module - Basic Use Case"
+ * \endif
+ * \if I2C_SLAVE_CALLBACK_MODE
+ * - \subpage asfdoc_sam0_sercom_i2c_slave_callback_use_case "Quick Start Guide for the I2C Slave module - Callback Use Case"
+ * - \subpage asfdoc_sam0_sercom_i2c_slave_dma_use_case "Quick Start Guide for the I2C Slave module - DMA Use Case"
+ * \endif
+ *
+ * \page asfdoc_sam0_sercom_i2c_document_revision_history Document Revision History
+ *
+ * \if (I2C_MASTER_MODE || I2C_MASTER_CALLBACK_MODE)
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42117E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42117D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for 10-bit addressing and high speed in SAM D21.
+ *		    Added support for SAM R21 and SAM D10/D11.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42117C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42117B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42117A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ * \else
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42116E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42116D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for 10-bit addressing and high speed in SAM D21.
+ *		    Added support for SAM R21 and SAM D10/D11.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42116C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42116B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42116A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ *\endif
+ */
+
+#endif /* I2C_COMMON_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/i2c/i2c_master.h

@@ -0,0 +1,619 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Master Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef I2C_MASTER_H_INCLUDED
+#define I2C_MASTER_H_INCLUDED
+
+#include "i2c_common.h"
+#include <sercom.h>
+#include <pinmux.h>
+
+#if I2C_MASTER_CALLBACK_MODE == true
+#  include <sercom_interrupt.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef PINMUX_DEFAULT
+#  define PINMUX_DEFAULT 0
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_i2c_group
+ *
+ * @{
+ */
+
+/**
+ * \brief I<SUP>2</SUP>C master packet for read/write
+ *
+ * Structure to be used when transferring I<SUP>2</SUP>C master packets.
+ */
+struct i2c_master_packet {
+	/** Address to slave device  */
+	uint16_t address;
+	/** Length of data array */
+	uint16_t data_length;
+	/** Data array containing all data to be transferred */
+	uint8_t *data;
+	/** Use 10-bit addressing. Set to false if the feature is not supported by the device  */
+	bool ten_bit_address;
+	/** Use high speed transfer. Set to false if the feature is not supported by the device */
+	bool high_speed;
+	/** High speed mode master code (0000 1XXX), valid when high_speed is true */
+	uint8_t hs_master_code;
+};
+
+/** \brief Interrupt flags
+ *
+ * Flags used when reading or setting interrupt flags.
+ */
+enum i2c_master_interrupt_flag {
+	/** Interrupt flag used for write */
+	I2C_MASTER_INTERRUPT_WRITE = 0,
+	/** Interrupt flag used for read */
+	I2C_MASTER_INTERRUPT_READ  = 1,
+};
+
+/**
+ * \brief Values for hold time after start bit.
+ *
+ * Values for the possible I<SUP>2</SUP>C master mode SDA internal hold times after start
+ * bit has been sent.
+ */
+enum i2c_master_start_hold_time {
+	/** Internal SDA hold time disabled */
+	I2C_MASTER_START_HOLD_TIME_DISABLED = SERCOM_I2CM_CTRLA_SDAHOLD(0),
+	/** Internal SDA hold time 50ns - 100ns */
+	I2C_MASTER_START_HOLD_TIME_50NS_100NS = SERCOM_I2CM_CTRLA_SDAHOLD(1),
+	/** Internal SDA hold time 300ns - 600ns */
+	I2C_MASTER_START_HOLD_TIME_300NS_600NS = SERCOM_I2CM_CTRLA_SDAHOLD(2),
+	/** Internal SDA hold time 400ns - 800ns */
+	I2C_MASTER_START_HOLD_TIME_400NS_800NS = SERCOM_I2CM_CTRLA_SDAHOLD(3),
+};
+
+/**
+ * \brief Values for inactive bus time-out.
+ *
+ * If the inactive bus time-out is enabled and the bus is inactive for
+ * longer than the time-out setting, the bus state logic will be set to idle.
+ */
+enum i2c_master_inactive_timeout {
+	/** Inactive bus time-out disabled */
+	I2C_MASTER_INACTIVE_TIMEOUT_DISABLED = SERCOM_I2CM_CTRLA_INACTOUT(0),
+	/** Inactive bus time-out 5-6 SCL cycle time-out */
+	I2C_MASTER_INACTIVE_TIMEOUT_55US = SERCOM_I2CM_CTRLA_INACTOUT(1),
+	/** Inactive bus time-out 10-11 SCL cycle time-out */
+	I2C_MASTER_INACTIVE_TIMEOUT_105US = SERCOM_I2CM_CTRLA_INACTOUT(2),
+	/** Inactive bus time-out 20-21 SCL cycle time-out */
+	I2C_MASTER_INACTIVE_TIMEOUT_205US = SERCOM_I2CM_CTRLA_INACTOUT(3),
+};
+
+/**
+ * \brief I<SUP>2</SUP>C frequencies
+ *
+ * Values for I<SUP>2</SUP>C speeds supported by the module. The driver
+ * will also support setting any other value, in which case set
+ * the value in the \ref i2c_master_config at desired value divided by 1000.
+ *
+ * Example: If 10KHz operation is required, give baud_rate in the configuration
+ * structure the value 10.
+ */
+enum i2c_master_baud_rate {
+	/** Baud rate at 100KHz (Standard-mode) */
+	I2C_MASTER_BAUD_RATE_100KHZ = 100,
+	/** Baud rate at 400KHz (Fast-mode) */
+	I2C_MASTER_BAUD_RATE_400KHZ = 400,
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+	/** Baud rate at 1MHz (Fast-mode Plus) */
+	I2C_MASTER_BAUD_RATE_1000KHZ = 1000,
+	/** Baud rate at 3.4MHz (High-speed mode) */
+	I2C_MASTER_BAUD_RATE_3400KHZ = 3400,
+#endif
+};
+
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+/**
+ * \brief Enum for the transfer speed
+ *
+ * Enum for the transfer speed.
+ */
+enum i2c_master_transfer_speed {
+	/** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz */
+	I2C_MASTER_SPEED_STANDARD_AND_FAST = SERCOM_I2CM_CTRLA_SPEED(0),
+	/** Fast-mode Plus (Fm+) up to 1MHz */
+	I2C_MASTER_SPEED_FAST_MODE_PLUS = SERCOM_I2CM_CTRLA_SPEED(1),
+	/** High-speed mode (Hs-mode) up to 3.4MHz */
+	I2C_MASTER_SPEED_HIGH_SPEED = SERCOM_I2CM_CTRLA_SPEED(2),
+};
+#endif
+
+#if I2C_MASTER_CALLBACK_MODE == true
+/**
+ * \brief Callback types
+ *
+ * The available callback types for the I<SUP>2</SUP>C master module.
+ */
+enum i2c_master_callback {
+	/** Callback for packet write complete */
+	I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0,
+	/** Callback for packet read complete */
+	I2C_MASTER_CALLBACK_READ_COMPLETE  = 1,
+	/** Callback for error */
+	I2C_MASTER_CALLBACK_ERROR          = 2,
+#  if !defined(__DOXYGEN__)
+	/** Total number of callbacks */
+	_I2C_MASTER_CALLBACK_N             = 3,
+#  endif
+};
+
+#  if !defined(__DOXYGEN__)
+/* Prototype for software module */
+struct i2c_master_module;
+
+typedef void (*i2c_master_callback_t)(
+		struct i2c_master_module *const module);
+#  endif
+#endif
+
+/**
+ * \brief SERCOM I<SUP>2</SUP>C Master driver software device instance structure.
+ *
+ * SERCOM I<SUP>2</SUP>C Master driver software instance structure, used to
+ * retain software state information of an associated hardware module instance.
+ *
+ * \note The fields of this structure should not be altered by the user
+ *       application; they are reserved for module-internal use only.
+ */
+struct i2c_master_module {
+#if !defined(__DOXYGEN__)
+	/** Hardware instance initialized for the struct */
+	Sercom *hw;
+	/** Module lock */
+	volatile bool locked;
+	/** Unknown bus state timeout */
+	uint16_t unknown_bus_state_timeout;
+	/** Buffer write timeout value */
+	uint16_t buffer_timeout;
+	/** If true, stop condition will be sent after a read/write */
+	bool send_stop;
+	/** If true, nack signal will be sent after a read/write */
+	bool send_nack;
+#  if I2C_MASTER_CALLBACK_MODE == true
+	/** Pointers to callback functions */
+	volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N];
+	/** Mask for registered callbacks */
+	volatile uint8_t registered_callback;
+	/** Mask for enabled callbacks */
+	volatile uint8_t enabled_callback;
+	/** The total number of bytes to transfer */
+	volatile uint16_t buffer_length;
+	/**
+	 * Counter used for bytes left to send in write and to count number of
+	 * obtained bytes in read
+	 */
+	volatile uint16_t buffer_remaining;
+	/** Data buffer for packet write and read */
+	volatile uint8_t *buffer;
+	/** Save direction of async request. 1 = read, 0 = write */
+	volatile enum i2c_transfer_direction transfer_direction;
+	/** Status for status read back in error callback */
+	volatile enum status_code status;
+#  endif
+#endif
+};
+
+/**
+ * \brief Configuration structure for the I<SUP>2</SUP>C Master device
+ *
+ * This is the configuration structure for the I<SUP>2</SUP>C Master device. It
+ * is used as an argument for \ref i2c_master_init to provide the desired
+ * configurations for the module. The structure should be initialized using the
+ * \ref i2c_master_get_config_defaults.
+ */
+struct i2c_master_config {
+	/** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
+	 * standard-mode, Fast-mode, and Fast-mode Plus Transfers,
+	 * \ref i2c_master_baud_rate */
+	uint32_t baud_rate;
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+	/** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
+	 * High-speed mode, \ref i2c_master_baud_rate */
+	uint32_t baud_rate_high_speed;
+	/** Transfer speed mode */
+	enum i2c_master_transfer_speed transfer_speed;
+#endif
+	/** GCLK generator to use as clock source */
+	enum gclk_generator generator_source;
+	/** Bus hold time after start signal on data line */
+	enum i2c_master_start_hold_time start_hold_time;
+	/** Unknown bus state \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" */
+	uint16_t unknown_bus_state_timeout;
+	/** Timeout for packet write to wait for slave */
+	uint16_t buffer_timeout;
+	/** Set to keep module active in sleep modes */
+	bool run_in_standby;
+	/** PAD0 (SDA) pinmux */
+	uint32_t pinmux_pad0;
+	/** PAD1 (SCL) pinmux */
+	uint32_t pinmux_pad1;
+	/** Set to enable SCL low time-out */
+	bool scl_low_timeout;
+	/** Inactive bus time out */
+	enum i2c_master_inactive_timeout inactive_timeout;
+#ifdef FEATURE_I2C_SCL_STRETCH_MODE
+	/** Set to enable SCL stretch only after ACK bit (required for high speed) */
+	bool scl_stretch_only_after_ack_bit;
+#endif
+#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
+	/** Set to enable slave SCL low extend time-out */
+	bool slave_scl_low_extend_timeout;
+	/** Set to enable maser SCL low extend time-out */
+	bool master_scl_low_extend_timeout;
+#endif
+	/** Get more accurate BAUD, considering rise time(required for standard-mode and Fast-mode) */
+	uint16_t sda_scl_rise_time_ns;
+};
+
+/**
+ * \name Lock/Unlock
+ * @{
+ */
+
+/**
+ * \brief Attempt to get lock on driver instance
+ *
+ * This function checks the instance's lock, which indicates whether or not it
+ * is currently in use, and sets the lock if it was not already set.
+ *
+ * The purpose of this is to enable exclusive access to driver instances, so
+ * that, e.g., transactions by different services will not interfere with each
+ * other.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline enum status_code i2c_master_lock(
+		struct i2c_master_module *const module)
+{
+	enum status_code status;
+
+	system_interrupt_enter_critical_section();
+
+	if (module->locked) {
+		status = STATUS_BUSY;
+	} else {
+		module->locked = true;
+		status = STATUS_OK;
+	}
+
+	system_interrupt_leave_critical_section();
+
+	return status;
+}
+
+/**
+ * \brief Unlock driver instance
+ *
+ * This function clears the instance lock, indicating that it is available for
+ * use.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ *
+ * \retval STATUS_OK If the module was locked
+ * \retval STATUS_BUSY If the module was already locked
+ */
+static inline void i2c_master_unlock(struct i2c_master_module *const module)
+{
+	module->locked = false;
+}
+
+/** @} */
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Returns the synchronization status of the module
+ *
+ * Returns the synchronization status of the module.
+ *
+ * \param[in]  module  Pointer to software module structure
+ *
+ * \return Status of the synchronization.
+ * \retval true   Module is busy synchronizing
+ * \retval false  Module is not synchronizing
+ */
+static inline bool i2c_master_is_syncing (
+		const struct i2c_master_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_hw = &(module->hw->I2CM);
+
+#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1)
+	return (i2c_hw->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY);
+#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2)
+	return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
+#else
+#  error Unknown SERCOM SYNCBUSY scheme!
+#endif
+}
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal
+ * Wait for hardware module to sync
+ *
+ * \param[in]  module  Pointer to software module structure
+ */
+static void _i2c_master_wait_for_sync(
+		const struct i2c_master_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+
+	while (i2c_master_is_syncing(module)) {
+		/* Wait for I2C module to sync. */
+	}
+}
+#endif
+
+/**
+ * \brief Gets the I<SUP>2</SUP>C master default configurations
+ *
+ * Use to initialize the configuration structure to known default values.
+ *
+ * The default configuration is as follows:
+ * - Baudrate 100KHz
+ * - GCLK generator 0
+ * - Do not run in standby
+ * - Start bit hold time 300ns - 600ns
+ * - Buffer timeout = 65535
+ * - Unknown bus status timeout = 65535
+ * - Do not run in standby
+ * - PINMUX_DEFAULT for SERCOM pads
+ *
+ * Those default configuration only available if the device supports it:
+ * - High speed baudrate 3.4MHz
+ * - Standard-mode and Fast-mode transfer speed
+ * - SCL stretch disabled
+ * - Slave SCL low extend time-out disabled
+ * - Master SCL low extend time-out disabled
+ *
+ * \param[out] config  Pointer to configuration structure to be initiated
+ */
+static inline void i2c_master_get_config_defaults(
+		struct i2c_master_config *const config)
+{
+	/*Sanity check argument */
+	Assert(config);
+	config->baud_rate        = I2C_MASTER_BAUD_RATE_100KHZ;
+#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
+	config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ;
+	config->transfer_speed       = I2C_MASTER_SPEED_STANDARD_AND_FAST;
+#endif
+	config->generator_source = GCLK_GENERATOR_0;
+	config->run_in_standby   = false;
+	config->start_hold_time  = I2C_MASTER_START_HOLD_TIME_300NS_600NS;
+	config->buffer_timeout   = 65535;
+	config->unknown_bus_state_timeout = 65535;
+	config->pinmux_pad0      = PINMUX_DEFAULT;
+	config->pinmux_pad1      = PINMUX_DEFAULT;
+	config->scl_low_timeout  = false;
+	config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED;
+#ifdef FEATURE_I2C_SCL_STRETCH_MODE
+	config->scl_stretch_only_after_ack_bit = false;
+#endif
+#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
+	config->slave_scl_low_extend_timeout   = false;
+	config->master_scl_low_extend_timeout  = false;
+#endif
+	/* The typical value is 215ns */
+	config->sda_scl_rise_time_ns = 215;
+}
+
+enum status_code i2c_master_init(
+		struct i2c_master_module *const module,
+		Sercom *const hw,
+		const struct i2c_master_config *const config);
+
+/**
+ * \brief Enables the I<SUP>2</SUP>C module
+ *
+ * Enables the requested I<SUP>2</SUP>C module and set the bus state to IDLE
+ * after the specified \ref asfdoc_sam0_sercom_i2c_timeout "timeout" period if no
+ * stop bit is detected.
+ *
+ * \param[in]  module  Pointer to the software module struct
+ */
+static inline void i2c_master_enable(
+		const struct i2c_master_module *const module)
+{
+	/* Sanity check of arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Timeout counter used to force bus state */
+	uint32_t timeout_counter = 0;
+
+	/* Wait for module to sync */
+	_i2c_master_wait_for_sync(module);
+
+	/* Enable module */
+	i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+
+#if I2C_MASTER_CALLBACK_MODE == true
+	/* Enable module interrupts */
+	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+#endif
+	/* Start timeout if bus state is unknown */
+	while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) {
+		timeout_counter++;
+		if(timeout_counter >= (module->unknown_bus_state_timeout)) {
+			/* Timeout, force bus state to idle */
+			i2c_module->STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(1);
+			/* Workaround #1 */
+			return;
+		}
+	}
+}
+
+/**
+ * \brief Disable the I<SUP>2</SUP>C module
+ *
+ * Disables the requested I<SUP>2</SUP>C module.
+ *
+ * \param[in]  module  Pointer to the software module struct
+ */
+static inline void i2c_master_disable(
+		const struct i2c_master_module *const module)
+{
+	/* Sanity check of arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+#if I2C_MASTER_CALLBACK_MODE == true
+		/* Disable module interrupts */
+		system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+#endif
+
+	/* Wait for module to sync */
+	_i2c_master_wait_for_sync(module);
+
+	/* Disbale interrupt */
+	i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
+	/* Clear interrupt flag */
+	i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MASK;
+
+	/* Disable module */
+	i2c_module->CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+
+}
+
+void i2c_master_reset(struct i2c_master_module *const module);
+
+/** @} */
+
+/**
+* \name Read and Write
+* @{
+*/
+
+enum status_code i2c_master_read_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_read_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_wait(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_wait_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+void i2c_master_send_stop(struct i2c_master_module *const module);
+
+void i2c_master_send_nack(struct i2c_master_module *const module);
+
+enum status_code i2c_master_read_byte(
+		struct i2c_master_module *const module,
+		uint8_t *byte);
+
+enum status_code i2c_master_write_byte(
+		struct i2c_master_module *const module,
+		uint8_t byte);
+
+enum status_code i2c_master_read_packet_wait_no_nack(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+/** @} */
+
+#ifdef FEATURE_I2C_DMA_SUPPORT
+/**
+* \name SERCOM I2C Master with DMA Interfaces
+* @{
+*/
+
+/**
+ * \brief Set I<SUP>2</SUP>C for DMA transfer with slave address and transfer size.
+ *
+ * This function will set the slave address, transfer size and enable the auto transfer
+ * mode for DMA.
+ *
+ * \param[in,out] module Pointer to the driver instance to lock
+ * \param[in] addr I<SUP>2</SUP>C slave address
+ * \param[in] length I<SUP>2</SUP>C transfer length with DMA
+ * \param[in] direction I<SUP>2</SUP>C transfer direction
+ *
+ */
+static inline void i2c_master_dma_set_transfer(struct i2c_master_module *const module,
+		uint16_t addr, uint8_t length, enum i2c_transfer_direction direction)
+{
+	module->hw->I2CM.ADDR.reg =
+		SERCOM_I2CM_ADDR_ADDR(addr<<1) |
+		SERCOM_I2CM_ADDR_LENEN |
+		SERCOM_I2CM_ADDR_LEN(length) |
+		direction;
+}
+
+/** @} */
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_MASTER_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/i2c/i2c_master_interrupt.h

@@ -0,0 +1,204 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Master Interrupt Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef I2C_MASTER_INTERRUPT_H_INCLUDED
+#define I2C_MASTER_INTERRUPT_H_INCLUDED
+
+#include "i2c_master.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_i2c_group
+ * @{
+ *
+ */
+
+/**
+ * \name Callbacks
+ * @{
+ */
+#if !defined(__DOXYGEN__)
+void _i2c_master_interrupt_handler(
+		uint8_t instance);
+#endif
+
+void i2c_master_register_callback(
+		struct i2c_master_module *const module,
+		i2c_master_callback_t callback,
+		enum i2c_master_callback callback_type);
+
+void i2c_master_unregister_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type);
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback specified by the callback_type.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback_type  Callback type to enable
+ */
+static inline void i2c_master_enable_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Mark callback as enabled */
+	module->enabled_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Disables callback
+ *
+ * Disables the callback specified by the callback_type.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback_type  Callback type to disable
+ */
+static inline void i2c_master_disable_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Mark callback as disabled */
+	module->enabled_callback &= ~(1 << callback_type);
+}
+
+/** @} */
+
+/**
+ * \name Read and Write, Interrupt-driven
+ * @{
+ */
+
+enum status_code i2c_master_read_bytes(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+ 
+enum status_code i2c_master_read_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_read_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_read_packet_job_no_nack(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_bytes(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+enum status_code i2c_master_write_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet);
+
+/**
+ * \brief Cancel any currently ongoing operation
+ *
+ * Terminates the running transfer operation.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static inline void i2c_master_cancel_job(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Set buffer to 0 */
+	module->buffer_remaining = 0;
+	/* Update status */
+	module->status = STATUS_ABORTED;
+}
+
+/**
+ * \brief Get status from ongoing job
+ *
+ * Will return the status of a transfer operation.
+ *
+ * \param[in] module  Pointer to software module structure
+ *
+ * \return Last status code from transfer operation.
+ * \retval STATUS_OK                    No error has occurred
+ * \retval STATUS_BUSY                  If transfer is in progress
+ * \retval STATUS_BUSY                  If master module is busy
+ * \retval STATUS_ERR_DENIED            If error on bus
+ * \retval STATUS_ERR_PACKET_COLLISION  If arbitration is lost
+ * \retval STATUS_ERR_BAD_ADDRESS       If slave is busy, or no slave
+ *                                      acknowledged the address
+ * \retval STATUS_ERR_TIMEOUT           If timeout occurred
+ * \retval STATUS_ERR_OVERFLOW          If slave did not acknowledge last sent
+ *                                      data, indicating that slave does not
+ *                                      want more data and was not able to read
+ */
+static inline enum status_code i2c_master_get_job_status(
+		struct i2c_master_module *const module)
+{
+	/* Check sanity */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Return current status code */
+	return module->status;
+}
+
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* I2C_MASTER_INTERRUPT_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c

@@ -0,0 +1,752 @@
+/**
+ * \file
+ *
+ * \brief SAM I2C Master Interrupt Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "i2c_master_interrupt.h"
+
+extern enum status_code _i2c_master_wait_for_bus(
+		struct i2c_master_module *const module);
+
+extern enum status_code _i2c_master_address_response(
+		struct i2c_master_module *const module);
+
+extern enum status_code _i2c_master_send_hs_master_code(
+		struct i2c_master_module *const module,
+		uint8_t hs_master_code);;
+
+/**
+ * \internal
+ * Read next data. Used by interrupt handler to get next data byte from slave.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_master_read(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+	bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+	/* Find index to save next value in buffer */
+	uint16_t buffer_index = module->buffer_length;
+	buffer_index -= module->buffer_remaining;
+
+	module->buffer_remaining--;
+
+	if (sclsm_flag) {
+		if (module->send_nack && module->buffer_remaining == 1) {
+			/* Set action to NACK. */
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+		}
+	} else {
+		if (module->send_nack && module->buffer_remaining == 0) {
+			/* Set action to NACK. */
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+		}
+	}
+
+	if (module->buffer_remaining == 0) {
+		if (module->send_stop) {
+			/* Send stop condition */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+		}
+	}
+	
+	/* Read byte from slave and put in buffer */
+	_i2c_master_wait_for_sync(module);
+	module->buffer[buffer_index] = i2c_module->DATA.reg;
+}
+
+/**
+ * \internal
+ *
+ * Write next data. Used by interrupt handler to send next data byte to slave.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_master_write(struct i2c_master_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Check for ack from slave */
+	if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
+	{
+		/* Set status */
+		module->status = STATUS_ERR_OVERFLOW;
+		/* Do not write more data */
+		return;
+	}
+
+	/* Find index to get next byte in buffer */
+	uint16_t buffer_index = module->buffer_length;
+	buffer_index -= module->buffer_remaining;
+
+	module->buffer_remaining--;
+
+	/* Write byte from buffer to slave */
+	_i2c_master_wait_for_sync(module);
+	i2c_module->DATA.reg = module->buffer[buffer_index];
+}
+
+/**
+ * \internal
+ * Acts on slave address response. Checks for errors concerning master->slave
+ * handshake.
+ *
+ * \param[in,out] module  Pointer to software module structure
+ */
+static void _i2c_master_async_address_response(
+		struct i2c_master_module *const module)
+{
+	/* Sanity check arguments. */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Check for error. Ignore bus-error; workaround for bus state stuck in
+	 * BUSY.
+	 */
+	if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB)
+	{
+		/* Clear write interrupt flag */
+		i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
+
+		/* Check arbitration */
+		if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
+			/* Return busy */
+			module->status = STATUS_ERR_PACKET_COLLISION;
+		}
+		/* No slave responds */
+		else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
+			module->status           = STATUS_ERR_BAD_ADDRESS;
+			module->buffer_remaining = 0;
+
+			if (module->send_stop) {
+				/* Send stop condition */
+				_i2c_master_wait_for_sync(module);
+				i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+			}
+		}
+	}
+
+	module->buffer_length = module->buffer_remaining;
+
+	/* Check for status OK. */
+	if (module->status == STATUS_BUSY) {
+		/* Call function based on transfer direction. */
+		if (module->transfer_direction == I2C_TRANSFER_WRITE) {
+			_i2c_master_write(module);
+		} else {
+			_i2c_master_read(module);
+		}
+	}
+}
+
+/**
+ * \brief Registers callback for the specified callback type
+ *
+ * Associates the given callback function with the
+ * specified callback type.
+ *
+ * To enable the callback, the \ref i2c_master_enable_callback function
+ * must be used.
+ *
+ * \param[in,out]  module         Pointer to the software module struct
+ * \param[in]      callback       Pointer to the function desired for the
+ *                                specified callback
+ * \param[in]      callback_type  Callback type to register
+ */
+void i2c_master_register_callback(
+		struct i2c_master_module *const module,
+		const i2c_master_callback_t callback,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(callback);
+
+	/* Register callback */
+	module->callbacks[callback_type] = callback;
+
+	/* Set corresponding bit to set callback as registered */
+	module->registered_callback |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters callback for the specified callback type
+ *
+ * When called, the currently registered callback for the given callback type
+ * will be removed.
+ *
+ * \param[in,out] module         Pointer to the software module struct
+ * \param[in]     callback_type  Specifies the callback type to unregister
+ */
+void i2c_master_unregister_callback(
+		struct i2c_master_module *const module,
+		enum i2c_master_callback callback_type)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Register callback */
+	module->callbacks[callback_type] = NULL;
+
+	/* Clear corresponding bit to set callback as unregistered */
+	module->registered_callback &= ~(1 << callback_type);
+}
+
+/**
+ * \internal
+ * Starts a read bytes operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_read_bytes(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_READ;
+	module->status             = STATUS_BUSY;
+	module->send_stop = false;
+	module->send_nack = false;
+	
+	/* Enable interrupts */
+	i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Starts a read packet operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+static enum status_code _i2c_master_read_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+	enum status_code tmp_status;
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_READ;
+	module->status             = STATUS_BUSY;
+
+	bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+	/* Switch to high speed mode */
+	if (packet->high_speed) {
+		_i2c_master_send_hs_master_code(module, packet->hs_master_code);
+	}
+
+	/* Set action to ACK or NACK. */
+	if ((sclsm_flag) && (packet->data_length == 1)) {
+		i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+	} else {
+		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+	}
+
+	if (packet->ten_bit_address) {
+		/*
+		 * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must
+		 * be set and read/write bit (ADDR.ADDR[0]) equal to 0.
+		 */
+		i2c_module->ADDR.reg = (packet->address << 1) |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+			SERCOM_I2CM_ADDR_TENBITEN;
+
+		/* Wait for response on bus. */
+		tmp_status = _i2c_master_wait_for_bus(module);
+
+		/* Set action to ack. */
+		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+		/* Check for address response error unless previous error is
+		 * detected. */
+		if (tmp_status == STATUS_OK) {
+			tmp_status = _i2c_master_address_response(module);
+		}
+
+		if (tmp_status == STATUS_OK) {
+			/* Enable interrupts */
+			i2c_module->INTENSET.reg =
+				SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+			/*
+			 * Write ADDR[7:0] register to "11110 address[9:8] 1"
+			 * ADDR.TENBITEN must be cleared
+			 */
+			i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) |
+				(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+				I2C_TRANSFER_READ;
+		} else {
+			return tmp_status;
+		}
+	} else {
+		/* Enable interrupts */
+		i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+		/* Set address and direction bit. Will send start command on bus */
+		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initiates a read packet operation
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
+ * bus. This is the non-blocking equivalent of \ref i2c_master_read_packet_wait.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK    If reading was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_read_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we send STOP */
+	module->send_stop = true;
+	module->send_nack = true;
+	/* Start reading */
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \brief Initiates a read packet operation without sending a STOP condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C bus without
+ * sending a stop condition, thus retaining ownership of the bus when done.
+ * To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK   If reading was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another operation
+ */
+enum status_code i2c_master_read_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we don't send STOP */
+	module->send_stop = false;
+	module->send_nack = true;
+	/* Start reading */
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \brief Initiates a read packet operation without sending a NACK signal and a 
+ * STOP condition when done
+ *
+ * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C bus without
+ * sending a nack and a stop condition, thus retaining ownership of the bus when done.
+ * To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition must be
+ * performed.
+ *
+ * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting reading I<SUP>2</SUP>C packet.
+ * \retval STATUS_OK   If reading was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another operation
+ */
+enum status_code i2c_master_read_packet_job_no_nack(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with a job */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we don't send STOP */
+	module->send_stop = false;
+	module->send_nack = false;
+	/* Start reading */
+	return _i2c_master_read_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Starts a write bytes operation.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting write I<SUP>2</SUP>C bytes.
+ * \retval STATUS_OK    If writing was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_write_bytes(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_WRITE;
+	module->status             = STATUS_BUSY;
+	module->send_stop = false;
+	module->send_nack = false;
+	
+	/* Enable interrupts */
+	i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal Initiates a write packet operation
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK   If writing was started successfully
+ * \retval STATUS_BUSY If module is currently busy with another transfer
+ */
+static enum status_code _i2c_master_write_packet(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+	/* Switch to high speed mode */
+	if (packet->high_speed) {
+		_i2c_master_send_hs_master_code(module, packet->hs_master_code);
+	}
+
+	/* Set action to ACK. */
+	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+	/* Save packet to software module */
+	module->buffer             = packet->data;
+	module->buffer_remaining   = packet->data_length;
+	module->transfer_direction = I2C_TRANSFER_WRITE;
+	module->status             = STATUS_BUSY;
+
+	/* Enable interrupts */
+	i2c_module->INTENSET.reg =
+			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+	/* Set address and direction bit, will send start command on bus */
+	if (packet->ten_bit_address) {
+		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+			SERCOM_I2CM_ADDR_TENBITEN;
+	} else {
+		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initiates a write packet operation
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C
+ * bus. This is the non-blocking equivalent of \ref i2c_master_write_packet_wait.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK    If writing was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another transfer
+ */
+enum status_code i2c_master_write_packet_job(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with another job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Make sure we send STOP at end*/
+	module->send_stop = true;
+	module->send_nack = true;
+	/* Start write operation */
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \brief Initiates a write packet operation without sending a STOP condition when done
+ *
+ * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
+ * without sending a stop condition, thus retaining ownership of the bus when
+ * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or
+ * \ref i2c_master_write_packet_wait "write" with stop condition or sending
+ * a stop with the \ref i2c_master_send_stop function must be performed.
+ *
+ * This is the non-blocking equivalent of \ref i2c_master_write_packet_wait_no_stop.
+ *
+ * \param[in,out] module  Pointer to software module struct
+ * \param[in,out] packet  Pointer to I<SUP>2</SUP>C packet to transfer
+ *
+ * \return Status of starting writing I<SUP>2</SUP>C packet job.
+ * \retval STATUS_OK    If writing was started successfully
+ * \retval STATUS_BUSY  If module is currently busy with another
+ */
+enum status_code i2c_master_write_packet_job_no_stop(
+		struct i2c_master_module *const module,
+		struct i2c_master_packet *const packet)
+{
+	/* Sanity check */
+	Assert(module);
+	Assert(module->hw);
+	Assert(packet);
+
+	/* Check if the I2C module is busy with another job. */
+	if (module->buffer_remaining > 0) {
+		return STATUS_BUSY;
+	}
+
+	/* Do not send stop condition when done */
+	module->send_stop = false;
+	module->send_nack = true;
+	/* Start write operation */
+	return _i2c_master_write_packet(module, packet);
+}
+
+/**
+ * \internal
+ * Interrupt handler for I<SUP>2</SUP>C master.
+ *
+ * \param[in] instance  SERCOM instance that triggered the interrupt
+ */
+void _i2c_master_interrupt_handler(
+		uint8_t instance)
+{
+	/* Get software module for callback handling */
+	struct i2c_master_module *module =
+			(struct i2c_master_module*)_sercom_instances[instance];
+
+	Assert(module);
+
+	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+	bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+	/* Combine callback registered and enabled masks */
+	uint8_t callback_mask = module->enabled_callback;
+	callback_mask &= module->registered_callback;
+
+	/* Check if the module should respond to address ack */
+	if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) {
+		/* Call function for address response */
+		_i2c_master_async_address_response(module);
+
+	/* Check if buffer write is done */
+	} else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+			(module->status == STATUS_BUSY) &&
+			(module->transfer_direction == I2C_TRANSFER_WRITE)) {
+		/* Stop packet operation */
+		i2c_module->INTENCLR.reg =
+				SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
+
+		module->buffer_length = 0;
+		module->status        = STATUS_OK;
+
+		if (module->send_stop) {
+			/* Send stop condition */
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+		} else {
+			/* Clear write interrupt flag */
+			i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+		}
+		
+		if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) {
+			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+		}
+
+	/* Continue buffer write/read */
+	} else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)){
+		/* Check that bus ownership is not lost */
+		if ((!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) &&
+				(!(sclsm_flag && (module->buffer_remaining == 1))))	{
+			module->status = STATUS_ERR_PACKET_COLLISION;
+		} else if (module->transfer_direction == I2C_TRANSFER_WRITE) {
+			_i2c_master_write(module);
+		} else {
+			_i2c_master_read(module);
+		}
+	}
+
+	/* Check if read buffer transfer is complete */
+	if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+			(module->status == STATUS_BUSY) &&
+			(module->transfer_direction == I2C_TRANSFER_READ)) {
+		
+		/* Clear read interrupt flag */
+		if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
+			i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+		}
+		/* Stop packet operation */
+		i2c_module->INTENCLR.reg =
+				SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
+		module->buffer_length = 0;
+		module->status        = STATUS_OK;
+
+		/* Call appropriate callback if enabled and registered */
+		if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
+				&& (module->transfer_direction == I2C_TRANSFER_READ)) {
+			module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
+		} else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
+				&& (module->transfer_direction == I2C_TRANSFER_WRITE)) {
+			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+		}
+	}
+
+	/* Check for error */
+	if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK)) {
+		/* Stop packet operation */
+		i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB |
+				SERCOM_I2CM_INTENCLR_SB;
+
+		module->buffer_length = 0;
+		module->buffer_remaining = 0;
+
+		/* Send nack and stop command unless arbitration is lost */
+		if ((module->status != STATUS_ERR_PACKET_COLLISION) &&
+				module->send_stop) {
+			_i2c_master_wait_for_sync(module);
+			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT |
+					SERCOM_I2CM_CTRLB_CMD(3);
+		}
+
+		/* Call error callback if enabled and registered */
+		if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR)) {
+			module->callbacks[I2C_MASTER_CALLBACK_ERROR](module);
+		}
+	}
+}

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/i2c/quick_start_master/qs_i2c_master_basic_use.h

@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Master Quick Start Guide
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_i2c_master_basic_use_case Quick Start Guide for SERCOM I2C Master - Basic
+ *
+ * In this use case, the I<SUP>2</SUP>C will used and set up as follows:
+ *  - Master mode
+ *  - 100KHz operation speed
+ *  - Not operational in standby
+ *  - 10000 packet timeout value
+ *  - 65535 unknown bus state timeout value
+ *
+ *
+ * \section asfdoc_sam0_sercom_i2c_master_basic_use_case_prereq Prerequisites
+ * The device must be connected to an I<SUP>2</SUP>C slave.
+ *
+ * \section asfdoc_sam0_sercom_i2c_master_basic_use_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_master_basic_use_setup_code Code
+ * The following must be added to the user application:
+ *
+ * - A sample buffer to send, a sample buffer to read:
+ * \snippet qs_i2c_master_basic_use.c packet_data
+ *
+ * - Slave address to access:
+ * \snippet qs_i2c_master_basic_use.c address
+ *
+ * - Number of times to try to send packet if it fails:
+ * \snippet qs_i2c_master_basic_use.c timeout
+ *
+ * - Globally accessible module structure:
+ * \snippet qs_i2c_master_basic_use.c dev_inst
+ *
+ * - Function for setting up the module:
+ * \snippet qs_i2c_master_basic_use.c initialize_i2c
+ *
+ * - Add to user application \c main():
+ * \snippet qs_i2c_master_basic_use.c init
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_master_basic_use_setup_workflow Workflow
+ * -# Configure and enable module.
+ *    \snippet qs_i2c_master_basic_use.c initialize_i2c
+ *   -# Create and initialize configuration structure.
+ *      \snippet qs_i2c_master_basic_use.c init_conf
+ *   -# Change settings in the configuration.
+ *      \snippet qs_i2c_master_basic_use.c conf_change
+ *   -# Initialize the module with the set configurations.
+ *      \snippet qs_i2c_master_basic_use.c init_module
+ *   -# Enable the module.
+ *      \snippet qs_i2c_master_basic_use.c enable_module
+ * -# Create a variable to see when we should stop trying to send packet.
+ *    \snippet qs_i2c_master_basic_use.c timeout_counter
+ * -# Create a packet to send.
+ *    \snippet qs_i2c_master_basic_use.c packet
+ *
+ * \section asfdoc_sam0_sercom_i2c_master_basic_use_implemenation Implementation
+ * \subsection asfdoc_sam0_sercom_i2c_master_basic_use_implemenation_code Code
+ * Add to user application \c main():
+ * \snippet qs_i2c_master_basic_use.c main
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_master_basic_use_implemenation_workflow Workflow
+ * -# Write packet to slave.
+ *    \snippet qs_i2c_master_basic_use.c write_packet
+ * The module will try to send the packet TIMEOUT number of times or until it is
+ * successfully sent.
+ * -# Read packet from slave.
+ *    \snippet qs_i2c_master_basic_use.c read_packet
+ * The module will try to read the packet TIMEOUT number of times or until it is
+ * successfully read.
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <asf.h>
+#include <conf_clocks.h>
+

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/i2c/quick_start_master_callback/qs_i2c_master_callback.h

@@ -0,0 +1,123 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Master Interface Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_i2c_master_callback_use_case Quick Start Guide for SERCOM I2C Master - Callback
+ *
+ * In this use case, the I<SUP>2</SUP>C will used and set up as follows:
+ *  - Master mode
+ *  - 100KHz operation speed
+ *  - Not operational in standby
+ *  - 65535 unknown bus state timeout value
+ *
+ * \section asfdoc_sam0_sercom_i2c_master_callback_use_case_prereq Prerequisites
+ * The device must be connected to an I<SUP>2</SUP>C slave.
+ *
+ * \section asfdoc_sam0_sercom_i2c_master_callback_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_setup_code Code
+ * The following must be added to the user application:
+ *
+ * A sample buffer to write from, a reversed buffer to write from and length of
+ * buffers.
+ * \snippet qs_i2c_master_callback.c packet_data
+ *
+ * Address of slave:
+ * \snippet qs_i2c_master_callback.c address
+ *
+ * Globally accessible module structure:
+ * \snippet qs_i2c_master_callback.c dev_inst
+ *
+ * Globally accessible packet:
+ * \snippet qs_i2c_master_callback.c packet_glob
+ *
+ * Function for setting up module:
+ * \snippet qs_i2c_master_callback.c initialize_i2c
+ *
+ * Callback function for write complete:
+ * \snippet qs_i2c_master_callback.c callback_func
+ *
+ * Function for setting up the callback functionality of the driver:
+ * \snippet qs_i2c_master_callback.c setup_callback
+ *
+ * Add to user application \c main():
+ * \snippet qs_i2c_master_callback.c run_initialize_i2c
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_setup_workflow Workflow
+ * -# Configure and enable module.
+ *    \snippet qs_i2c_master_callback.c config
+ *  -# Create and initialize configuration structure.
+ *     \snippet qs_i2c_master_callback.c init_conf
+ *  -# Change settings in the configuration.
+ *     \snippet qs_i2c_master_callback.c conf_change
+ *  -# Initialize the module with the set configurations.
+ *     \snippet qs_i2c_master_callback.c init_module
+ *  -# Enable the module.
+ *     \snippet qs_i2c_master_callback.c enable_module
+ * -# Configure callback functionality.
+ *    \snippet qs_i2c_master_callback.c config_callback
+ *  -# Register write complete callback.
+ *     \snippet qs_i2c_master_callback.c callback_reg
+ *  -# Enable write complete callback.
+ *     \snippet qs_i2c_master_callback.c callback_en
+ * -# Create a packet to send to slave.
+ *    \snippet qs_i2c_master_callback.c write_packet
+ *
+ * \section asfdoc_sam0_sercom_i2c_master_callback_use_case_implementation Implementation
+ * \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_code Code
+ * Add to user application \c main():
+ * \snippet qs_i2c_master_callback.c while
+ * \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_implementation_workflow Workflow
+ * -# Write packet to slave.
+ *    \snippet qs_i2c_master_callback.c write_packet
+ * -# Infinite while loop, while waiting for interaction with slave.
+ *    \snippet qs_i2c_master_callback.c while
+ *
+ * \section asfdoc_sam0_sercom_i2c_master_callback_use_case_callback Callback
+ * Each time a packet is sent, the callback function will be called.
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_master_callback_use_case_callback_workflow Workflow
+ * - Write complete callback:
+ *  -# Send every other packet in reversed order.
+ *     \snippet qs_i2c_master_callback.c revert_order
+ *  -# Write new packet to slave.
+ *     \snippet qs_i2c_master_callback.c write_packet
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <asf.h>
+#include <conf_clocks.h>
+

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/i2c/quick_start_master_dma/qs_i2c_master_dma.h

@@ -0,0 +1,164 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM I2C Master Driver with DMA Quick Start Guide
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_i2c_master_dma_use_case Quick Start Guide for Using DMA with SERCOM I2C Master
+ *
+ * The supported board list:
+ *    - SAMD21 Xplained Pro
+ *    - SAMR21 Xplained Pro
+ *    - SAML21 Xplained Pro
+ *    - SAML22 Xplained Pro
+ *    - SAMDA1 Xplained Pro
+ *    - SAMC21 Xplained Pro
+ *    - SAMHA1G16A Xplained Pro
+ *
+ * In this use case, the I<SUP>2</SUP>C will used and set up as follows:
+ *  - Master mode
+ *  - 100KHz operation speed
+ *  - Not operational in standby
+ *  - 10000 packet timeout value
+ *  - 65535 unknown bus state timeout value
+ *
+ *
+ * \section asfdoc_sam0_sercom_i2c_master_dma_use_case_prereq Prerequisites
+ * The device must be connected to an I<SUP>2</SUP>C slave.
+ *
+ * \section asfdoc_sam0_sercom_i2c_master_dma_use_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_code Code
+ * The following must be added to the user application:
+ *
+ * - A sample buffer to send, number of entries to send and address of slave:
+ * \snippet qs_i2c_master_dma.c packet_data
+ *
+ * Number of times to try to send packet if it fails:
+ * \snippet qs_i2c_master_dma.c timeout
+ *
+ * - Globally accessible module structure:
+ * \snippet qs_i2c_master_dma.c dev_i2c_inst
+ *
+ * - Function for setting up the module:
+ * \snippet qs_i2c_master_dma.c initialize_i2c
+ *
+ * - Globally accessible DMA module structure:
+ * \snippet qs_i2c_master_dma.c dma_resource
+ *
+ * - Globally transfer done flag:
+ * \snippet qs_i2c_master_dma.c transfer_done_flag
+ *
+ * - Globally accessible DMA transfer descriptor:
+ * \snippet qs_i2c_master_dma.c transfer_descriptor
+ *
+ * - Function for transfer done callback:
+ * \snippet qs_i2c_master_dma.c transfer_done
+ *
+ * - Function for setting up the DMA resource:
+ * \snippet qs_i2c_master_dma.c config_dma_resource
+ *
+ * - Function for setting up the DMA transfer descriptor:
+ * \snippet qs_i2c_master_dma.c setup_dma_transfer_descriptor
+ * - Add to user application \c main():
+ * \snippet qs_i2c_master_dma.c init
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_master_dma_use_setup_workflow Workflow
+ * -# Configure and enable module:
+ * \snippet qs_i2c_master_dma.c config_i2c
+ *  -# Create and initialize configuration structure.
+ *    \snippet qs_i2c_master_dma.c init_conf
+ *  -# Change settings in the configuration.
+ *    \snippet qs_i2c_master_dma.c conf_change
+ *  -# Initialize the module with the set configurations.
+ *    \snippet qs_i2c_master_dma.c init_module
+ *  -# Enable the module.
+ *    \snippet qs_i2c_master_dma.c enable_module
+ *
+ * -# Configure DMA
+ *  -# Create a DMA resource configuration structure, which can be filled out to
+ *    adjust the configuration of a single DMA transfer.
+ *    \snippet qs_i2c_master_dma.c dma_setup_1
+ *
+ *  -# Initialize the DMA resource configuration struct with the module's
+ *    default values.
+ *    \snippet qs_i2c_master_dma.c dma_setup_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ *  -# Set extra configurations for the DMA resource. It is using peripheral
+ *    trigger. SERCOM TX trigger causes a transaction transfer in
+ *    this example.
+ *    \snippet qs_i2c_master_dma.c dma_setup_3
+ *
+ *  -# Allocate a DMA resource with the configurations.
+ *    \snippet qs_i2c_master_dma.c dma_setup_4
+ *
+ *  -# Create a DMA transfer descriptor configuration structure, which can be
+ *    filled out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_i2c_master_dma.c dma_setup_5
+ *
+ *  -# Initialize the DMA transfer descriptor configuration struct with the module's
+ *    default values.
+ *    \snippet qs_i2c_master_dma.c dma_setup_6
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ *  -# Set the specific parameters for a DMA transfer with transfer size, source
+ *    address, and destination address.
+ *    \snippet qs_i2c_master_dma.c dma_setup_7
+ *
+ *  -# Create the DMA transfer descriptor.
+ *    \snippet qs_i2c_master_dma.c dma_setup_8
+ *
+ * \section asfdoc_sam0_sercom_i2c_master_dma_use_implemenation Implementation
+ * \subsection asfdoc_sam0_sercom_i2c_master_dma_use_implemenation_code Code
+ * Add to user application \c main():
+ * \snippet qs_i2c_master_dma.c main
+ *
+ * \subsection asfdoc_sam0_sercom_i2c_master_dma_use_implemenation_workflow Workflow
+ * -# Start the DMA transfer job.
+ *    \snippet qs_i2c_master_dma.c start_transfer_job
+ *
+ * -# Set the auto address length and enable flag.
+ *    \snippet qs_i2c_master_dma.c set_i2c_addr
+ * 
+ * -# Waiting for transfer complete.
+ *    \snippet qs_i2c_master_dma.c waiting_for_complete
+ *
+ * -# Enter an infinite loop once transfer complete.
+ *    \snippet qs_i2c_master_dma.c inf_loop
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/sercom.c

@@ -0,0 +1,280 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "sercom.h"
+
+#define SHIFT 32
+#define BAUD_INT_MAX   8192
+#define BAUD_FP_MAX     8
+
+#if !defined(__DOXYGEN__)
+/**
+ * \internal Configuration structure to save current gclk status.
+ */
+struct _sercom_conf {
+	/* Status of gclk generator initialization */
+	bool generator_is_set;
+	/* Sercom gclk generator used */
+	enum gclk_generator generator_source;
+};
+
+static struct _sercom_conf _sercom_config;
+
+
+/**
+ * \internal Calculate 64 bit division, ref can be found in
+ * http://en.wikipedia.org/wiki/Division_algorithm#Long_division
+ */
+static uint64_t long_division(uint64_t n, uint64_t d)
+{
+	int32_t i;
+	uint64_t q = 0, r = 0, bit_shift;
+	for (i = 63; i >= 0; i--) {
+		bit_shift = (uint64_t)1 << i;
+
+		r = r << 1;
+
+		if (n & bit_shift) {
+			r |= 0x01;
+		}
+
+		if (r >= d) {
+			r = r - d;
+			q |= bit_shift;
+		}
+	}
+
+	return q;
+}
+
+/**
+ * \internal Calculate synchronous baudrate value (SPI/UART)
+ */
+enum status_code _sercom_get_sync_baud_val(
+		const uint32_t baudrate,
+		const uint32_t external_clock,
+		uint16_t *const baudvalue)
+{
+	/* Baud value variable */
+	uint16_t baud_calculated = 0;
+	uint32_t clock_value = external_clock;
+
+
+	/* Check if baudrate is outside of valid range */
+	if (baudrate > (external_clock / 2)) {
+		/* Return with error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	}
+
+	/* Calculate BAUD value from clock frequency and baudrate */
+	clock_value = external_clock / 2;
+	while (clock_value >= baudrate) {
+		clock_value = clock_value - baudrate;
+		baud_calculated++;
+	}
+	baud_calculated = baud_calculated - 1;
+
+	/* Check if BAUD value is more than 255, which is maximum
+	 * for synchronous mode */
+	if (baud_calculated > 0xFF) {
+		/* Return with an error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	} else {
+		*baudvalue = baud_calculated;
+		return STATUS_OK;
+	}
+}
+
+/**
+ * \internal Calculate asynchronous baudrate value (UART)
+*/
+enum status_code _sercom_get_async_baud_val(
+		const uint32_t baudrate,
+		const uint32_t peripheral_clock,
+		uint16_t *const baudval,
+		enum sercom_asynchronous_operation_mode mode,
+		enum sercom_asynchronous_sample_num sample_num)
+{
+	/* Temporary variables  */
+	uint64_t ratio = 0;
+	uint64_t scale = 0;
+	uint64_t baud_calculated = 0;
+	uint8_t baud_fp;
+	uint32_t baud_int = 0;
+	uint64_t temp1;
+
+	/* Check if the baudrate is outside of valid range */
+	if ((baudrate * sample_num) > peripheral_clock) {
+		/* Return with error code */
+		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+	}
+
+	if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
+		/* Calculate the BAUD value */
+		temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
+		ratio = long_division(temp1, peripheral_clock);
+		scale = ((uint64_t)1 << SHIFT) - ratio;
+		baud_calculated = (65536 * scale) >> SHIFT;
+	} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
+		temp1 = ((uint64_t)baudrate * sample_num);
+		baud_int = long_division( peripheral_clock, temp1);
+		if(baud_int > BAUD_INT_MAX) {
+				return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+		}
+		temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
+		baud_fp = temp1 - 8 * baud_int;
+		baud_calculated = baud_int | (baud_fp << 13);
+	}
+
+	*baudval = baud_calculated;
+	return STATUS_OK;
+}
+#endif
+
+/**
+ * \brief Set GCLK channel to generator.
+ *
+ * This will set the appropriate GCLK channel to the requested GCLK generator.
+ * This will set the generator for all SERCOM instances, and the user will thus
+ * only be able to set the same generator that has previously been set, if any.
+ *
+ * After the generator has been set the first time, the generator can be changed
+ * using the \c force_change flag.
+ *
+ * \param[in]  generator_source The generator to use for SERCOM.
+ * \param[in]  force_change     Force change the generator.
+ *
+ * \return Status code indicating the GCLK generator change operation.
+ * \retval STATUS_OK                       If the generator update request was
+ *                                         successful.
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  If a generator was already configured
+ *                                         and the new configuration was not
+ *                                         forced.
+ */
+enum status_code sercom_set_gclk_generator(
+		const enum gclk_generator generator_source,
+		const bool force_change)
+{
+	/* Check if valid option */
+	if (!_sercom_config.generator_is_set || force_change) {
+		/* Create and fill a GCLK configuration structure for the new config */
+		struct system_gclk_chan_config gclk_chan_conf;
+		system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+		gclk_chan_conf.source_generator = generator_source;
+		system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
+		system_gclk_chan_enable(SERCOM_GCLK_ID);
+
+		/* Save config */
+		_sercom_config.generator_source = generator_source;
+		_sercom_config.generator_is_set = true;
+
+		return STATUS_OK;
+	} else if (generator_source == _sercom_config.generator_source) {
+		/* Return status OK if same config */
+		return STATUS_OK;
+	}
+
+	/* Return invalid config to already initialized GCLK */
+	return STATUS_ERR_ALREADY_INITIALIZED;
+}
+
+/** \internal
+ * Creates a switch statement case entry to convert a SERCOM instance and pad
+ * index to the default SERCOM pad MUX setting.
+ */
+#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \
+		case (uintptr_t)SERCOM##n: \
+			switch (pad) { \
+				case 0: \
+					return SERCOM##n##_PAD0_DEFAULT; \
+				case 1: \
+					return SERCOM##n##_PAD1_DEFAULT; \
+				case 2: \
+					return SERCOM##n##_PAD2_DEFAULT; \
+				case 3: \
+					return SERCOM##n##_PAD3_DEFAULT; \
+			} \
+			break;
+
+/**
+ * \internal Gets the default PAD pinout for a given SERCOM.
+ *
+ * Returns the pinmux settings for the given SERCOM and pad. This is used
+ * for default configuration of pins.
+ *
+ * \param[in]  sercom_module   Pointer to the SERCOM module
+ * \param[in]  pad             PAD to get default pinout for
+ *
+ * \returns The default pinmux for the given SERCOM instance and PAD
+ *
+ */
+uint32_t _sercom_get_default_pad(
+		Sercom *const sercom_module,
+		const uint8_t pad)
+{
+	switch ((uintptr_t)sercom_module) {
+		/* Auto-generate a lookup table for the default SERCOM pad defaults */
+		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+	}
+
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \internal
+ * Find index of given instance.
+ *
+ * \param[in] sercom_instance  Instance pointer.
+ *
+ * \return Index of given instance.
+ */
+uint8_t _sercom_get_sercom_inst_index(
+		Sercom *const sercom_instance)
+{
+	/* Save all available SERCOM instances for compare */
+	Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
+
+	/* Find index for sercom instance */
+	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+		if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given */
+	Assert(false);
+	return 0;
+}

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/sercom.h

@@ -0,0 +1,108 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef SERCOM_H_INCLUDED
+#define SERCOM_H_INCLUDED
+
+#include <compiler.h>
+#include <system.h>
+#include <clock.h>
+#include <system_interrupt.h>
+#include "sercom_pinout.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* SERCOM modules should share  same slow GCLK channel ID */
+#define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW
+
+#if (0x1ff >= REV_SERCOM)
+#  define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1
+#elif (0x400 >= REV_SERCOM)
+#  define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2
+#else
+#  error "Unknown SYNCBUSY scheme for this SERCOM revision"
+#endif
+
+/**
+ * \brief sercom asynchronous operation mode
+ *
+ * Select sercom asynchronous operation mode
+ */
+enum sercom_asynchronous_operation_mode {
+	SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0,
+	SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL,
+};
+
+/**
+ * \brief sercom asynchronous samples per bit
+ *
+ * Select number of samples per bit
+ */
+enum sercom_asynchronous_sample_num {
+	SERCOM_ASYNC_SAMPLE_NUM_3 = 3,
+	SERCOM_ASYNC_SAMPLE_NUM_8 = 8,
+	SERCOM_ASYNC_SAMPLE_NUM_16 = 16,
+};
+
+enum status_code sercom_set_gclk_generator(
+		const enum gclk_generator generator_source,
+		const bool force_change);
+
+enum status_code _sercom_get_sync_baud_val(
+		const uint32_t baudrate,
+		const uint32_t external_clock,
+		uint16_t *const baudval);
+
+enum status_code _sercom_get_async_baud_val(
+		const uint32_t baudrate,
+		const uint32_t peripheral_clock,
+		uint16_t *const baudval,
+		enum sercom_asynchronous_operation_mode mode,
+		enum sercom_asynchronous_sample_num sample_num);
+
+uint32_t _sercom_get_default_pad(
+		Sercom *const sercom_module,
+		const uint8_t pad);
+
+uint8_t _sercom_get_sercom_inst_index(
+		Sercom *const sercom_instance);
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SERCOM_H_INCLUDED

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/sercom_interrupt.c

@@ -0,0 +1,131 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "sercom_interrupt.h"
+
+void *_sercom_instances[SERCOM_INST_NUM];
+
+/** Save status of initialized handlers */
+static bool _handler_table_initialized = false;
+
+/** Void pointers for saving device instance structures */
+static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance);
+
+/**
+ * \internal
+ * Default interrupt handler.
+ *
+ * \param[in] instance SERCOM instance used.
+ */
+static void _sercom_default_handler(
+		const uint8_t instance)
+{
+	Assert(false);
+}
+
+/**
+ * \internal
+ * Saves the given callback handler.
+ *
+ * \param[in]  instance           Instance index.
+ * \param[in]  interrupt_handler  Pointer to instance callback handler.
+ */
+void _sercom_set_handler(
+		const uint8_t instance,
+		const sercom_handler_t interrupt_handler)
+{
+	/* Initialize handlers with default handler and device instances with 0 */
+	if (_handler_table_initialized == false) {
+		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
+			_sercom_interrupt_handlers[i] = &_sercom_default_handler;
+			_sercom_instances[i] = NULL;
+		}
+
+		_handler_table_initialized = true;
+	}
+
+	/* Save interrupt handler */
+	_sercom_interrupt_handlers[instance] = interrupt_handler;
+}
+
+
+/** \internal
+ * Converts a given SERCOM index to its interrupt vector index.
+ */
+#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \
+		SYSTEM_INTERRUPT_MODULE_SERCOM##n,
+
+/** \internal
+ * Generates a SERCOM interrupt handler function for a given SERCOM index.
+ */
+#define _SERCOM_INTERRUPT_HANDLER(n, unused) \
+		void SERCOM##n##_Handler(void) \
+		{ \
+			_sercom_interrupt_handlers[n](n); \
+		}
+
+/**
+ * \internal
+ * Returns the system interrupt vector.
+ *
+ * \param[in]  sercom_instance  Instance pointer
+ *
+ * \return Enum of system interrupt vector
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM0
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM1
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM2
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM3
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM4
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM5
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
+ * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
+ */
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+		Sercom *const sercom_instance)
+{
+	const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
+		{
+			MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
+		};
+
+	/* Retrieve the index of the SERCOM being requested */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
+
+	/* Get the vector number from the lookup table for the requested SERCOM */
+	return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
+}
+
+/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
+MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/sercom_interrupt.h

@@ -0,0 +1,62 @@
+/**
+ * \file
+ *
+ * \brief SAM Serial Peripheral Interface Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SERCOM_INTERRUPT_H_INCLUDED
+#define SERCOM_INTERRUPT_H_INCLUDED
+
+#include "sercom.h"
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Look-up table for device instances */
+extern void *_sercom_instances[SERCOM_INST_NUM];
+
+typedef void (*sercom_handler_t)(uint8_t instance);
+
+enum system_interrupt_vector _sercom_get_interrupt_vector(
+		Sercom *const sercom_instance);
+
+void _sercom_set_handler(
+		const uint8_t instance,
+		const sercom_handler_t interrupt_handler);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SERCOM_INTERRUPT_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/sercom_pinout.h

@@ -0,0 +1,612 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM Module Pinout Definitions
+ *
+ *
+ * Copyright (c) 2012-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SERCOM_PINOUT_H_INCLUDED
+#define SERCOM_PINOUT_H_INCLUDED
+
+#include <compiler.h>
+
+#if SAMR21E
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+# if SAM_PART_IS_DEFINED(SAMR21E19A)
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+# else
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA27F_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA28F_SERCOM3_PAD1
+#endif
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+	/* SERCOM4 */
+# if SAM_PART_IS_DEFINED(SAMR21E19A)
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+# else
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
+# endif
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif SAMR21G
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif (SAMD09)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
+
+#elif (SAMD10DS) || (SAMD10DM) || (SAMD10DU) || (SAMD11DS) || (SAMD11DM) || (SAMD11DU) 
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA22C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA23C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA16D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA25D_SERCOM2_PAD3
+
+#elif (SAMD10C) || (SAMD11C)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
+
+#elif SAM_PART_IS_DEFINED(SAMD21E15L) || SAM_PART_IS_DEFINED(SAMD21E16L)
+
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+#elif (SAML22N)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PB02C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PB21C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PB00C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PB01C_SERCOM3_PAD3
+
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12C_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13C_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14C_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15C_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
+#elif (SAML22J) || (SAML22G)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA12D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA13D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA14D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA15D_SERCOM3_PAD3
+#elif (SAMC20E) || (SAMC21E)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+#elif (SAMC20G) || (SAMC21G)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+  #ifdef ID_SERCOM4
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+  #endif
+
+  #ifdef ID_SERCOM5
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
+  #endif
+
+#elif (SAMC20J) || (SAMC21J)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+
+  #ifdef ID_SERCOM4
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+  #endif
+
+  #ifdef ID_SERCOM5
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB00D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB01D_SERCOM5_PAD3
+  #endif
+
+#elif (SAMDA1)
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if (SAMDA1E)
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+  #else
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+  #endif
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#elif   (SAMHA1E) || (SAMHA0E)
+	
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM5_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA20C_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      0 /* No available pin */
+	
+#elif   (SAMHA1G) || (SAMHA0G)
+	
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+   
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+    
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+    
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+    
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB16C_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB17C_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA20C_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA21C_SERCOM5_PAD3
+
+#elif (SAML21E) || (SAMR34) || (SAMR35) || (WLR089)
+
+	/* SERCOM0 */
+ 	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+ 	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if !SAM_PART_IS_DEFINED(SAML21E18A) 
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+	
+    /* SERCOM5 */
+    #define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+    #define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+  #endif
+  
+#elif  (SAMR30E)
+
+   /* SERCOM0 */
+   #define SERCOM0_PAD0_DEFAULT      0 /* No available pin */
+   #define SERCOM0_PAD1_DEFAULT      0 /* No available pin */
+   #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+   #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+   /* SERCOM1 */
+   #define SERCOM1_PAD0_DEFAULT      0 /* No available pin */
+   #define SERCOM1_PAD1_DEFAULT      0 /* No available pin */
+   #define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+   #define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+   /* SERCOM2 */
+   #define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+   #define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+   #define SERCOM2_PAD2_DEFAULT      0 /* No available pin */
+   #define SERCOM2_PAD3_DEFAULT      0 /* No available pin */
+
+   /* SERCOM3 */
+   #define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+   #define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+   #define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+   #define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  /* SERCOM4 */
+  #define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+  #define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+  #define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+  #define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+
+  /* SERCOM5 */
+  #define SERCOM5_PAD0_DEFAULT      0
+  #define SERCOM5_PAD1_DEFAULT      0
+  #define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+  #define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+
+#else
+	/* SERCOM0 */
+	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+	/* SERCOM1 */
+#if SAM_PART_IS_DEFINED(SAMD21G15L) || SAM_PART_IS_DEFINED(SAMD21G16L)
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+#else
+	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+#endif
+
+	/* SERCOM2 */
+	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+	/* SERCOM3 */
+	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+  #if !(SAMD20E || SAMD21E)
+	/* SERCOM4 */
+	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
+	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+
+	/* SERCOM5 */
+	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+  #endif
+  
+#endif
+#endif /* SERCOM_PINOUT_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/spi/quick_start_dma/qs_spi_dma_use.h

@@ -0,0 +1,258 @@
+/**
+ * \file
+ *
+ * \brief SAM D21/R21/L21/L22/DA1/C21/R30 Quick Start Guide for Using SPI driver with DMA
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_spi_dma_use_case Quick Start Guide for Using DMA with SERCOM SPI
+ *
+ * The supported board list:
+ *    - SAM D21 Xplained Pro
+ *    - SAM R21 Xplained Pro
+ *    - SAM L21 Xplained Pro
+ *    - SAM L22 Xplained Pro
+ *    - SAM DA1 Xplained Pro
+ *    - SAM C21 Xplained Pro
+ *    - SAM R30 Xplained Pro
+ *
+ * This quick start will transmit a buffer data from master to slave through DMA.
+ * In this use case the SPI master will be configured with the following
+ * settings on SAM Xplained Pro:
+ * - Master Mode enabled
+ * - MSB of the data is transmitted first
+ * - Transfer mode 0
+ * - SPI MUX Setting E
+ * - 8-bit character size
+ * - Not enabled in sleep mode
+ * - Baudrate 100000
+ * - GLCK generator 0
+ *
+ * The SPI slave will be configured with the following settings:
+ * - Slave mode enabled
+ * - Preloading of shift register enabled
+ * - MSB of the data is transmitted first
+ * - Transfer mode 0
+ * - SPI MUX Setting E
+ * - 8-bit character size
+ * - Not enabled in sleep mode
+ * - GLCK generator 0
+ *
+ * Note that the pinouts on other boards may different, see next sector for
+ * details.
+ *
+ * \section asfdoc_sam0_sercom_spi_dma_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_spi_dma_use_case_prereq Prerequisites
+ * The following connections has to be made using wires:
+ * - SAM D21/DA1 Xplained Pro.
+ *  - \b SS_0:  EXT1 PIN15 (PA05) <--> EXT2 PIN15 (PA17)
+ *  - \b DO/DI: EXT1 PIN16 (PA06) <--> EXT2 PIN17 (PA16)
+ *  - \b DI/DO: EXT1 PIN17 (PA04) <--> EXT2 PIN16 (PA18)
+ *  - \b SCK:   EXT1 PIN18 (PA07) <--> EXT2 PIN18 (PA19)
+ * - SAM R21 Xplained Pro.
+ *  - \b SS_0:  EXT1 PIN15 (PB03) <--> EXT1 PIN10 (PA23)
+ *  - \b DO/DI: EXT1 PIN16 (PB22) <--> EXT1 PIN9  (PA22)
+ *  - \b DI/DO: EXT1 PIN17 (PB02) <--> EXT1 PIN7  (PA18)
+ *  - \b SCK:   EXT1 PIN18 (PB23) <--> EXT1 PIN8  (PA19)
+ * - SAM L21 Xplained Pro.
+ *  - \b SS_0:  EXT1 PIN15 (PA05) <--> EXT1 PIN12 (PA09)
+ *  - \b DO/DI: EXT1 PIN16 (PA06) <--> EXT1 PIN11 (PA08)
+ *  - \b DI/DO: EXT1 PIN17 (PA04) <--> EXT2 PIN03 (PA10)
+ *  - \b SCK:   EXT1 PIN18 (PA07) <--> EXT2 PIN04 (PA11)
+ * - SAM L22 Xplained Pro.
+ *  - \b SS_0:  EXT1 PIN15 (PB21) <--> EXT2 PIN15 (PA17)
+ *  - \b DO/DI: EXT1 PIN16 (PB00) <--> EXT2 PIN17 (PA16)
+ *  - \b DI/DO: EXT1 PIN17 (PB02) <--> EXT2 PIN16 (PA18)
+ *  - \b SCK:   EXT1 PIN18 (PB01) <--> EXT2 PIN18 (PA19)
+ * - SAM C21 Xplained Pro.
+ *  - \b SS_0:  EXT1 PIN15 (PA17) <--> EXT2 PIN15 (PB03)
+ *  - \b DO/DI: EXT1 PIN16 (PA18) <--> EXT2 PIN17 (PB02)
+ *  - \b DI/DO: EXT1 PIN17 (PA16) <--> EXT2 PIN16 (PB00)
+ *  - \b SCK:   EXT1 PIN18 (PA19) <--> EXT2 PIN18 (PB01)
+ *
+ * \subsection asfdoc_sam0_spi_dma_use_case_setup_code Code
+ *
+ * Add to the main application source file, before user definitions and
+ * functions according to your board:
+ *
+ * For SAM D21 Xplained Pro:
+ * \snippet samd21_xplained_pro/conf_quick_start.h definition_master
+ * \snippet samd21_xplained_pro/conf_quick_start.h definition_slave
+ * \snippet samd21_xplained_pro/conf_quick_start.h definition_peripheral_trigger
+ * For SAM R21 Xplained Pro:
+ * \snippet samr21_xplained_pro/conf_quick_start.h definition_master
+ * \snippet samr21_xplained_pro/conf_quick_start.h definition_slave
+ * \snippet samr21_xplained_pro/conf_quick_start.h definition_peripheral_trigger
+ * For SAM L21 Xplained Pro:
+ * \snippet saml21_xplained_pro/conf_quick_start.h definition_master
+ * \snippet saml21_xplained_pro/conf_quick_start.h definition_slave
+ * \snippet saml21_xplained_pro/conf_quick_start.h definition_peripheral_trigger
+ * For SAM L22 Xplained Pro:
+ * \snippet saml22_xplained_pro/conf_quick_start.h definition_master
+ * \snippet saml22_xplained_pro/conf_quick_start.h definition_slave
+ * \snippet saml22_xplained_pro/conf_quick_start.h definition_peripheral_trigger
+ * For SAM DA1 Xplained Pro:
+ * \snippet samda1_xplained_pro/conf_quick_start.h definition_master
+ * \snippet samda1_xplained_pro/conf_quick_start.h definition_slave
+ * \snippet samda1_xplained_pro/conf_quick_start.h definition_peripheral_trigger
+ * For SAM C21 Xplained Pro:
+ * \snippet samc21_xplained_pro/conf_quick_start.h definition_master
+ * \snippet samc21_xplained_pro/conf_quick_start.h definition_slave
+ * \snippet samc21_xplained_pro/conf_quick_start.h definition_peripheral_trigger
+ *
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_spi_dma_use.c buf_length
+ * \snippet qs_spi_dma_use.c spi_baudrate
+ * \snippet qs_spi_dma_use.c slave_select_pin
+ * \snippet qs_spi_dma_use.c spi_buffer
+ * \snippet qs_spi_dma_use.c spi_module_inst
+ * \snippet qs_spi_dma_use.c dma_transfer_done_flag
+ * \snippet qs_spi_dma_use.c slave_dev_inst
+ * \snippet qs_spi_dma_use.c dma_transfer_descriptor
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_spi_dma_use.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_spi_dma_use.c setup_init
+ *
+ * \subsection asfdoc_sam0_spi_dma_use_case_setup_flow Workflow
+ * -# Create a module software instance structure for the SPI module to store
+ *    the SPI driver state while it is in use.
+ *    \snippet qs_spi_dma_use.c spi_module_inst
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Create a module software instance structure for DMA resource to store
+ *    the DMA resource state while it is in use.
+ *    \snippet qs_spi_dma_use.c dma_resource
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Create transfer done flag to indication DMA transfer done.
+ *    \snippet qs_spi_dma_use.c dma_transfer_done_flag
+ * -# Define the buffer length for TX/RX.
+ *    \snippet qs_spi_dma_use.c buf_length
+ * -# Create buffer to store the data to be transferred.
+ *    \snippet qs_spi_dma_use.c spi_buffer
+ * -# Create the SPI module configuration struct, which can be filled out to
+ *     adjust the configuration of a physical SPI peripheral.
+ *     \snippet qs_spi_dma_use.c spi_master_config
+ *     \snippet qs_spi_dma_use.c spi_slave_config
+ * -# Initialize the SPI configuration struct with the module's default values.
+ *     \snippet qs_spi_dma_use.c spi_master_conf_defaults
+ *     \snippet qs_spi_dma_use.c spi_slave_conf_defaults
+ *     \note This should always be performed before using the configuration
+ *           struct to ensure that all values are initialized to known default
+ *           settings.
+ *
+ * -# Alter the SPI settings to configure the physical pinout, baudrate, and
+ *     other relevant parameters.
+ *     \snippet qs_spi_dma_use.c spi_master_mux_setting
+ *     \snippet qs_spi_dma_use.c spi_slave_mux_setting
+ * -# Configure the SPI module with the desired settings, retrying while the
+ *     driver is busy until the configuration is stressfully set.
+ *     \snippet qs_spi_dma_use.c spi_master_init
+ *     \snippet qs_spi_dma_use.c spi_slave_init
+ * -# Enable the SPI module.
+ *     \snippet qs_spi_dma_use.c spi_master_enable
+ *     \snippet qs_spi_dma_use.c spi_slave_enable
+ *
+ * -# Create the DMA resource configuration structure, which can be filled out to
+ *    adjust the configuration of a single DMA transfer.
+ *    \snippet qs_spi_dma_use.c dma_tx_setup_1
+ *    \snippet qs_spi_dma_use.c dma_rx_setup_1
+ *
+ * -# Initialize the DMA resource configuration struct with the module's
+ *    default values.
+ *    \snippet qs_spi_dma_use.c dma_tx_setup_2
+ *    \snippet qs_spi_dma_use.c dma_rx_setup_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set extra configurations for the DMA resource. It is using peripheral
+ *    trigger. SERCOM TX empty and RX complete trigger causes a beat transfer in
+ *    this example.
+ *    \snippet qs_spi_dma_use.c dma_tx_setup_3
+ *    \snippet qs_spi_dma_use.c dma_rx_setup_3
+ *
+ * -# Allocate a DMA resource with the configurations.
+ *    \snippet qs_spi_dma_use.c dma_tx_setup_4
+ *    \snippet qs_spi_dma_use.c dma_rx_setup_4
+ *
+ * -# Create a DMA transfer descriptor configuration structure, which can be
+ *    filled out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_spi_dma_use.c dma_tx_setup_5
+ *    \snippet qs_spi_dma_use.c dma_rx_setup_5
+ *
+ * -# Initialize the DMA transfer descriptor configuration struct with the module's
+ *    default values.
+ *    \snippet qs_spi_dma_use.c dma_tx_setup_6
+ *    \snippet qs_spi_dma_use.c dma_rx_setup_6
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set the specific parameters for a DMA transfer with transfer size, source
+ *    address, and destination address.
+ *    \snippet qs_spi_dma_use.c dma_tx_setup_7
+ *    \snippet qs_spi_dma_use.c dma_rx_setup_7
+ *
+ * -# Create the DMA transfer descriptor.
+ *    \snippet qs_spi_dma_use.c dma_tx_setup_8
+ *    \snippet qs_spi_dma_use.c dma_rx_setup_8
+ *
+ * \section asfdoc_sam0_spi_dma_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_spi_dma_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_spi_dma_use.c main
+ *
+ * \subsection asfdoc_sam0_spi_dma_use_case_main_flow Workflow
+ * -# Select the slave.
+ *    \snippet qs_spi_dma_use.c select_slave
+ *
+ * -# Start the transfer job.
+ *    \snippet qs_spi_dma_use.c main_1
+ *
+ * -# Wait for transfer done.
+ *    \snippet qs_spi_dma_use.c main_2
+ *
+ * -# Deselect the slave.
+ *    \snippet qs_spi_dma_use.c deselect_slave
+ *
+ * -# Enter endless loop.
+ *    \snippet qs_spi_dma_use.c endless_loop
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/spi/quick_start_master/qs_spi_master_basic.h

@@ -0,0 +1,126 @@
+/**
+ * \file
+ *
+ * \brief SAM SPI Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_spi_master_basic_use Quick Start Guide for SERCOM SPI Master - Polled
+ *
+ * In this use case, the SPI on extension header 1 of the Xplained Pro board
+ * will be configured with the following settings:
+ * - Master Mode enabled
+ * - MSB of the data is transmitted first
+ * - Transfer mode 0
+ * - SPI MUX Setting E (see \ref asfdoc_sam0_sercom_spi_mux_settings_master)
+ * - 8-bit character size
+ * - Not enabled in sleep mode
+ * - Baudrate 100000
+ * - GLCK generator 0
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_master_basic_use_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_spi_master_basic_use_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_sercom_spi_master_basic_use_setup_code Code
+ * The following must be added to the user application:
+ *
+ * A sample buffer to send via SPI.
+ * \snippet qs_spi_master_basic.c buffer
+ * Number of entries in the sample buffer.
+ * \snippet qs_spi_master_basic.c buf_length
+ * GPIO pin to use as Slave Select.
+ * \snippet qs_spi_master_basic.c slave_select_pin
+ * A globally available software device instance struct to store the SPI driver
+ * state while it is in use.
+ * \snippet qs_spi_master_basic.c dev_inst
+ * A globally available peripheral slave software device instance struct.
+ * \snippet qs_spi_master_basic.c slave_dev_inst
+ * A function for configuring the SPI.
+ * \snippet qs_spi_master_basic.c configure_spi
+ *
+ * Add to user application \c main().
+ * \snippet qs_spi_master_basic.c main_setup
+ *
+ * \section asfdoc_sam0_sercom_spi_master_basic_use_workflow Workflow
+ * -# Initialize system.
+ *    \snippet qs_spi_master_basic.c system_init
+ * -# Set-up the SPI.
+ *    \snippet qs_spi_master_basic.c run_config
+ *   -# Create configuration struct.
+ *      \snippet qs_spi_master_basic.c config
+ *   -# Create peripheral slave configuration struct.
+ *      \snippet qs_spi_master_basic.c slave_config
+ *   -# Create peripheral slave software device instance struct.
+ *      \snippet qs_spi_master_basic.c slave_dev_inst
+ *   -# Get default peripheral slave configuration.
+ *      \snippet qs_spi_master_basic.c slave_conf_defaults
+ *   -# Set Slave Select pin.
+ *      \snippet qs_spi_master_basic.c ss_pin
+ *   -# Initialize peripheral slave software instance with configuration.
+ *      \snippet qs_spi_master_basic.c slave_init
+ *   -# Get default configuration to edit.
+ *      \snippet qs_spi_master_basic.c conf_defaults
+ *   -# Set MUX setting E.
+ *      \snippet qs_spi_master_basic.c mux_setting
+ *   -# Set pinmux for pad 0 (data in (MISO)).
+ *      \snippet qs_spi_master_basic.c di
+ *   -# Set pinmux for pad 1 as unused, so the pin can be used for other purposes.
+ *      \snippet qs_spi_master_basic.c ss
+ *   -# Set pinmux for pad 2 (data out (MOSI)).
+ *      \snippet qs_spi_master_basic.c do
+ *   -# Set pinmux for pad 3 (SCK).
+ *      \snippet qs_spi_master_basic.c sck
+ *   -# Initialize SPI module with configuration.
+ *      \snippet qs_spi_master_basic.c init
+ *   -# Enable SPI module.
+ *      \snippet qs_spi_master_basic.c enable
+ *
+ * \section asfdoc_sam0_sercom_spi_master_basic_use_case Use Case
+ * \subsection asfdoc_sam0_sercom_spi_master_basic_use_case_code Code
+ * Add the following to your user application \c main().
+ * \snippet qs_spi_master_basic.c main_use_case
+ * \subsection asfdoc_sam0_sercom_spi_master_basic_use_case_workflow Workflow
+ * -# Select slave.
+ *    \snippet qs_spi_master_basic.c select_slave
+ * -# Write buffer to SPI slave.
+ *    \snippet qs_spi_master_basic.c write
+ * -# Deselect slave.
+ *    \snippet qs_spi_master_basic.c deselect_slave
+ * -# Light up.
+ *    \snippet qs_spi_master_basic.c light_up
+ * -# Infinite loop.
+ *    \snippet qs_spi_master_basic.c inf_loop
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/spi/quick_start_slave/qs_spi_slave_basic.h

@@ -0,0 +1,116 @@
+/**
+ * \file
+ *
+ * \brief SAM SPI Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_spi_slave_basic_use Quick Start Guide for SERCOM SPI Slave - Polled
+ *
+ * In this use case, the SPI on extension header 1 of the Xplained Pro board
+ * will configured with the following settings:
+ * - Slave mode enabled
+ * - Preloading of shift register enabled
+ * - MSB of the data is transmitted first
+ * - Transfer mode 0
+ * - SPI MUX Setting E (see \ref asfdoc_sam0_sercom_spi_mux_settings_slave)
+ * - 8-bit character size
+ * - Not enabled in sleep mode
+ * - GLCK generator 0
+ *
+ *
+ * \section asfdoc_sam0_sercom_spi_slave_basic_use_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_spi_slave_basic_use_prereq Prerequisites
+ * The device must be connected to an SPI master which must read from the device.
+ *
+ * \subsection asfdoc_sam0_sercom_spi_slave_basic_use_setup_code Code
+ * The following must be added to the user application source file, outside
+ * any functions:
+ *
+ * A sample buffer to send via SPI.
+ * \snippet qs_spi_slave_basic.c buffer
+ * Number of entries in the sample buffer.
+ * \snippet qs_spi_slave_basic.c buf_length
+ * A globally available software device instance struct to store the SPI driver
+ * state while it is in use.
+ * \snippet qs_spi_slave_basic.c dev_inst
+ * A function for configuring the SPI.
+ * \snippet qs_spi_slave_basic.c configure_spi
+ *
+ * Add to user application \c main().
+ * \snippet qs_spi_slave_basic.c main_start
+ *
+ * \subsection asfdoc_sam0_sercom_spi_slave_basic_use_workflow Workflow
+ * -# Initialize system.
+ *    \snippet qs_spi_slave_basic.c system_init
+ * -# Set-up the SPI.
+ *    \snippet qs_spi_slave_basic.c run_config
+ *   -# Create configuration struct.
+ *      \snippet qs_spi_slave_basic.c config
+ *   -# Get default configuration to edit.
+ *      \snippet qs_spi_slave_basic.c conf_defaults
+ *   -# Set the SPI in slave mode.
+ *      \snippet qs_spi_slave_basic.c conf_spi_slave_instance
+ *   -# Enable preloading of shift register.
+ *      \snippet qs_spi_slave_basic.c conf_preload
+ *   -# Set frame format to SPI frame.
+ *      \snippet qs_spi_slave_basic.c conf_format
+ *   -# Set MUX setting E.
+ *      \snippet qs_spi_slave_basic.c mux_setting
+ *   -# Set pinmux for pad 0 (data in MOSI).
+ *      \snippet qs_spi_slave_basic.c di
+ *   -# Set pinmux for pad 1 (slave select).
+ *      \snippet qs_spi_slave_basic.c ss
+ *   -# Set pinmux for pad 2 (data out MISO).
+ *      \snippet qs_spi_slave_basic.c do
+ *   -# Set pinmux for pad 3 (SCK).
+ *      \snippet qs_spi_slave_basic.c sck
+ *   -# Initialize SPI module with configuration.
+ *      \snippet qs_spi_slave_basic.c init
+ *   -# Enable SPI module.
+ *      \snippet qs_spi_slave_basic.c enable
+ *
+ * \section asfdoc_sam0_sercom_spi_slave_basic_use_case Use Case
+ * \subsection asfdoc_sam0_sercom_spi_slave_basic_use_case_code Code
+ * Add the following to your user application \c main().
+ * \snippet qs_spi_slave_basic.c main_use_case
+ * \subsection asfdoc_sam0_sercom_spi_slave_basic_use_case_workflow Workflow
+ * -# Read data from SPI master.
+ *    \snippet qs_spi_slave_basic.c read
+ * -# Compare the received data with the transmitted data from SPI master.
+ *    \snippet qs_spi_slave_basic.c compare
+ * -# Infinite loop. If the data is matched, LED0 will flash slowly. Otherwise, 
+ *    LED will flash quickly.
+ *    \snippet qs_spi_slave_basic.c inf_loop
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/usart/quick_start/qs_usart_basic_use.h

@@ -0,0 +1,106 @@
+/**
+ * \file
+ *
+ * \brief SAM USART Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_basic_use_case Quick Start Guide for SERCOM USART - Basic
+ *
+ * This quick start will echo back characters typed into the terminal. In this
+ * use case the USART will be configured with the following settings:
+ * - Asynchronous mode
+ * - 9600 Baudrate
+ * - 8-bits, No Parity and one Stop Bit
+ * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
+ *
+ * \section asfdoc_sam0_sercom_usart_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_basic_use_case_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_usart_basic_use.c module_inst
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_usart_basic_use.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_usart_basic_use.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_setup_flow Workflow
+ * -# Create a module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_usart_basic_use.c module_inst
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Configure the USART module.
+ *  -# Create a USART module configuration struct, which can be filled out to
+ *     adjust the configuration of a physical USART peripheral.
+ *     \snippet qs_usart_basic_use.c setup_config
+ *  -# Initialize the USART configuration struct with the module's default values.
+ *     \snippet qs_usart_basic_use.c setup_config_defaults
+ *     \note This should always be performed before using the configuration
+ *           struct to ensure that all values are initialized to known default
+ *           settings.
+ *
+ *  -# Alter the USART settings to configure the physical pinout, baudrate, and
+ *     other relevant parameters.
+ *     \snippet qs_usart_basic_use.c setup_change_config
+ *  -# Configure the USART module with the desired settings, retrying while the
+ *     driver is busy until the configuration is stressfully set.
+ *     \snippet qs_usart_basic_use.c setup_set_config
+ *  -# Enable the USART module.
+ *     \snippet qs_usart_basic_use.c setup_enable
+ *
+ *
+ * \section asfdoc_sam0_usart_basic_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_usart_basic_use.c main
+ *
+ * \subsection asfdoc_sam0_usart_basic_use_case_main_flow Workflow
+ * -# Send a string to the USART to show the demo is running, blocking until
+ *    all characters have been sent.
+ *    \snippet qs_usart_basic_use.c main_send_string
+ * -# Enter an infinite loop to continuously echo received values on the USART.
+ *    \snippet qs_usart_basic_use.c main_loop
+ * -# Perform a blocking read of the USART, storing the received character into
+ *    the previously declared temporary variable.
+ *    \snippet qs_usart_basic_use.c main_read
+ * -# Echo the received variable back to the USART via a blocking write.
+ *    \snippet qs_usart_basic_use.c main_write
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/usart/quick_start_callback/qs_usart_callback.h

@@ -0,0 +1,120 @@
+/**
+ * \file
+ *
+ * \brief SAM USART Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_callback_use_case Quick Start Guide for SERCOM USART - Callback
+ *
+ * This quick start will echo back characters typed into the terminal, using
+ * asynchronous TX and RX callbacks from the USART peripheral. In this use case
+ * the USART will be configured with the following settings:
+ * - Asynchronous mode
+ * - 9600 Baudrate
+ * - 8-bits, No Parity and one Stop Bit
+ * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
+ *
+ * \section asfdoc_sam0_sercom_usart_callback_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_callback_use_case_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_usart_callback.c module_inst
+ * \snippet qs_usart_callback.c rx_buffer_var
+ *
+ * Copy-paste the following callback function code to your user application:
+ * \snippet qs_usart_callback.c callback_funcs
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_usart_callback.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_usart_callback.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_setup_flow Workflow
+ * -# Create a module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_usart_callback.c module_inst
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Configure the USART module.
+ *  -# Create a USART module configuration struct, which can be filled out to
+ *     adjust the configuration of a physical USART peripheral.
+ *     \snippet qs_usart_callback.c setup_config
+ *  -# Initialize the USART configuration struct with the module's default values.
+ *     \snippet qs_usart_callback.c setup_config_defaults
+ *     \note This should always be performed before using the configuration
+ *           struct to ensure that all values are initialized to known default
+ *           settings.
+ *
+ *  -# Alter the USART settings to configure the physical pinout, baudrate, and
+ *     other relevant parameters.
+ *     \snippet qs_usart_callback.c setup_change_config
+ *  -# Configure the USART module with the desired settings, retrying while the
+ *     driver is busy until the configuration is stressfully set.
+ *     \snippet qs_usart_callback.c setup_set_config
+ *  -# Enable the USART module.
+ *     \snippet qs_usart_callback.c setup_enable
+ * -# Configure the USART callbacks.
+ *  -# Register the TX and RX callback functions with the driver.
+ *     \snippet qs_usart_callback.c setup_register_callbacks
+ *  -# Enable the TX and RX callbacks so that they will be called by the driver
+ *     when appropriate.
+ *     \snippet qs_usart_callback.c setup_enable_callbacks
+ *
+ * \section asfdoc_sam0_usart_callback_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_usart_callback.c main
+ *
+ * \subsection asfdoc_sam0_usart_callback_use_case_main_flow Workflow
+ * -# Enable global interrupts, so that the callbacks can be fired.
+ *    \snippet qs_usart_callback.c enable_global_interrupts
+ * -# Send a string to the USART to show the demo is running, blocking until
+ *    all characters have been sent.
+ *    \snippet qs_usart_callback.c main_send_string
+ * -# Enter an infinite loop to continuously echo received values on the USART.
+ *    \snippet qs_usart_callback.c main_loop
+ * -# Perform an asynchronous read of the USART, which will fire the registered
+ *    callback when characters are received.
+ *    \snippet qs_usart_callback.c main_read
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <asf.h>
+#include <conf_clocks.h>
+

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/usart/quick_start_dma/qs_usart_dma_use.h

@@ -0,0 +1,208 @@
+/**
+ * \file
+ *
+ * \brief SAM Quick Start Guide for Using Usart driver with DMA
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_dma_use_case Quick Start Guide for Using DMA with SERCOM USART
+ *
+ * The supported board list:
+ *    - SAM D21 Xplained Pro
+ *    - SAM R21 Xplained Pro
+ *    - SAM D11 Xplained Pro
+ *    - SAM DA1 Xplained Pro
+ *    - SAM HA1G16A Xplained Pro
+ *    - SAM L21 Xplained Pro
+ *    - SAM L22 Xplained Pro
+ *    - SAM C21 Xplained Pro
+ *
+ * This quick start will receive eight bytes of data from the PC terminal and transmit back the string
+ * to the terminal through DMA. In this use case the USART will be configured with the following
+ * settings:
+ * - Asynchronous mode
+ * - 9600 Baudrate
+ * - 8-bits, No Parity and one Stop Bit
+ * - TX and RX enabled and connected to the Xplained Pro Embedded Debugger virtual COM port
+ *
+ * \section asfdoc_sam0_sercom_usart_dma_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_dma_use_case_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_usart_dma_use.c module_inst
+ * \snippet qs_usart_dma_use.c dma_resource
+ * \snippet qs_usart_dma_use.c usart_buffer
+ * \snippet qs_usart_dma_use.c transfer_descriptor
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_usart_dma_use.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_usart_dma_use.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_setup_flow Workflow
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_inst Create variables
+ * -# Create a module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_usart_dma_use.c module_inst
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Create module software instance structures for DMA resources to store
+ *    the DMA resource state while it is in use.
+ *    \snippet qs_usart_dma_use.c dma_resource
+ *    \note This should never go out of scope as long as the module is in use.
+ *          In most cases, this should be global.
+ *
+ * -# Create a buffer to store the data to be transferred /received.
+ *    \snippet qs_usart_dma_use.c usart_buffer
+ * -# Create DMA transfer descriptors for RX/TX.
+ *    \snippet qs_usart_dma_use.c transfer_descriptor
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_usart Configure the USART
+ * -# Create a USART module configuration struct, which can be filled out to
+ *    adjust the configuration of a physical USART peripheral.
+ *    \snippet qs_usart_dma_use.c setup_config
+ * -# Initialize the USART configuration struct with the module's default values.
+ *    \snippet qs_usart_dma_use.c setup_config_defaults
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Alter the USART settings to configure the physical pinout, baudrate, and
+ *    other relevant parameters.
+ *    \snippet qs_usart_dma_use.c setup_change_config
+ * -# Configure the USART module with the desired settings, retrying while the
+ *    driver is busy until the configuration is stressfully set.
+ *    \snippet qs_usart_dma_use.c setup_set_config
+ * -# Enable the USART module.
+ *    \snippet qs_usart_dma_use.c setup_enable
+ *
+ * \subsubsection asfdoc_sam0_usart_dma_use_case_setup_flow_dma Configure DMA
+ * -# Create a callback function of receiver done.
+ *    \snippet qs_usart_dma_use.c transfer_done_rx
+ *
+ * -# Create a callback function of transmission done.
+ *    \snippet qs_usart_dma_use.c transfer_done_tx
+ *
+ * -# Create a DMA resource configuration structure, which can be filled out to
+ *    adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_rx_1
+ *
+ * -# Initialize the DMA resource configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_rx_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set extra configurations for the DMA resource. It is using peripheral
+ *    trigger. SERCOM TX empty trigger causes a beat transfer in
+ *    this example.
+ *    \snippet qs_usart_dma_use.c setup_rx_3
+ *
+ * -# Allocate a DMA resource with the configurations.
+ *    \snippet qs_usart_dma_use.c setup_rx_4
+ *
+ * -# Create a DMA transfer descriptor configuration structure, which can be
+ *    filled out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_rx_5
+ *
+ * -# Initialize the DMA transfer descriptor configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_rx_6
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set the specific parameters for a DMA transfer with transfer size, source
+ *    address, and destination address.
+ *    \snippet qs_usart_dma_use.c setup_rx_7
+ *
+ * -# Create the DMA transfer descriptor.
+ *    \snippet qs_usart_dma_use.c setup_rx_8
+ *
+ * -# Create a DMA resource configuration structure for TX, which can be filled
+ *    out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_tx_1
+ *
+ * -# Initialize the DMA resource configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_tx_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set extra configurations for the DMA resource. It is using peripheral
+ *    trigger. SERCOM RX Ready trigger causes a beat transfer in
+ *    this example.
+ *    \snippet qs_usart_dma_use.c setup_tx_3
+ *
+ * -# Allocate a DMA resource with the configurations.
+ *    \snippet qs_usart_dma_use.c setup_tx_4
+ *
+ * -# Create a DMA transfer descriptor configuration structure, which can be
+ *    filled out to adjust the configuration of a single DMA transfer.
+ *    \snippet qs_usart_dma_use.c setup_tx_5
+ *
+ * -# Initialize the DMA transfer descriptor configuration struct with the module's
+ *    default values.
+ *    \snippet qs_usart_dma_use.c setup_tx_6
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Set the specific parameters for a DMA transfer with transfer size, source
+ *    address, and destination address.
+ *    \snippet qs_usart_dma_use.c setup_tx_7
+ *
+ * -# Create the DMA transfer descriptor.
+ *    \snippet qs_usart_dma_use.c setup_tx_8
+ *
+ * \section asfdoc_sam0_usart_dma_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_usart_dma_use.c main
+ *
+ * \subsection asfdoc_sam0_usart_dma_use_case_main_flow Workflow
+ * -# Wait for receiving data.
+ *    \snippet qs_usart_dma_use.c main_1
+ *
+ * -# Enter endless loop.
+ *    \snippet qs_usart_dma_use.c endless_loop
+ */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/usart/quick_start_lin/qs_lin.h

@@ -0,0 +1,94 @@
+/**
+ * \file
+ *
+ * \brief SAM USART LIN Quick Start
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_sercom_usart_lin_use_case Quick Start Guide for SERCOM USART LIN
+ *
+ * The supported board list:
+ *    - SAMC21 Xplained Pro
+ *
+ * This quick start will set up LIN frame format transmission according to your
+ * configuration \c CONF_LIN_NODE_TYPE.
+ * For LIN master, it will send LIN command after startup.
+ * For LIN salve, once received a format from LIN master with ID \c LIN_ID_FIELD_VALUE,
+ * it will reply four data bytes plus a checksum.
+ *
+ * \section asfdoc_sam0_sercom_usart_lin_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_sercom_usart_lin_use_case_prereq Prerequisites
+ * When verify data transmission between LIN master and slave, two boards are needed:
+ * one is for LIN master and the other is for LIN slave.
+ * connect LIN master LIN PIN with LIN slave LIN PIN.
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_setup_code Code
+ * Add to the main application source file, outside of any functions:
+ * \snippet qs_lin.c module_var
+ *
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_lin.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_lin.c setup_init
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_setup_flow Workflow
+ * -# Create USART CDC and LIN module software instance structure for the USART module to store
+ *    the USART driver state while it is in use.
+ *    \snippet qs_lin.c module_inst
+ * -# Define LIN ID field for header format.
+ *    \snippet qs_lin.c lin_id
+ *    \note The ID \c LIN_ID_FIELD_VALUE is eight bits as [P1,P0,ID5...ID0], when it's 0x64, the
+ * 		data field length is four bytes plus a checksum byte.
+ *
+ * -# Define LIN RX/TX buffer.
+ *    \snippet qs_lin.c lin_buffer
+ *    \note For \c tx_buffer and \c rx_buffer, the last byte is for checksum.
+ *
+ * -# Configure the USART CDC for output message.
+ *     \snippet qs_lin.c CDC_setup
+ *
+ * -# Configure the USART LIN module.
+ *     \snippet qs_lin.c lin_setup
+ *    \note The LIN frame format can be configured as master or slave, refer to \c CONF_LIN_NODE_TYPE .
+ *
+ * \section asfdoc_sam0_usart_lin_use_case_main Use Case
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_main_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_lin.c main_setup
+ *
+ * \subsection asfdoc_sam0_usart_lin_use_case_main_flow Workflow
+ * -# Set up USART LIN module.
+ *     \snippet qs_lin.c configure_lin
+ * -# For LIN master, sending LIN command. For LIN slaver, start reading data .
+ *     \snippet qs_lin.c lin_master_cmd
+ */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/usart/usart.c

@@ -0,0 +1,806 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Driver
+ *
+ * Copyright (c) 2012-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "usart.h"
+#include <pinmux.h>
+#if USART_CALLBACK_MODE == true
+#  include "usart_interrupt.h"
+#endif
+
+/**
+ * \internal
+ * Set Configuration of the USART module
+ */
+static enum status_code _usart_set_config(
+		struct usart_module *const module,
+		const struct usart_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Index for generic clock */
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t gclk_index;
+
+#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35) || (SAMC21) || (WLR089)
+	if (sercom_index == 5) {
+		gclk_index   = SERCOM5_GCLK_ID_CORE;
+	} else {
+		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	}
+#else
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+
+	/* Cache new register values to minimize the number of register writes */
+	uint32_t ctrla = 0;
+	uint32_t ctrlb = 0;
+#ifdef FEATURE_USART_ISO7816
+	uint32_t ctrlc = 0;
+#endif
+	uint16_t baud  = 0;
+	uint32_t transfer_mode;
+
+	enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+	enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+
+#ifdef FEATURE_USART_OVER_SAMPLE
+	switch (config->sample_rate) {
+		case USART_SAMPLE_RATE_16X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+			break;
+		case USART_SAMPLE_RATE_8X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+			break;
+		case USART_SAMPLE_RATE_3X_ARITHMETIC:
+			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
+			break;
+		case USART_SAMPLE_RATE_16X_FRACTIONAL:
+			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+			break;
+		case USART_SAMPLE_RATE_8X_FRACTIONAL:
+			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+			break;
+	}
+#endif
+
+	/* Set data order, internal muxing, and clock polarity */
+	ctrla = (uint32_t)config->data_order |
+		(uint32_t)config->mux_setting |
+	#ifdef FEATURE_USART_OVER_SAMPLE
+		config->sample_adjustment |
+		config->sample_rate |
+	#endif
+	#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
+	#endif
+		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
+
+	enum status_code status_code = STATUS_OK;
+
+	transfer_mode = (uint32_t)config->transfer_mode;
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		transfer_mode = config->iso7816_config.protocol_t;
+	}
+#endif
+	/* Get baud value from mode and clock */
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		baud = config->baudrate;
+	} else {
+#endif
+	switch (transfer_mode)
+	{
+		case USART_TRANSFER_SYNCHRONOUSLY:
+			if (!config->use_external_clock) {
+				status_code = _sercom_get_sync_baud_val(config->baudrate,
+						system_gclk_chan_get_hz(gclk_index), &baud);
+			}
+
+			break;
+
+		case USART_TRANSFER_ASYNCHRONOUSLY:
+			if (config->use_external_clock) {
+				status_code =
+						_sercom_get_async_baud_val(config->baudrate,
+							config->ext_clock_freq, &baud, mode, sample_num);
+			} else {
+				status_code =
+						_sercom_get_async_baud_val(config->baudrate,
+							system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
+			}
+
+			break;
+	}
+
+	/* Check if calculating the baudrate failed */
+	if (status_code != STATUS_OK) {
+		/* Abort */
+		return status_code;
+	}
+#ifdef FEATURE_USART_ISO7816
+	}
+#endif
+
+#ifdef FEATURE_USART_IRDA
+	if(config->encoding_format_enable) {
+		usart_hw->RXPL.reg = config->receive_pulse_length;
+	}
+#endif
+
+	/*Set baud val */
+	usart_hw->BAUD.reg = baud;
+
+	/* Set sample mode */
+	ctrla |= transfer_mode;
+
+	if (config->use_external_clock == false) {
+		ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
+	}
+	else {
+		ctrla |= SERCOM_USART_CTRLA_MODE(0x0);
+	}
+
+	/* Set stopbits and enable transceivers */
+	ctrlb =  
+		#ifdef FEATURE_USART_IRDA
+			(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
+		#endif
+		#ifdef FEATURE_USART_START_FRAME_DECTION
+			(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
+		#endif
+		#ifdef FEATURE_USART_COLLISION_DECTION
+			(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
+		#endif
+			(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
+			(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
+
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		ctrla |= SERCOM_USART_CTRLA_FORM(0x07);
+		if (config->iso7816_config.enable_inverse) {
+			ctrla |= SERCOM_USART_CTRLA_TXINV | SERCOM_USART_CTRLA_RXINV;
+		}
+		ctrlb |=  USART_CHARACTER_SIZE_8BIT;
+		
+		switch(config->iso7816_config.protocol_t) {
+			case ISO7816_PROTOCOL_T_0:
+				ctrlb |= (uint32_t)config->stopbits;	
+				ctrlc |= SERCOM_USART_CTRLC_GTIME(config->iso7816_config.guard_time) | \
+						(config->iso7816_config.inhibit_nack) | \
+						(config->iso7816_config.successive_recv_nack) | \
+						SERCOM_USART_CTRLC_MAXITER(config->iso7816_config.max_iterations);
+				break;	
+			case ISO7816_PROTOCOL_T_1:
+				ctrlb |= USART_STOPBITS_1;
+				break;		
+		}
+	} else {
+#endif
+	ctrlb |= (uint32_t)config->stopbits;
+	ctrlb |= (uint32_t)config->character_size;
+	/* Check parity mode bits */
+	if (config->parity != USART_PARITY_NONE) {
+		ctrla |= SERCOM_USART_CTRLA_FORM(1);
+		ctrlb |= config->parity;
+	} else {
+#ifdef FEATURE_USART_LIN_SLAVE
+		if(config->lin_slave_enable) {
+			ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
+		} else {
+			ctrla |= SERCOM_USART_CTRLA_FORM(0);
+		}
+#else
+		ctrla |= SERCOM_USART_CTRLA_FORM(0);
+#endif
+	}
+#ifdef FEATURE_USART_ISO7816
+	}
+#endif
+
+#ifdef FEATURE_USART_LIN_MASTER
+	usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk)
+						| config->lin_header_delay
+						| config->lin_break_length;
+
+	if (config->lin_node != LIN_INVALID_MODE) {
+		ctrla &= ~(SERCOM_USART_CTRLA_FORM(0xf));
+		ctrla |= config->lin_node;
+	}
+#endif
+
+	/* Set whether module should run in standby. */
+	if (config->run_in_standby || system_is_debugger_present()) {
+		ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
+	}
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Write configuration to CTRLB */
+	usart_hw->CTRLB.reg = ctrlb;
+
+	/* Wait until synchronization is complete */
+	_usart_wait_for_sync(module);
+
+	/* Write configuration to CTRLA */
+	usart_hw->CTRLA.reg = ctrla;
+
+#ifdef FEATURE_USART_RS485
+	if ((usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_FORM_Msk) != \
+		SERCOM_USART_CTRLA_FORM(0x07)) {
+		usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7));
+		usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time);
+	}
+#endif
+
+#ifdef FEATURE_USART_ISO7816
+	if(config->iso7816_config.enabled) {
+		_usart_wait_for_sync(module);
+		usart_hw->CTRLC.reg = ctrlc;
+	}
+#endif
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Initializes the device
+ *
+ * Initializes the USART device based on the setting specified in the
+ * configuration struct.
+ *
+ * \param[out] module  Pointer to USART device
+ * \param[in]  hw      Pointer to USART hardware instance
+ * \param[in]  config  Pointer to configuration struct
+ *
+ * \return Status of the initialization.
+ *
+ * \retval STATUS_OK                       The initialization was successful
+ * \retval STATUS_BUSY                     The USART module is busy
+ *                                         resetting
+ * \retval STATUS_ERR_DENIED               The USART has not been disabled in
+ *                                         advance of initialization
+ * \retval STATUS_ERR_INVALID_ARG          The configuration struct contains
+ *                                         invalid configuration
+ * \retval STATUS_ERR_ALREADY_INITIALIZED  The SERCOM instance has already been
+ *                                         initialized with different clock
+ *                                         configuration
+ * \retval STATUS_ERR_BAUD_UNAVAILABLE     The BAUD rate given by the
+ *                                         configuration
+ *                                         struct cannot be reached with
+ *                                         the current clock configuration
+ */
+enum status_code usart_init(
+		struct usart_module *const module,
+		Sercom *const hw,
+		const struct usart_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(hw);
+	Assert(config);
+
+	enum status_code status_code = STATUS_OK;
+
+	/* Assign module pointer to software instance struct */
+	module->hw = hw;
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+	uint32_t pm_index, gclk_index; 
+#if (SAML22) || (SAMC20) 
+	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
+#elif (SAML21) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	if (sercom_index == 5) {
+		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
+		gclk_index   = SERCOM5_GCLK_ID_CORE;
+	} else {
+		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+	}
+#elif (SAMC21)
+	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+	
+	if (sercom_index == 5){
+		gclk_index	= SERCOM5_GCLK_ID_CORE;
+    } else {
+    	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
+    }
+#else
+	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+#endif
+
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
+		/* The module is busy resetting itself */
+		return STATUS_BUSY;
+	}
+
+	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
+		/* Check the module is enabled */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Turn on module in PM */
+#if (SAML21) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	if (sercom_index == 5) {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+	} else {
+		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);	
+	}
+#else
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+#endif
+
+	/* Set up the GCLK for the module */
+	struct system_gclk_chan_config gclk_chan_conf;
+	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+	gclk_chan_conf.source_generator = config->generator_source;
+	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+	system_gclk_chan_enable(gclk_index);
+	sercom_set_gclk_generator(config->generator_source, false);
+
+	/* Set character size */
+	module->character_size = config->character_size;
+
+	/* Set transmitter and receiver status */
+	module->receiver_enabled = config->receiver_enable;
+	module->transmitter_enabled = config->transmitter_enable;
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	module->lin_slave_enabled = config->lin_slave_enable;
+#endif
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	module->start_frame_detection_enabled = config->start_frame_detection_enable;
+#endif
+#ifdef FEATURE_USART_ISO7816
+	module->iso7816_mode_enabled = config->iso7816_config.enabled;
+#endif
+	/* Set configuration according to the config struct */
+	status_code = _usart_set_config(module, config);
+	if(status_code != STATUS_OK) {
+		return status_code;
+	}
+
+	struct system_pinmux_config pin_conf;
+	system_pinmux_get_config_defaults(&pin_conf);
+	pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+	uint32_t pad_pinmuxes[] = {
+			config->pinmux_pad0, config->pinmux_pad1,
+			config->pinmux_pad2, config->pinmux_pad3
+		};
+
+	/* Configure the SERCOM pins according to the user configuration */
+	for (uint8_t pad = 0; pad < 4; pad++) {
+		uint32_t current_pinmux = pad_pinmuxes[pad];
+
+		if (current_pinmux == PINMUX_DEFAULT) {
+			current_pinmux = _sercom_get_default_pad(hw, pad);
+		}
+
+		if (current_pinmux != PINMUX_UNUSED) {
+			pin_conf.mux_position = current_pinmux & 0xFFFF;
+			system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+		}
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Initialize parameters */
+	for (uint32_t i = 0; i < USART_CALLBACK_N; i++) {
+		module->callback[i]            = NULL;
+	}
+
+	module->tx_buffer_ptr              = NULL;
+	module->rx_buffer_ptr              = NULL;
+	module->remaining_tx_buffer_length = 0x0000;
+	module->remaining_rx_buffer_length = 0x0000;
+	module->callback_reg_mask          = 0x00;
+	module->callback_enable_mask       = 0x00;
+	module->rx_status                  = STATUS_OK;
+	module->tx_status                  = STATUS_OK;
+
+	/* Set interrupt handler and register USART software module struct in
+	 * look-up table */
+	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+	_sercom_set_handler(instance_index, _usart_interrupt_handler);
+	_sercom_instances[instance_index] = module;
+#endif
+
+	return status_code;
+}
+
+/**
+ * \brief Transmit a character via the USART
+ *
+ * This blocking function will transmit a single character via the
+ * USART.
+ *
+ * \param[in]  module   Pointer to the software instance struct
+ * \param[in]  tx_data  Data to transfer
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK         If the operation was completed
+ * \retval STATUS_BUSY       If the operation was not completed, due to the USART
+ *                           module being busy
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_wait(
+		struct usart_module *const module,
+		const uint16_t tx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Check if the USART is busy doing asynchronous operation. */
+	if (module->remaining_tx_buffer_length > 0) {
+		return STATUS_BUSY;
+	}
+
+#else
+	/* Check if USART is ready for new data */
+	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
+		/* Return error code */
+		return STATUS_BUSY;
+	}
+#endif
+
+	/* Write data to USART module */
+	usart_hw->DATA.reg = tx_data;
+
+	while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
+		/* Wait until data is sent */
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Receive a character via the USART
+ *
+ * This blocking function will receive a character via the USART.
+ *
+ * \param[in]   module   Pointer to the software instance struct
+ * \param[out]  rx_data  Pointer to received data
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK                If the operation was completed
+ * \retval STATUS_BUSY              If the operation was not completed,
+ *                                  due to the USART module being busy
+ * \retval STATUS_ERR_BAD_FORMAT    If the operation was not completed,
+ *                                  due to configuration mismatch between USART
+ *                                  and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW  If the operation was not completed,
+ *                                  due to the baudrate being too low or the
+ *                                  system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA      If the operation was not completed, due to
+ *                                  data being corrupted
+ * \retval STATUS_ERR_DENIED        If the receiver is not enabled
+ */
+enum status_code usart_read_wait(
+		struct usart_module *const module,
+		uint16_t *const rx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Error variable */
+	uint8_t error_code;
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+#if USART_CALLBACK_MODE == true
+	/* Check if the USART is busy doing asynchronous operation. */
+	if (module->remaining_rx_buffer_length > 0) {
+		return STATUS_BUSY;
+	}
+#endif
+
+	/* Check if USART has new data */
+	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
+		/* Return error code */
+		return STATUS_BUSY;
+	}
+
+	/* Read out the status code and mask away all but the 3 LSBs*/
+	error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+
+	/* Check if an error has occurred during the receiving */
+	if (error_code) {
+		/* Check which error occurred */
+		if (error_code & SERCOM_USART_STATUS_FERR) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+
+			return STATUS_ERR_BAD_FORMAT;
+		} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+
+			return STATUS_ERR_OVERFLOW;
+		} else if (error_code & SERCOM_USART_STATUS_PERR) {
+			/* Clear flag by writing a 1 to it and
+			 * return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+
+			return STATUS_ERR_BAD_DATA;
+		}
+#ifdef FEATURE_USART_LIN_SLAVE
+		else if (error_code & SERCOM_USART_STATUS_ISF) {
+			/* Clear flag by writing 1 to it  and
+			 *  return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+
+			return STATUS_ERR_PROTOCOL;
+		}
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+		else if (error_code & SERCOM_USART_STATUS_COLL) {
+			/* Clear flag by writing 1 to it
+			 *  return with an error code */
+			usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+
+			return STATUS_ERR_PACKET_COLLISION;
+		}
+#endif
+	}
+
+	/* Read data from USART module */
+	*rx_data = usart_hw->DATA.reg;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Transmit a buffer of characters via the USART
+ *
+ * This blocking function will transmit a block of \c length characters
+ * via the USART.
+ *
+ * \note Using this function in combination with the interrupt (\c _job) functions is
+ *       not recommended as it has no functionality to check if there is an
+ *       ongoing interrupt driven operation running or not.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer to data to transmit
+ * \param[in]  length   Number of characters to transmit
+ *
+ * \note If using 9-bit data, the array that *tx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define TX_LEN 3
+          uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
+          usart_write_buffer_wait(&module, (uint8_t*)tx_buf, TX_LEN);
+    \endcode
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK              If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_TIMEOUT     If operation was not completed, due to USART
+ *                                module timing out
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_write_buffer_wait(
+		struct usart_module *const module,
+		const uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Check if the buffer length is valid */
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	uint16_t tx_pos = 0;
+
+	/* Blocks while buffer is being transferred */
+	while (length--) {
+		/* Wait for the USART to be ready for new data and abort
+		* operation if it doesn't get ready within the timeout*/
+		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) {
+				break;
+			} else if (i == USART_TIMEOUT) {
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+
+		/* Data to send is at least 8 bits long */
+		uint16_t data_to_send = tx_data[tx_pos++];
+
+		/* Check if the character size exceeds 8 bit */
+		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+			data_to_send |= (tx_data[tx_pos++] << 8);
+		}
+
+		/* Send the data through the USART module */
+		usart_write_wait(module, data_to_send);
+	}
+
+	/* Wait until Transmit is complete or timeout */
+	for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+		if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {
+			break;
+		} else if (i == USART_TIMEOUT) {
+			return STATUS_ERR_TIMEOUT;
+		}
+	}
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Receive a buffer of \c length characters via the USART
+ *
+ * This blocking function will receive a block of \c length characters
+ * via the USART.
+ *
+ * \note Using this function in combination with the interrupt (\c *_job)
+ *       functions is not recommended as it has no functionality to check if
+ *       there is an ongoing interrupt driven operation running or not.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[out] rx_data  Pointer to receive buffer
+ * \param[in]  length   Number of characters to receive
+ *
+ * \note If using 9-bit data, the array that *rx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define RX_LEN 3
+          uint16_t rx_buf[RX_LEN] = {0x0,};
+          usart_read_buffer_wait(&module, (uint8_t*)rx_buf, RX_LEN);
+    \endcode
+ *
+ * \return Status of the operation.
+ * \retval STATUS_OK                If operation was completed
+ * \retval STATUS_ERR_INVALID_ARG   If operation was not completed, due to an
+ *                                  invalid argument being supplied
+ * \retval STATUS_ERR_TIMEOUT       If operation was not completed, due
+ *                                  to USART module timing out
+ * \retval STATUS_ERR_BAD_FORMAT    If the operation was not completed,
+ *                                  due to a configuration mismatch
+ *                                  between USART and the sender
+ * \retval STATUS_ERR_BAD_OVERFLOW  If the operation was not completed,
+ *                                  due to the baudrate being too low or the
+ *                                  system frequency being too high
+ * \retval STATUS_ERR_BAD_DATA      If the operation was not completed, due
+ *                                  to data being corrupted
+ * \retval STATUS_ERR_DENIED        If the receiver is not enabled
+ */
+enum status_code usart_read_buffer_wait(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Check if the buffer length is valid */
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	uint16_t rx_pos = 0;
+
+	/* Blocks while buffer is being received */
+	while (length--) {
+		/* Wait for the USART to have new data and abort operation if it
+		 * doesn't get ready within the timeout*/
+		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
+			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
+				break;
+			} else if (i == USART_TIMEOUT) {
+				return STATUS_ERR_TIMEOUT;
+			}
+		}
+
+		enum status_code retval;
+		uint16_t received_data = 0;
+
+		retval = usart_read_wait(module, &received_data);
+
+		if (retval != STATUS_OK) {
+			/* Overflow, abort */
+			return retval;
+		}
+
+		/* Read value will be at least 8-bits long */
+		rx_data[rx_pos++] = received_data;
+
+		/* If 9-bit data, write next received byte to the buffer */
+		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+			rx_data[rx_pos++] = (received_data >> 8);
+		}
+	}
+
+	return STATUS_OK;
+}

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.c

@@ -0,0 +1,656 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Asynchronous Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "usart_interrupt.h"
+
+/**
+ * \internal
+ * Asynchronous write of a buffer with a given length
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer to data to be transmitted
+ * \param[in]  length   Length of data buffer
+ *
+ */
+enum status_code _usart_write_buffer(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(tx_data);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if the USART transmitter is busy */
+	if (module->remaining_tx_buffer_length > 0) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Write parameters to the device instance */
+	module->remaining_tx_buffer_length = length;
+
+	system_interrupt_leave_critical_section();
+
+	module->tx_buffer_ptr              = tx_data;
+	module->tx_status                  = STATUS_BUSY;
+
+	/* Enable the Data Register Empty Interrupt */
+	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE;
+
+	return STATUS_OK;
+}
+
+/**
+ * \internal
+ * Asynchronous read of a buffer with a given length
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  rx_data  Pointer to data to be received
+ * \param[in]  length   Length of data buffer
+ *
+ */
+enum status_code _usart_read_buffer(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+	Assert(rx_data);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	system_interrupt_enter_critical_section();
+
+	/* Check if the USART receiver is busy */
+	if (module->remaining_rx_buffer_length > 0) {
+		system_interrupt_leave_critical_section();
+		return STATUS_BUSY;
+	}
+
+	/* Set length for the buffer and the pointer, and let
+	 * the interrupt handler do the rest */
+	module->remaining_rx_buffer_length = length;
+
+	system_interrupt_leave_critical_section();
+
+	module->rx_buffer_ptr              = rx_data;
+	module->rx_status                  = STATUS_BUSY;
+
+	/* Enable the RX Complete Interrupt */
+	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	/* Enable the break character is received Interrupt */
+	if(module->lin_slave_enabled) {
+		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK;
+	}
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	/* Enable a start condition is detected Interrupt */
+	if(module->start_frame_detection_enabled) {
+		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS;
+	}
+#endif
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Registers a callback
+ *
+ * Registers a callback function, which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref usart_enable_callback
+ *       in order for the interrupt handler to call it when the conditions for
+ *       the callback type are met.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_func  Pointer to callback function
+ * \param[in]  callback_type  Callback type given by an enum
+ *
+ */
+void usart_register_callback(
+		struct usart_module *const module,
+		usart_callback_t callback_func,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	module->callback_reg_mask |= (1 << callback_type);
+}
+
+/**
+ * \brief Unregisters a callback
+ *
+ * Unregisters a callback function, which is implemented by the user.
+ *
+ * \param[in,out]  module         Pointer to USART software instance struct
+ * \param[in]      callback_type  Callback type given by an enum
+ *
+ */
+void usart_unregister_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	module->callback_reg_mask &= ~(1 << callback_type);
+}
+
+/**
+ * \brief Asynchronous write a single char
+ *
+ * Sets up the driver to write the data given. If registered and enabled,
+ * a callback function will be called when the transmit is completed.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Data to transfer
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK         If operation was completed
+ * \retval STATUS_BUSY       If operation was not completed, due to the
+ *                           USART module being busy
+ * \retval STATUS_ERR_DENIED If the transmitter is not enabled
+ */
+enum status_code usart_write_job(
+		struct usart_module *const module,
+		const uint16_t *tx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(tx_data);
+
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Call internal write buffer function with length 1 */
+	return _usart_write_buffer(module, (uint8_t *)tx_data, 1);
+}
+
+/**
+ * \brief Asynchronous read a single char
+ *
+ * Sets up the driver to read data from the USART module to the data
+ * pointer given. If registered and enabled, a callback will be called
+ * when the receiving is completed.
+ *
+ * \param[in]   module   Pointer to USART software instance struct
+ * \param[out]  rx_data  Pointer to where received data should be put
+ *
+ * \returns Status of the operation.
+ * \retval  STATUS_OK    If operation was completed
+ * \retval  STATUS_BUSY  If operation was not completed
+ */
+enum status_code usart_read_job(
+		struct usart_module *const module,
+		uint16_t *const rx_data)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	/* Call internal read buffer function with length 1 */
+	return _usart_read_buffer(module, (uint8_t *)rx_data, 1);
+}
+
+/**
+ * \brief Asynchronous buffer write
+ *
+ * Sets up the driver to write a given buffer over the USART. If registered and
+ * enabled, a callback function will be called.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[in]  tx_data  Pointer do data buffer to transmit
+ * \param[in]  length   Length of the data to transmit
+ *
+ * \note If using 9-bit data, the array that *tx_data point to should be defined 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+          #define TX_LEN 3
+          uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133};
+          usart_write_buffer_job(&module, (uint8_t*)tx_buf, TX_LEN);
+    \endcode
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK              If operation was completed successfully.
+ * \retval STATUS_BUSY            If operation was not completed, due to the
+ *                                USART module being busy
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_write_buffer_job(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(tx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the transmitter is enabled */
+	if (!(module->transmitter_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Issue internal asynchronous write */
+	return _usart_write_buffer(module, tx_data, length);
+}
+
+/**
+ * \brief Asynchronous buffer read
+ *
+ * Sets up the driver to read from the USART to a given buffer. If registered
+ * and enabled, a callback function will be called.
+ *
+ * \param[in]  module   Pointer to USART software instance struct
+ * \param[out] rx_data  Pointer to data buffer to receive
+ * \param[in]  length   Data buffer length
+ *
+ * \note If using 9-bit data, the array that *rx_data point to should be defined
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       is an address pointer, the highest byte is not discarded. For example:
+ *   \code
+           #define RX_LEN 3
+           uint16_t rx_buf[RX_LEN] = {0x0,};
+           usart_read_buffer_job(&module, (uint8_t*)rx_buf, RX_LEN);
+    \endcode
+ *
+ * \returns Status of the operation.
+ * \retval STATUS_OK              If operation was completed
+ * \retval STATUS_BUSY            If operation was not completed, due to the
+ *                                USART module being busy
+ * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid
+ *                                arguments
+ * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
+ */
+enum status_code usart_read_buffer_job(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(rx_data);
+
+	if (length == 0) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Check that the receiver is enabled */
+	if (!(module->receiver_enabled)) {
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Issue internal asynchronous read */
+	return _usart_read_buffer(module, rx_data, length);
+}
+
+/**
+ * \brief Cancels ongoing read/write operation
+ *
+ * Cancels the ongoing read/write operation modifying parameters in the
+ * USART software struct.
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transfer type to cancel
+ */
+void usart_abort_job(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(module->hw);
+
+	/* Get a pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	switch(transceiver_type) {
+		case USART_TRANSCEIVER_RX:
+			/* Clear the interrupt flag in order to prevent the receive
+			 * complete callback to fire */
+			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+
+			/* Clear the software reception buffer */
+			module->remaining_rx_buffer_length = 0;
+
+			break;
+
+		case USART_TRANSCEIVER_TX:
+			/* Clear the interrupt flag in order to prevent the receive
+			 * complete callback to fire */
+			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+
+			/* Clear the software reception buffer */
+			module->remaining_tx_buffer_length = 0;
+
+			break;
+	}
+}
+
+/**
+ * \brief Get status from the ongoing or last asynchronous transfer operation
+ *
+ * Returns the error from a given ongoing or last asynchronous transfer operation.
+ * Either from a read or write transfer.
+ *
+ * \param[in]  module            Pointer to USART software instance struct
+ * \param[in]  transceiver_type  Transfer type to check
+  *
+ * \return Status of the given job.
+ * \retval STATUS_OK               No error occurred during the last transfer
+ * \retval STATUS_BUSY             A transfer is ongoing
+ * \retval STATUS_ERR_BAD_DATA     The last operation was aborted due to a
+ *                                 parity error. The transfer could be affected
+ *                                 by external noise
+ * \retval STATUS_ERR_BAD_FORMAT   The last operation was aborted due to a
+ *                                 frame error
+ * \retval STATUS_ERR_OVERFLOW     The last operation was aborted due to a
+ *                                 buffer overflow
+ * \retval STATUS_ERR_INVALID_ARG  An invalid transceiver enum given
+ */
+enum status_code usart_get_job_status(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Variable for status code */
+	enum status_code status_code;
+
+	switch(transceiver_type) {
+	case USART_TRANSCEIVER_RX:
+			status_code = module->rx_status;
+			break;
+
+	case USART_TRANSCEIVER_TX:
+			status_code = module->tx_status;
+			break;
+
+	default:
+			status_code = STATUS_ERR_INVALID_ARG;
+			break;
+	}
+
+	return status_code;
+}
+
+/**
+ * \internal
+ * Handles interrupts as they occur, and it will run callback functions
+ * which are registered and enabled.
+ *
+ * \param[in]  instance  ID of the SERCOM instance calling the interrupt
+ *                       handler.
+ */
+void _usart_interrupt_handler(
+		uint8_t instance)
+{
+	/* Temporary variables */
+	uint16_t interrupt_status;
+	uint16_t callback_status;
+	uint8_t error_code;
+
+
+	/* Get device instance from the look-up table */
+	struct usart_module *module
+		= (struct usart_module *)_sercom_instances[instance];
+
+	/* Pointer to the hardware module instance */
+	SercomUsart *const usart_hw
+		= &(module->hw->USART);
+
+	/* Wait for the synchronization to complete */
+	_usart_wait_for_sync(module);
+
+	/* Read and mask interrupt flag register */
+	interrupt_status = usart_hw->INTFLAG.reg;
+	interrupt_status &= usart_hw->INTENSET.reg;
+	callback_status = module->callback_reg_mask &
+			module->callback_enable_mask;
+
+	/* Check if a DATA READY interrupt has occurred,
+	 * and if there is more to transfer */
+	if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
+		if (module->remaining_tx_buffer_length) {
+			/* Write value will be at least 8-bits long */
+			uint16_t data_to_send = *(module->tx_buffer_ptr);
+			/* Increment 8-bit pointer */
+			(module->tx_buffer_ptr)++;
+
+			if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+				data_to_send |= (*(module->tx_buffer_ptr) << 8);
+				/* Increment 8-bit pointer */
+				(module->tx_buffer_ptr)++;
+			}
+			/* Write the data to send */
+			usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
+
+			if (--(module->remaining_tx_buffer_length) == 0) {
+				/* Disable the Data Register Empty Interrupt */
+				usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+				/* Enable Transmission Complete interrupt */
+				usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
+
+			}
+		} else {
+			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+		}
+	}
+
+	/* Check if the Transmission Complete interrupt has occurred and
+	 * that the transmit buffer is empty */
+	if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
+
+		/* Disable TX Complete Interrupt, and set STATUS_OK */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
+		module->tx_status = STATUS_OK;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
+			(*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
+		}
+	}
+
+	/* Check if the Receive Complete interrupt has occurred, and that
+	 * there's more data to receive */
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
+
+		if (module->remaining_rx_buffer_length) {
+			/* Read out the status code and mask away all but the 4 LSBs*/
+			error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+#if !SAMD20
+			/* CTS status should not be considered as an error */
+			if(error_code & SERCOM_USART_STATUS_CTS) {
+				error_code &= ~SERCOM_USART_STATUS_CTS;
+			}
+#endif
+#ifdef FEATURE_USART_LIN_MASTER
+			/* TXE status should not be considered as an error */
+			if(error_code & SERCOM_USART_STATUS_TXE) {
+				error_code &= ~SERCOM_USART_STATUS_TXE;
+			}
+#endif
+			/* Check if an error has occurred during the receiving */
+			if (error_code) {
+				/* Check which error occurred */
+				if (error_code & SERCOM_USART_STATUS_FERR) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_BAD_FORMAT;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+				} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_OVERFLOW;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+				} else if (error_code & SERCOM_USART_STATUS_PERR) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_BAD_DATA;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+				}
+#ifdef FEATURE_USART_LIN_SLAVE
+				else if (error_code & SERCOM_USART_STATUS_ISF) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_PROTOCOL;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+				}
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+				else if (error_code & SERCOM_USART_STATUS_COLL) {
+					/* Store the error code and clear flag by writing 1 to it */
+					module->rx_status = STATUS_ERR_PACKET_COLLISION;
+					usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+				}
+#endif
+
+				/* Run callback if registered and enabled */
+				if (callback_status
+						& (1 << USART_CALLBACK_ERROR)) {
+					(*(module->callback[USART_CALLBACK_ERROR]))(module);
+				}
+
+			} else {
+
+				/* Read current packet from DATA register,
+				 * increment buffer pointer and decrement buffer length */
+				uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
+
+				/* Read value will be at least 8-bits long */
+				*(module->rx_buffer_ptr) = received_data;
+				/* Increment 8-bit pointer */
+				module->rx_buffer_ptr += 1;
+
+				if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
+					/* 9-bit data, write next received byte to the buffer */
+					*(module->rx_buffer_ptr) = (received_data >> 8);
+					/* Increment 8-bit pointer */
+					module->rx_buffer_ptr += 1;
+				}
+
+				/* Check if the last character have been received */
+				if(--(module->remaining_rx_buffer_length) == 0) {
+					/* Disable RX Complete Interrupt,
+					 * and set STATUS_OK */
+					usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+					module->rx_status = STATUS_OK;
+
+					/* Run callback if registered and enabled */
+					if (callback_status
+							& (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
+						(*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
+					}
+				}
+			}
+		} else {
+			/* This should not happen. Disable Receive Complete interrupt. */
+			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+		}
+	}
+
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+	if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
+			(*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
+		}
+	}
+#endif
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
+			(*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
+		}
+	}
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+
+		/* Run callback if registered and enabled */
+		if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
+			(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
+		}
+	}
+#endif
+}
+

firmware/SendcommCmdsys/src/ASF/sam0/drivers/sercom/usart/usart_interrupt.h

@@ -0,0 +1,167 @@
+/**
+ * \file
+ *
+ * \brief SAM SERCOM USART Asynchronous Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef USART_INTERRUPT_H_INCLUDED
+#define USART_INTERRUPT_H_INCLUDED
+
+#include "usart.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__DOXYGEN__)
+enum status_code _usart_write_buffer(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code _usart_read_buffer(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length);
+
+void _usart_interrupt_handler(
+		uint8_t instance);
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_sercom_usart_group
+ *
+ * @{
+ */
+
+/**
+ * \name Callback Management
+ * @{
+ */
+void usart_register_callback(
+		struct usart_module *const module,
+		usart_callback_t callback_func,
+		enum usart_callback callback_type);
+
+void usart_unregister_callback(
+		struct usart_module *module,
+		enum usart_callback callback_type);
+
+/**
+ * \brief Enables callback
+ *
+ * Enables the callback function registered by the \ref usart_register_callback.
+ * The callback function will be called from the interrupt handler when the
+ * conditions for the callback type are met.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+static inline void usart_enable_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Enable callback */
+	module->callback_enable_mask |= (1 << callback_type);
+
+}
+
+/**
+ * \brief Disable callback
+ *
+ * Disables the callback function registered by the \ref usart_register_callback,
+ * and the callback will not be called from the interrupt routine.
+ *
+ * \param[in]  module         Pointer to USART software instance struct
+ * \param[in]  callback_type  Callback type given by an enum
+ */
+static inline void usart_disable_callback(
+		struct usart_module *const module,
+		enum usart_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	module->callback_enable_mask &= ~(1 << callback_type);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Writing and Reading
+ * @{
+ */
+enum status_code usart_write_job(
+		struct usart_module *const module,
+		const uint16_t *tx_data);
+
+enum status_code usart_read_job(
+		struct usart_module *const module,
+		uint16_t *const rx_data);
+
+enum status_code usart_write_buffer_job(
+		struct usart_module *const module,
+		uint8_t *tx_data,
+		uint16_t length);
+
+enum status_code usart_read_buffer_job(
+		struct usart_module *const module,
+		uint8_t *rx_data,
+		uint16_t length);
+
+void usart_abort_job(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type);
+
+enum status_code usart_get_job_status(
+		struct usart_module *const module,
+		enum usart_transceiver_type transceiver_type);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USART_INTERRUPT_H_INCLUDED */
+

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/clock/clock.h

@@ -0,0 +1,43 @@
+/**
+ * \file
+ *
+ * \brief SAM Clock Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SYSTEM_CLOCK_H_INCLUDED
+#define SYSTEM_CLOCK_H_INCLUDED
+
+#include <compiler.h>
+#include <gclk.h>
+#include <clock_feature.h>
+
+#endif /* SYSTEM_CLOCK_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/clock/clock_samr34/clock_config_check.h

@@ -0,0 +1,449 @@
+/**
+ * \file
+ *
+ * \brief SAMR34 Clock Driver
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef CLOCK_CONFIG_CHECK_H
+#  define CLOCK_CONFIG_CHECK_H
+
+#if !defined(CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT)
+#  error CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_FLASH_WAIT_STATES)
+#  error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_CPU_DIVIDER)
+#  error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_LOW_POWER_DIVIDER)
+#  error CONF_CLOCK_LOW_POWER_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_BACKUP_DIVIDER)
+#  error CONF_CLOCK_BACK_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC16M_FREQ_SEL)
+#  error CONF_CLOCK_OSC16M_FREQ_SEL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC16M_ON_DEMAND)
+#  error CONF_CLOCK_OSC16M_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC16M_RUN_IN_STANDBY)
+#  error CONF_CLOCK_OSC16M_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ENABLE)
+#  error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL)
+#  error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY)
+#  error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME)
+#  error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL)
+#  error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_ON_DEMAND)
+#  error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY)
+#  error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE)
+#  error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL)
+#  error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME)
+#  error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT)
+#  error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT)
+#  error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND)
+#  error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY)
+#  error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE)
+#  error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME)
+#  error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT)
+#  error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT)
+#  error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND)
+#  error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY)
+#  error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE)
+#  error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_LOOP_MODE)
+#  error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ON_DEMAND)
+#  error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_FINE_VALUE)
+#  error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_RUN_IN_STANDBY)
+#  error CONF_CLOCK_DFLL_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR)
+#  error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR)
+#  error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK)
+#  error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK)
+#  error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP)
+#  error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE)
+#  error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE)
+#  error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE)
+#  error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_ENABLE)
+#  error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_ON_DEMAND)
+#  error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY)
+#  error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS)
+#  error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST)
+#  error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE)
+#  error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_TIME)
+#  error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK)
+#  error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_FILTER)
+#  error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY)
+#  error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER)
+#  error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY)
+#  error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_PRESCALER)
+#  error CONF_CLOCK_DPLL_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR)
+#  error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR)
+#  error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h
+#endif
+
+
+#if !defined(CONF_CLOCK_CONFIGURE_GCLK)
+#  error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_ENABLE)
+#  error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_PRESCALER)
+#  error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_ENABLE)
+#  error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_PRESCALER)
+#  error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_ENABLE)
+#  error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_PRESCALER)
+#  error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_ENABLE)
+#  error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_PRESCALER)
+#  error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_ENABLE)
+#  error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_PRESCALER)
+#  error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_ENABLE)
+#  error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_PRESCALER)
+#  error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_ENABLE)
+#  error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_PRESCALER)
+#  error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_ENABLE)
+#  error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_PRESCALER)
+#  error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_ENABLE)
+#  error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY)
+#  error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE)
+#  error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_PRESCALER)
+#  error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h
+#endif
+
+#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE)
+#  error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h
+#endif
+
+#endif /* CLOCK_CONFIG_CHECK_H */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/clock/clock_samr34/gclk.c

@@ -0,0 +1,454 @@
+/**
+ * \file
+ *
+ * \brief SAMR34 Generic Clock Driver
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <gclk.h>
+#include <clock.h>
+#include <system_interrupt.h>
+
+
+ /**
+  * \brief Determines if the hardware module(s) are currently synchronizing to the bus.
+  *
+  * Checks to see if the underlying hardware peripheral module(s) are currently
+  * synchronizing across multiple clock domains to the hardware bus, This
+  * function can be used to delay further operations on a module until such time
+  * that it is ready, to prevent blocking delays for synchronization in the
+  * user application.
+  * \param[in] generator  Generic Clock Generator index to sync
+  *
+  * \return Synchronization status of the underlying hardware module(s).
+  *
+  * \retval false if the module has completed synchronization
+  * \retval true if the module synchronization is ongoing
+  */
+static inline bool system_gclk_is_syncing(const uint8_t generator)
+{
+
+	 if (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(1 << generator )){
+		 return true;
+	}
+
+	 return false;
+}
+
+
+/**
+ * \brief Initializes the GCLK driver.
+ *
+ * Initializes the Generic Clock module, disabling and resetting all active
+ * Generic Clock Generators and Channels to their power-on default values.
+ */
+void system_gclk_init(void)
+{
+	/* Turn on the digital interface clock */
+	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_GCLK);
+
+	/* Software reset the module to ensure it is re-initialized correctly */
+	GCLK->CTRLA.reg = GCLK_CTRLA_SWRST;
+	while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {
+		/* Wait for reset to complete */
+	}
+}
+
+/**
+ * \brief Writes a Generic Clock Generator configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock Generator configuration
+ * to the hardware module.
+ *
+ * \note Changing the clock source on the fly (on a running
+ *       generator) can take additional time if the clock source is configured
+ *       to only run on-demand (ONDEMAND bit is set) and it is not currently
+ *       running (no peripheral is requesting the clock source). In this case
+ *       the GCLK will request the new clock while still keeping a request to
+ *       the old clock source until the new clock source is ready.
+ *
+ * \note This function will not start a generator that is not already running;
+ *       to start the generator, call \ref system_gclk_gen_enable()
+ *       after configuring a generator.
+ *
+ * \param[in] generator  Generic Clock Generator index to configure
+ * \param[in] config     Configuration settings for the generator
+ */
+void system_gclk_gen_set_config(
+		const uint8_t generator,
+		struct system_gclk_gen_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Cache new register configurations to minimize sync requirements. */
+	uint32_t new_genctrl_config ;
+
+
+	/* Select the requested source clock for the generator */
+	new_genctrl_config = config->source_clock << GCLK_GENCTRL_SRC_Pos;
+
+	/* Configure the clock to be either high or low when disabled */
+	if (config->high_when_disabled) {
+		new_genctrl_config |= GCLK_GENCTRL_OOV;
+	}
+
+	/* Configure if the clock output to I/O pin should be enabled. */
+	if (config->output_enable) {
+		new_genctrl_config |= GCLK_GENCTRL_OE;
+	}
+
+	/* Set division factor */
+	if (config->division_factor > 1) {
+		/* Check if division is a power of two */
+		if (((config->division_factor & (config->division_factor - 1)) == 0)) {
+			/* Determine the index of the highest bit set to get the
+			 * division factor that must be loaded into the division
+			 * register */
+
+			uint32_t div2_count = 0;
+
+			uint32_t mask;
+			for (mask = (1UL << 1); mask < config->division_factor;
+						mask <<= 1) {
+				div2_count++;
+			}
+
+			/* Set binary divider power of 2 division factor */
+			new_genctrl_config  |= div2_count << GCLK_GENCTRL_DIV_Pos;
+			new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
+		} else {
+			/* Set integer division factor */
+
+			new_genctrl_config  |=
+					(config->division_factor) << GCLK_GENCTRL_DIV_Pos;
+
+			/* Enable non-binary division with increased duty cycle accuracy */
+			new_genctrl_config |= GCLK_GENCTRL_IDC;
+		}
+
+	}
+
+	/* Enable or disable the clock in standby mode */
+	if (config->run_in_standby) {
+		new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
+	}
+
+	while (system_gclk_is_syncing(generator)) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	GCLK->GENCTRL[generator].reg = new_genctrl_config | (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN);
+
+	while (system_gclk_is_syncing(generator)) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Enables a Generic Clock Generator that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock Generator that was previously
+ * configured via a call to \ref system_gclk_gen_set_config().
+ *
+ * \param[in] generator  Generic Clock Generator index to enable
+ */
+void system_gclk_gen_enable(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing(generator)) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Enable generator */
+	GCLK->GENCTRL[generator].reg |= GCLK_GENCTRL_GENEN;
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock Generator that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock Generator that was previously
+ * started via a call to \ref system_gclk_gen_enable().
+ *
+ * \param[in] generator  Generic Clock Generator index to disable
+ */
+void system_gclk_gen_disable(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing(generator)) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Disable generator */
+	GCLK->GENCTRL[generator].reg &= ~GCLK_GENCTRL_GENEN;
+	while (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN) {
+		/* Wait for clock to become disabled */
+	}
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock Generator is enabled.
+ *
+ * \param[in] generator  Generic Clock Generator index to check
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock Generator is enabled
+ * \retval false The Generic Clock Generator is disabled
+ */
+bool system_gclk_gen_is_enabled(
+		const uint8_t generator)
+{
+	bool enabled;
+
+	system_interrupt_enter_critical_section();
+
+	/* Obtain the enabled status */
+	enabled = (GCLK->GENCTRL[generator].reg & GCLK_GENCTRL_GENEN);
+
+	system_interrupt_leave_critical_section();
+
+	return enabled;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock generator.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * generator, used as a source to a Generic Clock Channel module.
+ *
+ * \param[in] generator  Generic Clock Generator index
+ *
+ * \return The frequency of the generic clock generator, in Hz.
+ */
+uint32_t system_gclk_gen_get_hz(
+		const uint8_t generator)
+{
+	while (system_gclk_is_syncing(generator)) {
+		/* Wait for synchronization */
+	};
+
+	system_interrupt_enter_critical_section();
+
+	/* Get the frequency of the source connected to the GCLK generator */
+	uint32_t gen_input_hz = system_clock_source_get_hz(
+			(enum system_clock_source)GCLK->GENCTRL[generator].bit.SRC);
+
+	uint8_t divsel = GCLK->GENCTRL[generator].bit.DIVSEL;
+	uint32_t divider = GCLK->GENCTRL[generator].bit.DIV;
+
+	system_interrupt_leave_critical_section();
+
+	/* Check if the generator is using fractional or binary division */
+	if (!divsel && divider > 1) {
+		gen_input_hz /= divider;
+	} else if (divsel) {
+		gen_input_hz >>= (divider+1);
+	}
+
+	return gen_input_hz;
+}
+
+/**
+ * \brief Writes a Generic Clock configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Generic Clock configuration to the
+ * hardware module. If the clock is currently running, it will be stopped.
+ *
+ * \note Once called the clock will not be running; to start the clock,
+ *       call \ref system_gclk_chan_enable() after configuring a clock channel.
+ *
+ * \param[in] channel   Generic Clock channel to configure
+ * \param[in] config    Configuration settings for the clock
+ *
+ */
+void system_gclk_chan_set_config(
+		const uint8_t channel,
+		struct system_gclk_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Disable generic clock channel */
+	system_gclk_chan_disable(channel);
+
+	/* Configure the peripheral channel */
+	GCLK->PCHCTRL[channel].reg = GCLK_PCHCTRL_GEN(config->source_generator);
+
+
+}
+
+/**
+ * \brief Enables a Generic Clock that was previously configured.
+ *
+ * Starts the clock generation of a Generic Clock that was previously
+ * configured via a call to \ref system_gclk_chan_set_config().
+ *
+ * \param[in] channel   Generic Clock channel to enable
+ */
+void system_gclk_chan_enable(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Enable the peripheral channel */
+	GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_CHEN;
+
+	while (!(GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN)) {
+		/* Wait for clock synchronization */
+	}
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Disables a Generic Clock that was previously enabled.
+ *
+ * Stops the clock generation of a Generic Clock that was previously started
+ * via a call to \ref system_gclk_chan_enable().
+ *
+ * \param[in] channel  Generic Clock channel to disable
+ */
+void system_gclk_chan_disable(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	/* Sanity check WRTLOCK */
+	Assert(!GCLK->PCHCTRL[channel].bit.WRTLOCK);
+
+	/* Disable the peripheral channel */
+	GCLK->PCHCTRL[channel].reg &= ~GCLK_PCHCTRL_CHEN;
+
+	while (GCLK->PCHCTRL[channel].reg & GCLK_PCHCTRL_CHEN) {
+		/* Wait for clock synchronization */
+	}
+
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is enabled.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The enabled status.
+ * \retval true The Generic Clock channel is enabled
+ * \retval false The Generic Clock channel is disabled
+ */
+bool system_gclk_chan_is_enabled(
+		const uint8_t channel)
+{
+	bool enabled;
+
+	system_interrupt_enter_critical_section();
+
+	/* Select the requested generic clock channel */
+	enabled = GCLK->PCHCTRL[channel].bit.CHEN;
+
+	system_interrupt_leave_critical_section();
+
+	return enabled;
+}
+
+/**
+ * \brief Locks a Generic Clock channel from further configuration writes.
+ *
+ * Locks a generic clock channel from further configuration writes. It is only
+ * possible to unlock the channel configuration through a power on reset.
+ *
+ * \param[in] channel   Generic Clock channel to enable
+ */
+void system_gclk_chan_lock(
+		const uint8_t channel)
+{
+	system_interrupt_enter_critical_section();
+
+	GCLK->PCHCTRL[channel].reg |= GCLK_PCHCTRL_WRTLOCK | GCLK_PCHCTRL_CHEN;
+	system_interrupt_leave_critical_section();
+}
+
+/**
+ * \brief Determins if the specified Generic Clock channel is locked.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The lock status.
+ * \retval true The Generic Clock channel is locked
+ * \retval false The Generic Clock channel is not locked
+ */
+bool system_gclk_chan_is_locked(
+		const uint8_t channel)
+{
+	bool locked;
+
+	system_interrupt_enter_critical_section();
+	locked = GCLK->PCHCTRL[channel].bit.WRTLOCK;
+	system_interrupt_leave_critical_section();
+
+	return locked;
+}
+
+/**
+ * \brief Retrieves the clock frequency of a Generic Clock channel.
+ *
+ * Determines the clock frequency (in Hz) of a specified Generic Clock
+ * channel, used as a source to a device peripheral module.
+ *
+ * \param[in] channel  Generic Clock Channel index
+ *
+ * \return The frequency of the generic clock channel, in Hz.
+ */
+uint32_t system_gclk_chan_get_hz(
+		const uint8_t channel)
+{
+	uint8_t gen_id;
+
+	system_interrupt_enter_critical_section();
+	/* Select the requested generic clock channel */
+	gen_id = GCLK->PCHCTRL[channel].bit.GEN;
+	system_interrupt_leave_critical_section();
+
+	/* Return the clock speed of the associated GCLK generator */
+	return system_gclk_gen_get_hz(gen_id);
+}

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/clock/gclk.h

@@ -0,0 +1,297 @@
+/**
+ * \file
+ *
+ * \brief SAM Generic Clock Driver
+ *
+ * Copyright (c) 2012-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED
+#define SYSTEM_CLOCK_GCLK_H_INCLUDED
+
+/**
+ * \addtogroup asfdoc_sam0_system_clock_group
+ *
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief List of available GCLK generators.
+ *
+ * List of Available GCLK generators. This enum is used in the peripheral
+ * device drivers to select the GCLK generator to be used for its operation.
+ *
+ * The number of GCLK generators available is device dependent.
+ */
+enum gclk_generator {
+	/** GCLK generator channel 0 */
+	GCLK_GENERATOR_0,
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)
+	/** GCLK generator channel 1 */
+	GCLK_GENERATOR_1,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)
+	/** GCLK generator channel 2 */
+	GCLK_GENERATOR_2,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)
+	/** GCLK generator channel 3 */
+	GCLK_GENERATOR_3,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)
+	/** GCLK generator channel 4 */
+	GCLK_GENERATOR_4,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)
+	/** GCLK generator channel 5 */
+	GCLK_GENERATOR_5,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)
+	/** GCLK generator channel 6 */
+	GCLK_GENERATOR_6,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)
+	/** GCLK generator channel 7 */
+	GCLK_GENERATOR_7,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)
+	/** GCLK generator channel 8 */
+	GCLK_GENERATOR_8,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)
+	/** GCLK generator channel 9 */
+	GCLK_GENERATOR_9,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)
+	/** GCLK generator channel 10 */
+	GCLK_GENERATOR_10,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)
+	/** GCLK generator channel 11 */
+	GCLK_GENERATOR_11,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)
+	/** GCLK generator channel 12 */
+	GCLK_GENERATOR_12,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)
+	/** GCLK generator channel 13 */
+	GCLK_GENERATOR_13,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)
+	/** GCLK generator channel 14 */
+	GCLK_GENERATOR_14,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)
+	/** GCLK generator channel 15 */
+	GCLK_GENERATOR_15,
+#endif
+#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)
+	/** GCLK generator channel 16 */
+	GCLK_GENERATOR_16,
+#endif
+};
+
+/**
+ * \brief Generic Clock Generator configuration structure.
+ *
+ * Configuration structure for a Generic Clock Generator channel. This
+ * structure should be initialized by the
+ * \ref system_gclk_gen_get_config_defaults() function before being modified by
+ * the user application.
+ */
+struct system_gclk_gen_config {
+	/** Source clock input channel index, see the \ref system_clock_source */
+	uint8_t source_clock;
+	/** If \c true, the generator output level is high when disabled */
+	bool high_when_disabled;
+	/** Integer division factor of the clock output compared to the input */
+	uint32_t division_factor;
+	/** If \c true, the clock is kept enabled during device standby mode */
+	bool run_in_standby;
+	/** If \c true, enables GCLK generator clock output to a GPIO pin */
+	bool output_enable;
+};
+
+/**
+ * \brief Generic Clock configuration structure.
+ *
+ * Configuration structure for a Generic Clock channel. This structure
+ * should be initialized by the \ref system_gclk_chan_get_config_defaults()
+ * function before being modified by the user application.
+ */
+struct system_gclk_chan_config {
+	/** Generic Clock Generator source channel */
+	enum gclk_generator source_generator;
+};
+
+/** \name Generic Clock Management
+ * @{
+ */
+void system_gclk_init(void);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Management (Generators)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock Generator configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock Generator configuration structure to
+ * a set of known default values. This function should be called on all
+ * new instances of these configuration structures before being modified
+ * by the user application.
+ *
+ * The default configuration is:
+ *  \li The clock is generated undivided from the source frequency
+ *  \li The clock generator output is low when the generator is disabled
+ *  \li The input clock is sourced from input clock channel 0
+ *  \li The clock will be disabled during sleep
+ *  \li The clock output will not be routed to a physical GPIO pin
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_gclk_gen_get_config_defaults(
+		struct system_gclk_gen_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->division_factor    = 1;
+	config->high_when_disabled = false;
+#if SAML21 || SAML22  || SAMR30 || SAMR34 || SAMR35 || (WLR089)
+	config->source_clock       = GCLK_SOURCE_OSC16M;
+#elif (SAMC20) || (SAMC21)
+	config->source_clock       = GCLK_SOURCE_OSC48M;
+#else
+	config->source_clock       = GCLK_SOURCE_OSC8M;
+#endif
+	config->run_in_standby     = false;
+	config->output_enable      = false;
+}
+
+void system_gclk_gen_set_config(
+		const uint8_t generator,
+		struct system_gclk_gen_config *const config);
+
+void system_gclk_gen_enable(
+		const uint8_t generator);
+
+void system_gclk_gen_disable(
+		const uint8_t generator);
+
+bool system_gclk_gen_is_enabled(
+		const uint8_t generator);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Management (Channels)
+ * @{
+ */
+
+/**
+ * \brief Initializes a Generic Clock configuration structure to defaults.
+ *
+ * Initializes a given Generic Clock configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li The clock is sourced from the Generic Clock Generator channel 0
+ *  \li The clock configuration will not be write-locked when set
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_gclk_chan_get_config_defaults(
+		struct system_gclk_chan_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->source_generator = GCLK_GENERATOR_0;
+}
+
+void system_gclk_chan_set_config(
+		const uint8_t channel,
+		struct system_gclk_chan_config *const config);
+
+void system_gclk_chan_enable(
+		const uint8_t channel);
+
+void system_gclk_chan_disable(
+		const uint8_t channel);
+
+bool system_gclk_chan_is_enabled(
+		const uint8_t channel);
+
+void system_gclk_chan_lock(
+		const uint8_t channel);
+
+bool system_gclk_chan_is_locked(
+		const uint8_t channel);
+
+/** @} */
+
+
+/**
+ * \name Generic Clock Frequency Retrieval
+ * @{
+ */
+
+uint32_t system_gclk_gen_get_hz(
+		const uint8_t generator);
+
+uint32_t system_gclk_chan_get_hz(
+		const uint8_t channel);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/interrupt/system_interrupt.c

@@ -0,0 +1,207 @@
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include "system_interrupt.h"
+
+/**
+ * \brief Check if a interrupt line is pending.
+ *
+ * Checks if the requested interrupt vector is pending.
+ *
+ * \param[in] vector  Interrupt vector number to check
+ *
+ * \returns A boolean identifying if the requested interrupt vector is pending.
+ *
+ * \retval true   Specified interrupt vector is pending
+ * \retval false  Specified interrupt vector is not pending
+ *
+ */
+bool system_interrupt_is_pending(
+		const enum system_interrupt_vector vector)
+{
+	bool result;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		result = ((NVIC->ISPR[0] & (1 << vector)) != 0);
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);
+	} else {
+		Assert(false);
+		result = false;
+	}
+
+	return result;
+}
+
+/**
+ * \brief Set a interrupt vector as pending.
+ *
+ * Set the requested interrupt vector as pending (i.e. issues a software
+ * interrupt request for the specified vector). The software handler will be
+ * handled (if enabled) in a priority order based on vector number and
+ * configured priority settings.
+ *
+ * \param[in] vector  Interrupt vector number which is set as pending
+ *
+ * \returns Status code identifying if the vector was successfully set as
+ *          pending.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_pending(
+		const enum system_interrupt_vector vector)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		NVIC->ISPR[0] = (1 << vector);
+	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+		/* Note: Because NMI has highest priority it will be executed
+		 * immediately after it has been set pending */
+		SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
+	} else {
+		/* The user want to set something unsupported as pending */
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Clear pending interrupt vector.
+ *
+ * Clear a pending interrupt vector, so the software handler is not executed.
+ *
+ * \param[in] vector  Interrupt vector number to clear
+ *
+ * \returns A status code identifying if the interrupt pending state was
+ *          successfully cleared.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_clear_pending(
+		const enum system_interrupt_vector vector)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		NVIC->ICPR[0] = (1 << vector);
+	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
+		/* Note: Clearing of NMI pending interrupts does not make sense and is
+		 * not supported by the device, as it has the highest priority and will
+		 * always be executed at the moment it is set */
+		return STATUS_ERR_INVALID_ARG;
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
+	} else {
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Set interrupt vector priority level.
+ *
+ * Set the priority level of an external interrupt or exception.
+ *
+ * \param[in] vector          Interrupt vector to change
+ * \param[in] priority_level  New vector priority level to set
+ *
+ * \returns Status code indicating if the priority level of the interrupt was
+ *          successfully set.
+ *
+ * \retval STATUS_OK           If no error was detected
+ * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
+ */
+enum status_code system_interrupt_set_priority(
+		const enum system_interrupt_vector vector,
+		const enum system_interrupt_priority_level priority_level)
+{
+	enum status_code status = STATUS_OK;
+
+	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
+		uint8_t register_num = vector / 4;
+		uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+		NVIC->IP[register_num] =
+				(NVIC->IP[register_num] & ~(_SYSTEM_INTERRUPT_PRIORITY_MASK << priority_pos)) |
+				(priority_level << priority_pos);
+
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);
+	} else {
+		Assert(false);
+		status = STATUS_ERR_INVALID_ARG;
+	}
+
+	return status;
+}
+
+/**
+ * \brief Get interrupt vector priority level.
+ *
+ * Retrieves the priority level of the requested external interrupt or exception.
+ *
+ * \param[in] vector  Interrupt vector of which the priority level will be read
+ *
+ * \return Currently configured interrupt priority level of the given interrupt
+ *         vector.
+ */
+enum system_interrupt_priority_level system_interrupt_get_priority(
+		const enum system_interrupt_vector vector)
+{
+	uint8_t register_num = vector / 4;
+	uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+	enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;
+
+	if (vector >= 0) {
+		priority = (enum system_interrupt_priority_level)
+				((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
+		priority = (enum system_interrupt_priority_level)
+				((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+	}
+
+	return priority;
+}
+

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/interrupt/system_interrupt.h

@@ -0,0 +1,423 @@
+/**
+ * \file
+ *
+ * \brief SAM System Interrupt Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SYSTEM_INTERRUPT_H_INCLUDED
+#define SYSTEM_INTERRUPT_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_interrupt_group SAM System Interrupt (SYSTEM INTERRUPT) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of internal software and
+ * hardware interrupts/exceptions.
+ *
+ * The following peripheral is used by this module:
+ *  - NVIC (Nested Vector Interrupt Controller)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34
+ *  - Atmel | SMART SAM R35
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_interrupt_prerequisites
+ *  - \ref asfdoc_sam0_system_interrupt_module_overview
+ *  - \ref asfdoc_sam0_system_interrupt_special_considerations
+ *  - \ref asfdoc_sam0_system_interrupt_extra_info
+ *  - \ref asfdoc_sam0_system_interrupt_examples
+ *  - \ref asfdoc_sam0_system_interrupt_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_module_overview Module Overview
+ *
+ * The ARM&reg; Cortex&reg; M0+ core contains an interrupt and exception vector table, which
+ * can be used to configure the device's interrupt handlers; individual
+ * interrupts and exceptions can be enabled and disabled, as well as configured
+ * with a variable priority.
+ *
+ * This driver provides a set of wrappers around the core interrupt functions,
+ * to expose a simple API for the management of global and individual interrupts
+ * within the device.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_criticalsec Critical Sections
+ * In some applications it is important to ensure that no interrupts may be
+ * executed by the system whilst a critical portion of code is being run; for
+ * example, a buffer may be copied from one context to another - during which
+ * interrupts must be disabled to avoid corruption of the source buffer contents
+ * until the copy has completed. This driver provides a basic API to enter and
+ * exit nested critical sections, so that global interrupts can be kept disabled
+ * for as long as necessary to complete a critical application code section.
+ *
+ * \subsection asfdoc_sam0_system_interrupt_module_overview_softints Software Interrupts
+ * For some applications, it may be desirable to raise a module or core
+ * interrupt via software. For this reason, a set of APIs to set an interrupt or
+ * exception as pending are provided to the user application.
+ *
+ * \section asfdoc_sam0_system_interrupt_special_considerations Special Considerations
+ *
+ * Interrupts from peripherals in the SAM devices are on a per-module basis;
+ * an interrupt raised from any source within a module will cause a single,
+ * module-common handler to execute. It is the user application or driver's
+ * responsibility to de-multiplex the module-common interrupt to determine the
+ * exact interrupt cause.
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_interrupt_extra. This includes:
+ *  - \ref asfdoc_sam0_system_interrupt_extra_acronyms
+ *  - \ref asfdoc_sam0_system_interrupt_extra_dependencies
+ *  - \ref asfdoc_sam0_system_interrupt_extra_errata
+ *  - \ref asfdoc_sam0_system_interrupt_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_interrupt_exqsg.
+ *
+ * \section asfdoc_sam0_system_interrupt_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+#include <core_cm0plus.h>
+#include "system_interrupt_features.h"
+
+/**
+ * \brief Table of possible system interrupt/exception vector priorities.
+ *
+ * Table of all possible interrupt and exception vector priorities within the
+ * device.
+ */
+enum system_interrupt_priority_level {
+	/** Priority level 0, the highest possible interrupt priority */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_0  = 0,
+	/** Priority level 1 */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_1  = 1,
+	/** Priority level 2 */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_2  = 2,
+	/** Priority level 3, the lowest possible interrupt priority */
+	SYSTEM_INTERRUPT_PRIORITY_LEVEL_3  = 3,
+};
+
+/**
+ * \name Critical Section Management
+ * @{
+ */
+
+/**
+ * \brief Enters a critical section.
+ *
+ * Disables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_enter_critical_section(void)
+{
+	cpu_irq_enter_critical();
+}
+
+/**
+ * \brief Leaves a critical section.
+ *
+ * Enables global interrupts. To support nested critical sections, an internal
+ * count of the critical section nesting will be kept, so that global interrupts
+ * are only re-enabled upon leaving the outermost nested critical section.
+ *
+ */
+static inline void system_interrupt_leave_critical_section(void)
+{
+	cpu_irq_leave_critical();
+}
+
+/** @} */
+
+/**
+ * \name Interrupt Enabling/Disabling
+ * @{
+ */
+
+/**
+ * \brief Check if global interrupts are enabled.
+ *
+ * Checks if global interrupts are currently enabled.
+ *
+ * \returns A boolean that identifies if the global interrupts are enabled or not.
+ *
+ * \retval true   Global interrupts are currently enabled
+ * \retval false  Global interrupts are currently disabled
+ *
+ */
+static inline bool system_interrupt_is_global_enabled(void)
+{
+	return cpu_irq_is_enabled();
+}
+
+/**
+ * \brief Enables global interrupts.
+ *
+ * Enables global interrupts in the device to fire any enabled interrupt handlers.
+ */
+static inline void system_interrupt_enable_global(void)
+{
+	cpu_irq_enable();
+}
+
+/**
+ * \brief Disables global interrupts.
+ *
+ * Disabled global interrupts in the device, preventing any enabled interrupt
+ * handlers from executing.
+ */
+static inline void system_interrupt_disable_global(void)
+{
+	cpu_irq_disable();
+}
+
+/**
+ * \brief Checks if an interrupt vector is enabled or not.
+ *
+ * Checks if a specific interrupt vector is currently enabled.
+ *
+ * \param[in] vector  Interrupt vector number to check
+ *
+ * \returns A variable identifying if the requested interrupt vector is enabled.
+ *
+ * \retval true   Specified interrupt vector is currently enabled
+ * \retval false  Specified interrupt vector is currently disabled
+ *
+ */
+static inline bool system_interrupt_is_enabled(
+		const enum system_interrupt_vector vector)
+{
+	return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);
+}
+
+/**
+ * \brief Enable interrupt vector.
+ *
+ * Enables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector Interrupt vector to enable
+ */
+static inline void system_interrupt_enable(
+		const enum system_interrupt_vector vector)
+{
+	NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/**
+ * \brief Disable interrupt vector.
+ *
+ * Disables execution of the software handler for the requested interrupt vector.
+ *
+ * \param[in] vector  Interrupt vector to disable
+ */
+static inline void system_interrupt_disable(
+		const enum system_interrupt_vector vector)
+{
+	NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+}
+
+/** @} */
+
+/**
+ * \name Interrupt State Management
+ * @{
+ */
+
+/**
+ * \brief Get active interrupt (if any).
+ *
+ * Return the vector number for the current executing software handler, if any.
+ *
+ * \return Interrupt number that is currently executing.
+ */
+static inline enum system_interrupt_vector system_interrupt_get_active(void)
+{
+	uint32_t IPSR = __get_IPSR();
+	/* The IPSR returns the Exception number, which with an offset 16 to IRQ number. */
+	return (enum system_interrupt_vector)((IPSR & _SYSTEM_INTERRUPT_IPSR_MASK) - 16);
+}
+
+bool system_interrupt_is_pending(
+		const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_set_pending(
+		const enum system_interrupt_vector vector);
+
+enum status_code system_interrupt_clear_pending(
+		const enum system_interrupt_vector vector);
+
+/** @} */
+
+/**
+ * \name Interrupt Priority Management
+ * @{
+ */
+
+enum status_code system_interrupt_set_priority(
+		const enum system_interrupt_vector vector,
+		const enum system_interrupt_priority_level priority_level);
+
+enum system_interrupt_priority_level system_interrupt_get_priority(
+		const enum system_interrupt_vector vector);
+
+/** @} */
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>ISR</td>
+ *		<td>Interrupt Service Routine</td>
+ *	</tr>
+ *	<tr>
+ *		<td>NMI</td>
+ *		<td>Non-maskable Interrupt</td>
+ *	</tr>
+ *	<tr>
+ *		<td>SERCOM</td>
+ *		<td>Serial Communication Interface</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_interrupt_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_interrupt_group. QSGs are simple examples with
+ * step-by-step instructions to configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_system_interrupt_critsec_use_case
+ *  - \subpage asfdoc_sam0_system_interrupt_enablemodint_use_case
+ *
+ * \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</th>
+ *		<th>Date</th>
+ *		<th>Comments</th>
+ *	</tr>
+ *	<tr>
+ *		<td>42122E</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122D</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122C</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42122A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/interrupt/system_interrupt_samr34/system_interrupt_features.h

@@ -0,0 +1,158 @@
+/**
+ * \file
+ *
+ * \brief SAMR34 System Interrupt Driver
+ *
+ * Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
+
+#if !defined(__DOXYGEN__)
+
+/* Generates a interrupt vector table enum list entry for a given module type
+   and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
+#  define _MODULE_IRQn(n, module) \
+		SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
+
+/* Generates interrupt vector table enum list entries for all instances of a
+   given module type on the selected device. */
+#  define _SYSTEM_INTERRUPT_MODULES(name) \
+		MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
+
+#  define _SYSTEM_INTERRUPT_IPSR_MASK              0x0000003f
+#  define _SYSTEM_INTERRUPT_PRIORITY_MASK          0x00000003
+
+#  define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START  0
+
+#  define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS        30
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_interrupt_group
+ * @{
+ */
+
+/**
+ * \brief Table of possible system interrupt/exception vector numbers.
+ *
+ * Table of all possible interrupt and exception vector indexes within the
+ * SAM L21 device.
+ */
+#if defined(__DOXYGEN__)
+/** \note The actual enumeration name is "system_interrupt_vector". */
+enum system_interrupt_vector_samr34 {
+#else
+enum system_interrupt_vector {
+#endif
+	/** Interrupt vector index for a NMI interrupt */
+	SYSTEM_INTERRUPT_NON_MASKABLE      = NonMaskableInt_IRQn,
+	/** Interrupt vector index for a Hard Fault memory access exception */
+	SYSTEM_INTERRUPT_HARD_FAULT        = HardFault_IRQn,
+	/** Interrupt vector index for a Supervisor Call exception */
+	SYSTEM_INTERRUPT_SV_CALL           = SVCall_IRQn,
+	/** Interrupt vector index for a Pending Supervisor interrupt */
+	SYSTEM_INTERRUPT_PENDING_SV        = PendSV_IRQn,
+	/** Interrupt vector index for a System Tick interrupt */
+	SYSTEM_INTERRUPT_SYSTICK           = SysTick_IRQn,
+
+	/** Interrupt vector index for MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_SYSTEM     = SYSTEM_IRQn,
+	/** Interrupt vector index for a Watch Dog peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_WDT        = WDT_IRQn,
+	/** Interrupt vector index for a Real Time Clock peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_RTC        = RTC_IRQn,
+	/** Interrupt vector index for an External Interrupt peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_EIC        = EIC_IRQn,
+	/** Interrupt vector index for a Non Volatile Memory Controller interrupt */
+	SYSTEM_INTERRUPT_MODULE_NVMCTRL    = NVMCTRL_IRQn,
+	/** Interrupt vector index for a Direct Memory Access interrupt */
+	SYSTEM_INTERRUPT_MODULE_DMA        = DMAC_IRQn,
+	/** Interrupt vector index for a Universal Serial Bus interrupt */
+	SYSTEM_INTERRUPT_MODULE_USB        = USB_IRQn,
+	/** Interrupt vector index for an Event System interrupt */
+	SYSTEM_INTERRUPT_MODULE_EVSYS      = EVSYS_IRQn,
+#if defined(__DOXYGEN__)
+	/** Interrupt vector index for a SERCOM peripheral interrupt.
+	 *
+	 *  Each specific device may contain several SERCOM peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
+	 */
+	SYSTEM_INTERRUPT_MODULE_SERCOMn    = SERCOMn_IRQn,
+
+	/** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
+	 *
+	 *  Each specific device may contain several TCC peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_TCC0).
+	 */
+	SYSTEM_INTERRUPT_MODULE_TCCn        = TCCn_IRQn,
+
+	/** Interrupt vector index for a Timer/Counter peripheral interrupt.
+	 *
+	 *  Each specific device may contain several TC peripherals; each module
+	 *  instance will have its own entry in the table, with the instance number
+	 *  substituted for "n" in the entry name (e.g.
+	 *  \c SYSTEM_INTERRUPT_MODULE_TC3).
+	 */
+	SYSTEM_INTERRUPT_MODULE_TCn        = TCn_IRQn,
+#else
+	_SYSTEM_INTERRUPT_MODULES(SERCOM)
+
+	_SYSTEM_INTERRUPT_MODULES(TCC)
+#if	(SAML21J) || (SAMR34J) || (SAMR35J)
+	_SYSTEM_INTERRUPT_MODULES(TC)
+#else
+	SYSTEM_INTERRUPT_MODULE_TC0        = TC0_IRQn,
+	SYSTEM_INTERRUPT_MODULE_TC1        = TC1_IRQn,
+	SYSTEM_INTERRUPT_MODULE_TC4        = TC4_IRQn,
+#endif
+#endif
+
+	/** Interrupt vector index for an Analog Comparator peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_AC         = AC_IRQn,
+	/** Interrupt vector index for an Analog-to-Digital peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_ADC        = ADC_IRQn,
+	/** Interrupt vector index for a Peripheral Touch Controller peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_PTC        = PTC_IRQn,
+	/** Interrupt vector index for a AES peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_AES        = AES_IRQn,
+	/** Interrupt vector index for a TRNG peripheral interrupt */
+	SYSTEM_INTERRUPT_MODULE_TRNG       = TRNG_IRQn,
+};
+
+/** @} */
+
+#endif

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/pinmux/pinmux.c

@@ -0,0 +1,301 @@
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include <pinmux.h>
+
+/**
+ * \internal
+ * Writes out a given configuration of a Port pin configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] port      Base of the PORT module to configure
+ * \param[in] pin_mask  Mask of the port pin to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+static void _system_pinmux_config(
+		PortGroup *const port,
+		const uint32_t pin_mask,
+		const struct system_pinmux_config *const config)
+{
+	Assert(port);
+	Assert(config);
+
+	/* Track the configuration bits into a temporary variable before writing */
+	uint32_t pin_cfg = 0;
+
+	/* Enabled powersave mode, don't create configuration */
+	if (!config->powersave) {
+		/* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
+		 * be written later) and store the new MUX mask */
+		if (config->mux_position != SYSTEM_PINMUX_GPIO) {
+			pin_cfg |= PORT_WRCONFIG_PMUXEN;
+			pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
+		}
+
+		/* Check if the user has requested that the input buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Enable input buffer flag */
+			pin_cfg |= PORT_WRCONFIG_INEN;
+
+			/* Enable pull-up/pull-down control flag if requested */
+			if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
+				pin_cfg |= PORT_WRCONFIG_PULLEN;
+			}
+
+			/* Clear the port DIR bits to disable the output buffer */
+			port->DIRCLR.reg = pin_mask;
+		}
+
+		/* Check if the user has requested that the output buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Cannot use a pull-up if the output driver is enabled,
+			 * if requested the input buffer can only sample the current
+			 * output state */
+			pin_cfg &= ~PORT_WRCONFIG_PULLEN;
+		}
+	} else {
+		port->DIRCLR.reg = pin_mask;
+	}
+
+	/* The Write Configuration register (WRCONFIG) requires the
+	 * pins to to grouped into two 16-bit half-words - split them out here */
+	uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
+	uint32_t upper_pin_mask = (pin_mask >> 16);
+
+	/* Configure the lower 16-bits of the port to the desired configuration,
+	 * including the pin peripheral multiplexer just in case it is enabled */
+	port->WRCONFIG.reg
+		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
+
+	/* Configure the upper 16-bits of the port to the desired configuration,
+	 * including the pin peripheral multiplexer just in case it is enabled */
+	port->WRCONFIG.reg
+		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
+			PORT_WRCONFIG_HWSEL;
+
+	if(!config->powersave) {
+		/* Set the pull-up state once the port pins are configured if one was
+		 * requested and it does not violate the valid set of port
+		 * configurations */
+		if (pin_cfg & PORT_WRCONFIG_PULLEN) {
+			/* Set the OUT register bits to enable the pull-up if requested,
+			 * clear to enable pull-down */
+			if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
+				port->OUTSET.reg = pin_mask;
+			} else {
+				port->OUTCLR.reg = pin_mask;
+			}
+		}
+
+		/* Check if the user has requested that the output buffer be enabled */
+		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
+			/* Set the port DIR bits to enable the output buffer */
+			port->DIRSET.reg = pin_mask;
+		}
+	}
+}
+
+/**
+ * \brief Writes a Port pin configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin configuration to the hardware
+ * module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+void system_pinmux_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct system_pinmux_config *const config)
+{
+	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_mask = (1UL << (gpio_pin % 32));
+
+	_system_pinmux_config(port, pin_mask, config);
+}
+
+/**
+ * \brief Writes a Port pin group configuration to the hardware module.
+ *
+ * Writes out a given configuration of a Port pin group configuration to the
+ * hardware module.
+ *
+ * \note If the pin direction is set as an output, the pull-up/pull-down input
+ *       configuration setting is ignored.
+ *
+ * \param[in] port      Base of the PORT module to configure
+ * \param[in] mask      Mask of the port pin(s) to configure
+ * \param[in] config    Configuration settings for the pin
+ */
+void system_pinmux_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct system_pinmux_config *const config)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			_system_pinmux_config(port, (1UL << i), config);
+		}
+	}
+}
+
+/**
+ * \brief Configures the input sampling mode for a group of pins.
+ *
+ * Configures the input sampling mode for a group of pins, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New pin sampling mode to configure
+ */
+void system_pinmux_group_set_input_sample_mode(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_sample mode)
+{
+	Assert(port);
+
+	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+		port->CTRL.reg |= mask;
+	} else {
+		port->CTRL.reg &= ~mask;
+	}
+}
+
+#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
+/**
+ * \brief Configures the output slew rate mode for a group of pins.
+ *
+ * Configures the output slew rate mode for a group of pins, to
+ * control the speed at which the physical output pin can react to
+ * logical changes of the I/O pin value.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New pin slew rate mode to configure
+ */
+void system_pinmux_group_set_output_slew_rate(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_slew_rate mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
+				port->PINCFG[i].reg |=  PORT_PINCFG_SLEWLIM;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM;
+			}
+		}
+	}
+}
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+/**
+ * \brief Configures the output driver strength mode for a group of pins.
+ *
+ * Configures the output drive strength for a group of pins, to
+ * control the amount of current the pad is able to sink/source.
+ *
+ * \param[in] port     Base of the PORT module to configure
+ * \param[in] mask     Mask of the port pin(s) to configure
+ * \param[in] mode     New output driver strength mode to configure
+ */
+void system_pinmux_group_set_output_strength(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_strength mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
+				port->PINCFG[i].reg |=  PORT_PINCFG_DRVSTR;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR;
+			}
+		}
+	}
+}
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
+/**
+ * \brief Configures the output driver mode for a group of pins.
+ *
+ * Configures the output driver mode for a group of pins, to
+ * control the pad behavior.
+ *
+ * \param[in] port Base of the PORT module to configure
+ * \param[in] mask Mask of the port pin(s) to configure
+ * \param[in] mode New pad output driver mode to configure
+ */
+void system_pinmux_group_set_output_drive(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_drive mode)
+{
+	Assert(port);
+
+	for (int i = 0; i < 32; i++) {
+		if (mask & (1UL << i)) {
+			if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
+				port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN;
+			} else {
+				port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN;
+			}
+		}
+	}
+}
+#endif

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/pinmux/pinmux.h

@@ -0,0 +1,669 @@
+/**
+ * \file
+ *
+ * \brief SAM Pin Multiplexer Driver
+ *
+ * Copyright (c) 2012-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef PINMUX_H_INCLUDED
+#define PINMUX_H_INCLUDED
+
+/**
+ * \defgroup asfdoc_sam0_system_pinmux_group SAM System Pin Multiplexer (SYSTEM PINMUX) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides
+ * an interface for the configuration and management of the device's physical
+ * I/O Pins, to alter the direction and input/drive characteristics as well as
+ * to configure the pin peripheral multiplexer selection.
+ *
+ * The following peripheral is used by this module:
+ *  - PORT (Port I/O Management)
+ *
+ * The following devices can use this module:
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM L21/L22
+ *  - Atmel | SMART SAM DA1
+ *  - Atmel | SMART SAM C20/C21
+ *  - Atmel | SMART SAM HA1
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34
+ *  - Atmel | SMART SAM R35
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_pinmux_prerequisites
+ *  - \ref asfdoc_sam0_system_pinmux_module_overview
+ *  - \ref asfdoc_sam0_system_pinmux_special_considerations
+ *  - \ref asfdoc_sam0_system_pinmux_extra_info
+ *  - \ref asfdoc_sam0_system_pinmux_examples
+ *  - \ref asfdoc_sam0_system_pinmux_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_module_overview Module Overview
+ *
+ * The SAM devices contain a number of General Purpose I/O pins, used to
+ * interface the user application logic and internal hardware peripherals to
+ * an external system. The Pin Multiplexer (PINMUX) driver provides a method
+ * of configuring the individual pin peripheral multiplexers to select
+ * alternate pin functions.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_features Driver Feature Macro Definition
+ * <table>
+ *  <tr>
+ *    <th>Driver Feature Macro</th>
+ *    <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *    <td>FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH</td>
+ *    <td>SAM L21, SAM C20/C21, SAM R34/R35</td>
+ *  </tr>
+ * </table>
+ * \note The specific features are only available in the driver when the
+ * selected device supports those features.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins
+ * SAM devices use two naming conventions for the I/O pins in the device; one
+ * physical and one logical. Each physical pin on a device package is assigned
+ * both a physical port and pin identifier (e.g. "PORTA.0") as well as a
+ * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
+ * former is used to map physical pins to their physical internal device module
+ * counterparts, for simplicity the design of this driver uses the logical GPIO
+ * numbers instead.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_peripheral_muxing Peripheral Multiplexing
+ * SAM devices contain a peripheral MUX, which is individually controllable
+ * for each I/O pin of the device. The peripheral MUX allows you to select the
+ * function of a physical package pin - whether it will be controlled as a user
+ * controllable GPIO pin, or whether it will be connected internally to one of
+ * several peripheral modules (such as an I<SUP>2</SUP>C module). When a pin is
+ * configured in GPIO mode, other peripherals connected to the same pin will be
+ * disabled.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_pad_characteristics Special Pad Characteristics
+ * There are several special modes that can be selected on one or more I/O pins
+ * of the device, which alter the input and output characteristics of the pad.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_drive_strength Drive Strength
+ * The Drive Strength configures the strength of the output driver on the
+ * pad. Normally, there is a fixed current limit that each I/O pin can safely
+ * drive, however some I/O pads offer a higher drive mode which increases this
+ * limit for that I/O pin at the expense of an increased power consumption.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_slew_rate Slew Rate
+ * The Slew Rate configures the slew rate of the output driver, limiting the
+ * rate at which the pad output voltage can change with time.
+ *
+ * \subsubsection asfdoc_sam0_system_pinmux_input_sample_mode Input Sample Mode
+ * The Input Sample Mode configures the input sampler buffer of the pad. By
+ * default, the input buffer is only sampled "on-demand", i.e. when the user
+ * application attempts to read from the input buffer. This mode is the most
+ * power efficient, but increases the latency of the input sample by two clock
+ * cycles of the port clock. To reduce latency, the input sampler can instead
+ * be configured to always sample the input buffer on each port clock cycle, at
+ * the expense of an increased power consumption.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_module_overview_physical Physical Connection
+ *
+ * \ref asfdoc_sam0_system_pinmux_intconnections "The diagram below" shows
+ * how this module is interconnected within the device:
+ *
+ * \anchor asfdoc_sam0_system_pinmux_intconnections
+ * \dot
+ * digraph overview {
+ *   node [label="Port Pad" shape=square] pad;
+ *
+ *   subgraph driver {
+ *     node [label="Peripheral MUX" shape=trapezium] pinmux;
+ *     node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio;
+ *     node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
+ *   }
+ *
+ *   pinmux -> gpio;
+ *   pad    -> pinmux;
+ *   pinmux -> peripherals;
+ * }
+ * \enddot
+ *
+ * \section asfdoc_sam0_system_pinmux_special_considerations Special Considerations
+ *
+ * The SAM port pin input sampling mode is set in groups of four physical
+ * pins; setting the sampling mode of any pin in a sub-group of eight I/O pins
+ * will configure the sampling mode of the entire sub-group.
+ *
+ * High Drive Strength output driver mode is not available on all device pins -
+ * refer to your device specific datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_pinmux_extra. This includes:
+ *  - \ref asfdoc_sam0_system_pinmux_extra_acronyms
+ *  - \ref asfdoc_sam0_system_pinmux_extra_dependencies
+ *  - \ref asfdoc_sam0_system_pinmux_extra_errata
+ *  - \ref asfdoc_sam0_system_pinmux_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_examples Examples
+ *
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_system_pinmux_exqsg.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_api_overview API Overview
+ * @{
+ */
+
+#include <compiler.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*@{*/ 
+#if (SAML21) || (SAMC20) || (SAMC21) || (SAMD21) || (SAMD10) || (SAMD11) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089) || defined(__DOXYGEN__)
+/** Output Driver Strength Selection feature support */
+#  define FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+#endif
+/*@}*/
+
+/** Peripheral multiplexer index to select GPIO mode for a pin */
+#define SYSTEM_PINMUX_GPIO    (1 << 7)
+
+/**
+ * \brief Port pin direction configuration enum.
+ *
+ * Enum for the possible pin direction settings of the port pin configuration
+ * structure, to indicate the direction the pin should use.
+ */
+enum system_pinmux_pin_dir {
+	/** The pin's input buffer should be enabled, so that the pin state can
+	 *  be read */
+	SYSTEM_PINMUX_PIN_DIR_INPUT,
+	/** The pin's output buffer should be enabled, so that the pin state can
+	 *  be set (but not read back) */
+	SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+	/** The pin's output and input buffers should both be enabled, so that the
+	 *  pin state can be set and read back */
+	SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+};
+
+/**
+ * \brief Port pin input pull configuration enum.
+ *
+ * Enum for the possible pin pull settings of the port pin configuration
+ * structure, to indicate the type of logic level pull the pin should use.
+ */
+enum system_pinmux_pin_pull {
+	/** No logical pull should be applied to the pin */
+	SYSTEM_PINMUX_PIN_PULL_NONE,
+	/** Pin should be pulled up when idle */
+	SYSTEM_PINMUX_PIN_PULL_UP,
+	/** Pin should be pulled down when idle */
+	SYSTEM_PINMUX_PIN_PULL_DOWN,
+};
+
+/**
+ * \brief Port pin digital input sampling mode enum.
+ *
+ * Enum for the possible input sampling modes for the port pin configuration
+ * structure, to indicate the type of sampling a port pin should use.
+ */
+enum system_pinmux_pin_sample {
+	/** Pin input buffer should continuously sample the pin state */
+	SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,
+	/** Pin input buffer should be enabled when the IN register is read */
+	SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,
+};
+
+/**
+ * \brief Port pin configuration structure.
+ *
+ * Configuration structure for a port pin instance. This structure should
+ * be initialized by the \ref system_pinmux_get_config_defaults() function
+ * before being modified by the user application.
+ */
+struct system_pinmux_config {
+	/** MUX index of the peripheral that should control the pin, if peripheral
+	 *  control is desired. For GPIO use, this should be set to
+	 *  \ref SYSTEM_PINMUX_GPIO. */
+	uint8_t mux_position;
+
+	/** Port buffer input/output direction */
+	enum system_pinmux_pin_dir direction;
+
+	/** Logic level pull of the input buffer */
+	enum system_pinmux_pin_pull input_pull;
+
+	/** Enable lowest possible powerstate on the pin
+	 *
+	 *  \note All other configurations will be ignored, the pin will be disabled.
+	 */
+	bool powersave;
+};
+
+/** \name Configuration and Initialization
+ * @{
+ */
+
+/**
+ * \brief Initializes a Port pin configuration structure to defaults.
+ *
+ * Initializes a given Port pin configuration structure to a set of
+ * known default values. This function should be called on all new
+ * instances of these configuration structures before being modified by the
+ * user application.
+ *
+ * The default configuration is as follows:
+ *  \li Non peripheral (i.e. GPIO) controlled
+ *  \li Input mode with internal pull-up enabled
+ *
+ * \param[out] config  Configuration structure to initialize to default values
+ */
+static inline void system_pinmux_get_config_defaults(
+		struct system_pinmux_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	/* Default configuration values */
+	config->mux_position = SYSTEM_PINMUX_GPIO;
+	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+	config->input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+	config->powersave    = false;
+}
+
+void system_pinmux_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct system_pinmux_config *const config);
+
+void system_pinmux_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct system_pinmux_config *const config);
+
+/** @} */
+
+/** \name Special Mode Configuration (Physical Group Orientated)
+ *  @{
+ */
+
+/**
+ * \brief Retrieves the PORT module group instance from a given GPIO pin number.
+ *
+ * Retrieves the PORT module group instance associated with a given logical
+ * GPIO pin number.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to convert
+ *
+ * \return Base address of the associated PORT module.
+ */
+static inline PortGroup* system_pinmux_get_group_from_gpio_pin(
+		const uint8_t gpio_pin)
+{
+	uint8_t port_index  = (gpio_pin / 128);
+	uint8_t group_index = (gpio_pin / 32);
+
+	/* Array of available ports */
+	Port *const ports[PORT_INST_NUM] = PORT_INSTS;
+
+	if (port_index < PORT_INST_NUM) {
+		return &(ports[port_index]->Group[group_index]);
+	} else {
+		Assert(false);
+		return NULL;
+	}
+}
+
+void system_pinmux_group_set_input_sample_mode(
+		PortGroup *const port,
+		const uint32_t mask,
+		const enum system_pinmux_pin_sample mode);
+
+/** @} */
+
+/** \name Special Mode Configuration (Logical Pin Orientated)
+ *  @{
+ */
+
+/**
+ * \brief Retrieves the currently selected MUX position of a logical pin.
+ *
+ * Retrieves the selected MUX peripheral on a given logical GPIO pin.
+ *
+ * \param[in]  gpio_pin  Index of the GPIO pin to configure
+ *
+ * \return Currently selected peripheral index on the specified pin.
+ */
+static inline uint8_t system_pinmux_pin_get_mux_position(
+		const uint8_t gpio_pin)
+{
+	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_index = (gpio_pin % 32);
+
+	if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) {
+		return SYSTEM_PINMUX_GPIO;
+	}
+
+	uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;
+
+	if (pin_index & 1) {
+		return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+	}
+	else {
+		return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+	}
+}
+
+/**
+ * \brief Configures the input sampling mode for a GPIO pin.
+ *
+ * Configures the input sampling mode for a GPIO input, to
+ * control when the physical I/O pin value is sampled and
+ * stored inside the microcontroller.
+ *
+ * \param[in] gpio_pin Index of the GPIO pin to configure
+ * \param[in] mode     New pin sampling mode to configure
+ */
+static inline void system_pinmux_pin_set_input_sample_mode(
+		const uint8_t gpio_pin,
+		const enum system_pinmux_pin_sample mode)
+{
+	PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+	uint32_t pin_index = (gpio_pin % 32);
+
+	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
+		port->CTRL.reg |= (1 << pin_index);
+	} else {
+		port->CTRL.reg &= ~(1 << pin_index);
+	}
+}
+
+/** @} */
+
+#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH
+/**
+ * \brief Port pin drive output strength enum.
+ *
+ * Enum for the possible output drive strengths for the port pin
+ * configuration structure, to indicate the driver strength the pin should
+ * use.
+ */
+enum system_pinmux_pin_strength {
+  /** Normal output driver strength */
+  SYSTEM_PINMUX_PIN_STRENGTH_NORMAL,
+  /** High current output driver strength */
+  SYSTEM_PINMUX_PIN_STRENGTH_HIGH,
+};
+
+/**
+ * \brief Configures the output driver strength mode for a GPIO pin.
+ *
+ * Configures the output drive strength for a GPIO output, to
+ * control the amount of current the pad is able to sink/source.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New output driver strength mode to configure
+ */
+static inline void system_pinmux_pin_set_output_strength(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_strength mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_DRVSTR;
+  }
+ else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR;
+ }
+}
+
+void system_pinmux_group_set_output_strength(
+    PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_strength mode);
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
+/**
+ * \brief Port pin output slew rate enum.
+ *
+ * Enum for the possible output drive slew rates for the port pin
+ * configuration structure, to indicate the driver slew rate the pin should
+ * use.
+ */
+enum system_pinmux_pin_slew_rate {
+  /** Normal pin output slew rate */
+  SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL,
+  /** Enable slew rate limiter on the pin */
+  SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED,
+};
+
+/**
+ * \brief Configures the output slew rate mode for a GPIO pin.
+ *
+ * Configures the output slew rate mode for a GPIO output, to
+ * control the speed at which the physical output pin can react to
+ * logical changes of the I/O pin value.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New pin slew rate mode to configure
+ */
+static inline void system_pinmux_pin_set_output_slew_rate(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_slew_rate mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_SLEWLIM;
+  }
+  else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM;
+  }
+}
+
+void system_pinmux_group_set_output_slew_rate(
+   PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_slew_rate mode);
+#endif
+
+#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN
+/**
+ * \brief Port pin output drive mode enum.
+ *
+ * Enum for the possible output drive modes for the port pin configuration
+ * structure, to indicate the output mode the pin should use.
+ */
+enum system_pinmux_pin_drive {
+  /** Use totem pole output drive mode */
+  SYSTEM_PINMUX_PIN_DRIVE_TOTEM,
+  /** Use open drain output drive mode */
+  SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN,
+};
+
+/**
+ * \brief Configures the output driver mode for a GPIO pin.
+ *
+ * Configures the output driver mode for a GPIO output, to
+ * control the pad behavior.
+ *
+ * \param[in] gpio_pin  Index of the GPIO pin to configure
+ * \param[in] mode      New pad output driver mode to configure
+ */
+static inline void system_pinmux_pin_set_output_drive(
+    const uint8_t gpio_pin,
+    const enum system_pinmux_pin_drive mode)
+{
+  PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+  uint32_t pin_index = (gpio_pin % 32);
+
+  if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
+    port->PINCFG[pin_index].reg |=  PORT_PINCFG_ODRAIN;
+  }
+  else {
+    port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN;
+  }
+}
+
+void system_pinmux_group_set_output_drive(
+    PortGroup *const port,
+    const uint32_t mask,
+    const enum system_pinmux_pin_drive mode);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_acronyms Acronyms
+ * The table below presents the acronyms used in this module:
+ *
+ * <table>
+ *	<tr>
+ *		<th>Acronym</th>
+ *		<th>Description</th>
+ *	</tr>
+ *	<tr>
+ *		<td>GPIO</td>
+ *		<td>General Purpose Input/Output</td>
+ *	</tr>
+ *	<tr>
+ *		<td>MUX</td>
+ *		<td>Multiplexer</td>
+ *	</tr>
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_pinmux_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *	<tr>
+ *		<th>Changelog</th>
+ *	</tr>
+ *	<tr>
+ *		<td>Removed code of open drain, slew limit and drive strength
+ *		features</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Fixed broken sampling mode function implementations, which wrote
+ *		    corrupt configuration values to the device registers</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Added missing NULL pointer asserts to the PORT driver functions</td>
+ *	</tr>
+ *	<tr>
+ *		<td>Initial Release</td>
+ *	</tr>
+ * </table>
+ */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver
+ *
+ * This is a list of the available Quick Start guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_pinmux_group. QSGs are simple
+ * examples with step-by-step instructions to configure and use this driver in a
+ * selection of use cases. Note that a QSG can be compiled as a standalone
+ * application or be added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_system_pinmux_basic_use_case
+ *
+ * \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History
+ *
+ * <table>
+ *	<tr>
+ *		<th>Doc. Rev.</td>
+ *		<th>Date</td>
+ *		<th>Comments</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121F</td>
+ *		<td>12/2015</td>
+ *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121E</td>
+ *		<td>12/2014</td>
+ *		<td>Added support for SAM R21 and SAM D10/D11</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121D</td>
+ *		<td>01/2014</td>
+ *		<td>Added support for SAM D21</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121C</td>
+ *		<td>09/2013</td>
+ *		<td>Fixed incorrect documentation for the device pin sampling mode</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121B</td>
+ *		<td>06/2013</td>
+ *		<td>Corrected documentation typos</td>
+ *	</tr>
+ *	<tr>
+ *		<td>42121A</td>
+ *		<td>06/2013</td>
+ *		<td>Initial release</td>
+ *	</tr>
+ * </table>
+ */
+
+#endif

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h

@@ -0,0 +1,86 @@
+/**
+ * \file
+ *
+ * \brief SAM PINMUX Driver Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_system_pinmux_basic_use_case Quick Start Guide for SYSTEM PINMUX - Basic
+ *
+ * In this use case, the PINMUX module is configured for:
+ *  \li One pin in input mode, with pull-up enabled, connected to the GPIO
+ *      module
+ *  \li Sampling mode of the pin changed to sample on demand
+ *
+ * This use case sets up the PINMUX to configure a physical I/O pin set as
+ * an input with pull-up and changes the sampling mode of the pin to reduce
+ * power by only sampling the physical pin state when the user application
+ * attempts to read it.
+ *
+ * \section asfdoc_sam0_system_pinmux_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your application:
+ * \snippet qs_pinmux_basic.c setup
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_flow Workflow
+ * -# Create a PINMUX module pin configuration struct, which can be filled out
+ *    to adjust the configuration of a single port pin.
+ *    \snippet qs_pinmux_basic.c pinmux_config
+ * -# Initialize the pin configuration struct with the module's default values.
+ *    \snippet qs_pinmux_basic.c pinmux_config_defaults
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Adjust the configuration struct to request an input pin with pull-up
+ *    connected to the GPIO peripheral.
+ *  \snippet qs_pinmux_basic.c pinmux_update_config_values
+ * -# Configure GPIO10 with the initialized pin configuration struct, to enable
+ *    the input sampler on the pin.
+ *    \snippet qs_pinmux_basic.c pinmux_set_config
+ *
+ * \section asfdoc_sam0_system_pinmux_basic_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_pinmux_basic.c main
+ *
+ * \subsection asfdoc_sam0_system_pinmux_basic_use_case_flow Workflow
+
+ * -# Adjust the configuration of the pin to enable on-demand sampling mode.
+ *    \snippet qs_pinmux_basic.c pinmux_change_input_sampling
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/power/power_sam_l/power.h

@@ -0,0 +1,990 @@
+/**
+ * \file
+ *
+ * \brief SAM L21/L22/R30/R34/R35 Power functionality
+ *
+ * Copyright (c) 2014-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef POWER_H_INCLUDED
+#define POWER_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Device sleep modes.
+ *
+ * List of available sleep modes in the device. A table of clocks available in
+ * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ */
+enum system_sleepmode {
+	/** IDLE sleep mode */
+	SYSTEM_SLEEPMODE_IDLE       = PM_SLEEPCFG_SLEEPMODE(0x2),
+	/** STANDBY sleep mode */
+	SYSTEM_SLEEPMODE_STANDBY    = PM_SLEEPCFG_SLEEPMODE_STANDBY,
+	/** BACKUP sleep mode */
+	SYSTEM_SLEEPMODE_BACKUP     = PM_SLEEPCFG_SLEEPMODE_BACKUP,
+	/** OFF sleep mode */
+	SYSTEM_SLEEPMODE_OFF        = PM_SLEEPCFG_SLEEPMODE_OFF,
+};
+
+/**
+ * \brief Performance level.
+ *
+ * List of performance levels. Performance level technique consists of
+ * adjusting the regulator output voltage to reduce power consumption.
+ */
+enum system_performance_level {
+	/** Performance level 0 */
+	SYSTEM_PERFORMANCE_LEVEL_0  = PM_PLCFG_PLSEL_PL0,
+	/** Performance level 2 */
+	SYSTEM_PERFORMANCE_LEVEL_2  = PM_PLCFG_PLSEL_PL2,
+};
+
+/**
+ * \brief RAM Back-biasing mode.
+ *
+ * List of RAM back bias modes. By default, in standby sleep mode,
+ * RAM is in low power mode (back biased) if its power domain is in
+ * retention state. This behavior can be changed by configuring the Back Bias
+ * bit groups in STDBYCFG(STDBYCFG.BBIASxx).
+ */
+enum system_ram_back_bias_mode {
+	/** Retention Back biasing mode */
+	SYSTEM_RAM_BACK_BIAS_RETENTION = 0,
+	/** Standby Back Biasing mode */
+	SYSTEM_RAM_BACK_BIAS_STANDBY,
+	/** Standby OFF mode */
+	SYSTEM_RAM_BACK_BIAS_STANDBY_OFF,
+	/** Always OFF mode */
+	SYSTEM_RAM_BACK_BIAS_OFF,
+};
+
+#if SAML21 || SAMR30 || (SAMR34) || (SAMR35)|| (WLR089)
+/**
+ * \brief Linked power domain.
+ *
+ * List of linked power domains. Power domains can be linked to each other.
+ * It allows a power domain (PDn) to be kept in active state if the inferior
+ * power domain (PDn-1) is in active state too.
+ */
+enum system_linked_power_domain {
+	/** Power domains PD0/PD1/PD2 are not linked */
+	SYSTEM_LINKED_POWER_DOMAIN_DEFAULT   = PM_STDBYCFG_LINKPD_DEFAULT_Val,
+	/** Power domains PD0 and PD1 are linked */
+	SYSTEM_LINKED_POWER_DOMAIN_PD01      = PM_STDBYCFG_LINKPD_PD01_Val,
+	/** Power domains PD1 and PD2 are linked */
+	SYSTEM_LINKED_POWER_DOMAIN_PD12      = PM_STDBYCFG_LINKPD_PD12_Val,
+	/** All Power domains are linked */
+	SYSTEM_LINKED_POWER_DOMAIN_PD012     = PM_STDBYCFG_LINKPD_PD012_Val,
+};
+
+#if (SAML21XXXB) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+/**
+ * \brief VREG switching mode.
+ *
+ * List of VREG switching modes.
+ */
+enum system_vreg_switch_mode {
+	/** Automatic mode. */
+	SYSTEM_SYSTEM_VREG_SWITCH_AUTO = 0,
+	/** Performance oriented. */
+	SYSTEM_SYSTEM_VREG_SWITCH_PERFORMANCE,
+	/** Low Power consumption oriented. */
+	SYSTEM_SYSTEM_VREG_SWITCH_LP,
+};
+#endif
+
+/**
+ * \brief Power domain.
+ *
+ * List of power domains. Power domain gating technique consists of turning
+ * on or off power domain voltage to save power while keeping other domains
+ * powered up.
+ */
+enum system_power_domain {
+	/** All power domains switching are handled by hardware */
+	SYSTEM_POWER_DOMAIN_DEFAULT = PM_STDBYCFG_PDCFG_DEFAULT_Val,
+	/** Power domain 0 (PD0) is forced ACTIVE */
+	SYSTEM_POWER_DOMAIN_PD0     = PM_STDBYCFG_PDCFG_PD0_Val,
+	/** Power domain 0 and 1 (PD0 and PD1) are forced ACTIVE */
+	SYSTEM_POWER_DOMAIN_PD01    = PM_STDBYCFG_PDCFG_PD01_Val,
+	/** All power domains are forced ACTIVE */
+	SYSTEM_POWER_DOMAIN_PD012   = PM_STDBYCFG_PDCFG_PD012_Val,
+};
+#endif
+
+#if SAML22
+/**
+ * \brief Voltage Regulator switch in Standby mode.
+ *
+ */
+enum system_vreg_switch_mode {
+	/** Automatic mode. */
+	SYSTEM_VREG_SWITCH_AUTO        = PM_STDBYCFG_VREGSMOD_AUTO_Val,
+	/** Performance oriented. */
+	SYSTEM_VREG_SWITCH_PERFORMANCE = PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val,
+	/** Low Power consumption oriented. */
+	SYSTEM_VREG_SWITCH_LP          = PM_STDBYCFG_VREGSMOD_LP_Val,
+};
+
+#endif
+
+/**
+ * \brief Voltage regulator.
+ *
+ * Voltage regulators selection. In active mode, the voltage regulator
+ * can be chosen on the fly between a LDO or a Buck converter.
+ */
+enum system_voltage_regulator_sel {
+	/** The voltage regulator in active mode is a LDO voltage regulator */
+	SYSTEM_VOLTAGE_REGULATOR_LDO    = SUPC_VREG_SEL_LDO_Val,
+	/** The voltage regulator in active mode is a buck converter */
+	SYSTEM_VOLTAGE_REGULATOR_BUCK   = SUPC_VREG_SEL_BUCK_Val,
+};
+
+/**
+ * \brief Low power efficiency.
+ *
+ * Low power mode efficiency.
+ */
+enum system_voltage_regulator_low_power_efficiency {
+	/** The voltage regulator in Low power mode has the default efficiency and
+		support the whole VDD range (1.62V to 3.6V) */
+	SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT,
+	/** The voltage regulator in Low power mode has the highest efficiency and
+		support the limited VDD range (2.5V to 3.6V) */
+	SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_HIGHTEST,
+};
+
+/**
+ * \brief Voltage reference value.
+ *
+ * Voltage references selection.
+ */
+enum system_voltage_references_sel {
+	/** 1.0V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_1V0    = SUPC_VREF_SEL_1V0_Val,
+	/** 1.1V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_1V1    = SUPC_VREF_SEL_1V1_Val,
+	/** 1.2V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_1V2    = SUPC_VREF_SEL_1V2_Val,
+	/** 1.25V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_1V25   = SUPC_VREF_SEL_1V25_Val,
+	/** 2.0V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_2V0    = SUPC_VREF_SEL_2V0_Val,
+	/** 2.2V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_2V2    = SUPC_VREF_SEL_2V2_Val,
+	/** 2.4V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_2V4    = SUPC_VREF_SEL_2V4_Val,
+	/** 2.5V voltage reference typical value */
+	SYSTEM_VOLTAGE_REFERENCE_2V5    = SUPC_VREF_SEL_2V5_Val,
+};
+
+/**
+ * \brief Battery power switch configuration enum.
+ *
+ * Enum for Battery power switch modes.
+ */
+enum system_battery_power_switch {
+	/** The backup domain is always supplied by main power */
+	SYSTEM_BATTERY_POWER_SWITCH_NONE      = SUPC_BBPS_CONF_NONE_Val,
+	/** The power switch is handled by the automatic power switch */
+	SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC = SUPC_BBPS_CONF_APWS_Val,
+	/** The backup domain is always supplied by battery backup power */
+	SYSTEM_BATTERY_POWER_SWITCH_FORCED    = SUPC_BBPS_CONF_FORCED_Val,
+	/** The power switch is handled by the BOD33 */
+	SYSTEM_BATTERY_POWER_SWITCH_BOD33     = SUPC_BBPS_CONF_BOD33_Val,
+};
+
+/**
+ * \brief Voltage reference.
+ *
+ * List of available voltage references (VREF) that may be used within the
+ * device.
+ */
+enum system_voltage_reference {
+	/** Temperature sensor voltage reference */
+	SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
+	/** Voltage reference output */
+	SYSTEM_VOLTAGE_REFERENCE_OUTPUT,
+};
+
+/**
+ * \brief Backup IO enum.
+ *
+ * List of Backup input and output pins.
+ * If enabled (\ref system_backup_pin_output_enable), the pins can be driven
+ * by the SUPC.
+ */
+enum system_backup_pin {
+	/** Power Supply OK status pin */
+	SYSTEM_BACKUP_PIN_PSOK  = (0x1 << 0),
+	/** Backup output pin 0  */
+	SYSTEM_BACKUP_PIN_OUT_0 = (0x1 << 1),
+	/** Backup output pin 1  */
+	SYSTEM_BACKUP_PIN_OUT_1 = (0x1 << 2)
+};
+
+/**
+ * \brief Standby configuration.
+ *
+ * Configuration structure for standby mode.
+ */
+struct system_standby_config {
+#if SAML21 || SAMR30 || (SAMR34) || (SAMR35) || (WLR089)
+	/** Power domain. */
+	enum system_power_domain  power_domain;
+	/** Enable dynamic power gating for power domain 0 */
+	bool enable_dpgpd0;
+	/** Enable dynamic power gating for power domain 1 */
+	bool enable_dpgpd1;
+#if (SAML21XXXA)
+	/** Automatic VREG switching disable. */
+	bool disable_avregsd;
+#else
+	/** VREG switching mode */
+	enum system_vreg_switch_mode vregs_mode;
+#endif
+	/** Linked power domain */
+	enum system_linked_power_domain linked_power_domain;
+#elif SAML22
+	/** Regulator switch mode in standby. */
+	enum system_vreg_switch_mode vreg_switch_mode;
+#endif
+	/** Back bias for HMCRAMCHS. */
+	enum system_ram_back_bias_mode hmcramchs_back_bias;
+	/** Back bias for HMCRAMCLP */
+	enum system_ram_back_bias_mode hmcramclp_back_bias;
+};
+
+/**
+ * \brief Voltage Regulator System (VREG) Control configuration.
+ *
+ * Configuration structure for VREG.
+ */
+struct system_voltage_regulator_config {
+	/** Voltage scaling period */
+	uint8_t  voltage_scale_period;
+	/** Voltage scaling voltage step */
+	uint8_t voltage_scale_step;
+	/** Run in standby in standby sleep mode */
+	bool run_in_standby;
+	/** Voltage Regulator Selection */
+	enum system_voltage_regulator_sel  regulator_sel;
+	/** Low power efficiency */
+	enum system_voltage_regulator_low_power_efficiency low_power_efficiency;
+#if SAML22 || SAML21XXXB || (SAMR34J) || (SAMR35J) || (WLR089U0)
+	/** Run in standby in performance level 0. */
+	bool run_in_standby_pl0;
+#endif
+};
+
+/**
+ * \brief Voltage References System (VREF) Control configuration.
+ *
+ * Configuration structure for VREF.
+ */
+struct system_voltage_references_config {
+	/** Voltage References Selection */
+	enum system_voltage_references_sel  sel;
+	/** On Demand Control */
+	bool on_demand;
+	/** Run in standby */
+	bool run_in_standby;
+#if SAML22
+	/** Temperature Sensor Selection. */
+	bool temperature_sensor_sel;
+#endif
+};
+
+/**
+ * \brief Battery Backup Power Switch (BBPS) Control configuration.
+ *
+ * Configuration structure for Battery Backup Power Switch (BBPS).
+ */
+struct system_battery_backup_power_switch_config {
+	/** Enable device wake up when BBPS switches from
+		battery backup power to main power */
+	bool wake_enabled;
+	/** Battery backup power switch configuration */
+	enum system_battery_power_switch battery_power_switch;
+};
+
+/**
+ * \name Voltage Regulator
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for voltage regulator.
+ *
+ * Fills a configuration structure with the default configuration:
+ *   - Voltage scaling period is 1μs
+ *   - Voltage scaling voltage step is 2*min_step
+ *   - The voltage regulator is in low power mode in Standby sleep mode
+ *   - The voltage regulator in active mode is an LDO voltage regulator
+ *   - The voltage regulator in Low power mode has the default efficiency
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_voltage_regulator_get_config_defaults(
+		struct system_voltage_regulator_config *const config)
+{
+	Assert(config);
+	config->voltage_scale_period = 0;
+	config->voltage_scale_step   = 0;
+	config->run_in_standby       = false;
+	config->regulator_sel        = SYSTEM_VOLTAGE_REGULATOR_LDO;
+	config->low_power_efficiency = SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT;
+#if SAML22 || SAML21XXXB || SAMR34J || SAMR35J || (WLR089U0)
+	config->run_in_standby_pl0   = false;
+#endif
+}
+
+/**
+ * \brief Configure voltage regulator.
+ *
+ * Configures voltage regulator with the given configuration.
+ *
+ * \param[in] config  Voltage regulator configuration structure containing
+ *                    the new config
+ */
+static inline void system_voltage_regulator_set_config(
+		struct system_voltage_regulator_config *const config)
+{
+	Assert(config);
+	SUPC->VREG.bit.VSPER    = config->voltage_scale_period;
+	SUPC->VREG.bit.VSVSTEP  = config->voltage_scale_step;
+	SUPC->VREG.bit.RUNSTDBY = config->run_in_standby;
+	SUPC->VREG.bit.SEL      = config->regulator_sel;
+#if (SAML21XXXB) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	SUPC->VREG.bit.LPEFF    = config->low_power_efficiency;
+#endif
+#if SAML22 || SAML21XXXB || SAMR34J || SAMR35J || (WLR089U0)
+	SUPC->VREG.bit.STDBYPL0 = config->run_in_standby_pl0;
+#endif
+	while(!(SUPC->STATUS.reg & SUPC_STATUS_VREGRDY)) {
+		;
+	}
+}
+
+/**
+* \brief Enable the selected voltage regulator.
+ *
+ * Enables the selected voltage regulator source.
+ */
+static inline void system_voltage_regulator_enable(void)
+{
+	SUPC->VREG.reg |= SUPC_VREG_ENABLE;
+}
+
+/**
+ * \brief Disable the selected voltage regulator.
+ *
+ * Disables the selected voltage regulator.
+ */
+static inline void system_voltage_regulator_disable(void)
+{
+	SUPC->VREG.reg &= ~SUPC_VREG_ENABLE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Voltage References
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for voltage reference.
+ *
+ * Fill a configuration structure with the default configuration:
+ *   - 1.0V voltage reference typical value
+ *   - On demand control disabled
+ *   - The voltage reference and the temperature sensor are halted during standby sleep mode
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_voltage_reference_get_config_defaults(
+		struct system_voltage_references_config *const config)
+{
+	Assert(config);
+	config->sel            = SYSTEM_VOLTAGE_REFERENCE_1V0;
+	config->on_demand      = false;
+	config->run_in_standby = false;
+#if SAML22
+	config->temperature_sensor_sel = false;
+#endif
+}
+
+/**
+ * \brief Configure voltage reference.
+ *
+ * Configures voltage reference with the given configuration.
+ *
+ * \param[in] config  Voltage reference configuration structure containing
+ *                    the new config
+ */
+static inline void system_voltage_reference_set_config(
+		struct system_voltage_references_config *const config)
+{
+	Assert(config);
+	SUPC->VREF.bit.SEL      = config->sel;
+	SUPC->VREF.bit.ONDEMAND = config->on_demand;
+	SUPC->VREF.bit.RUNSTDBY = config->run_in_standby;
+#if SAML22
+	SUPC->VREF.bit.TSSEL    = config->temperature_sensor_sel;
+#endif
+}
+
+/**
+ * \brief Enable the selected voltage reference.
+ *
+ * Enables the selected voltage reference source, making the voltage reference
+ * available on a pin as well as an input source to the analog peripherals.
+ *
+ * \param[in] vref  Voltage reference to enable
+ */
+static inline void system_voltage_reference_enable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SUPC->VREF.reg |= SUPC_VREF_TSEN;
+			break;
+		case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
+			SUPC->VREF.reg |= SUPC_VREF_VREFOE;
+			break;
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * \brief Disable the selected voltage reference.
+ *
+ * Disables the selected voltage reference source.
+ *
+ * \param[in] vref  Voltage reference to disable
+ */
+static inline void system_voltage_reference_disable(
+		const enum system_voltage_reference vref)
+{
+	switch (vref) {
+		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+			SUPC->VREF.reg &= ~SUPC_VREF_TSEN;
+			break;
+		case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
+			SUPC->VREF.reg &= ~SUPC_VREF_VREFOE;
+			break;
+		default:
+			Assert(false);
+			return;
+	}
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Battery Backup Power Switch
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for battery backup power switch control.
+ *
+ * Fills a configuration structure with the default configuration:
+ *   - The main Power Supply OK status is not available on the PSOK pin
+ *   - The device is not woken up when switched from battery backup power to main power
+ *   - The backup domain is always supplied by main power
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_battery_backup_power_switch_get_config_defaults(
+		struct system_battery_backup_power_switch_config *const config)
+{
+	Assert(config);
+	config->wake_enabled         = false;
+	config->battery_power_switch = SYSTEM_BATTERY_POWER_SWITCH_NONE;
+}
+
+/**
+ * \brief Configure battery backup power switch.
+ *
+ * Configures battery backup power switch with the given configuration.
+ *
+ * \param[in] config  Battery backup power switch configuration structure containing
+ *                    the new config
+ */
+static inline void system_battery_backup_power_switch_set_config(
+		struct system_battery_backup_power_switch_config *const config)
+{
+	Assert(config);
+	uint32_t new_config = SUPC->BBPS.reg & SUPC_BBPS_PSOKEN;
+
+	if(config->wake_enabled) {
+		new_config |= SUPC_BBPS_WAKEEN;
+	}
+
+	new_config |= SUPC_BBPS_CONF(config->battery_power_switch);
+
+	SUPC->BBPS.reg = new_config;
+
+	if (config->battery_power_switch == SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC) {
+		while (!(SUPC->STATUS.reg & SUPC_STATUS_APWSRDY)) {
+			;
+		}
+	}
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Output Pins in Backup Mode
+ * @{
+ */
+
+/**
+ *  \brief Enable the backup pin output.
+ *
+ *  The output is enabled and driven by the SUPC.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_enable(
+		enum system_backup_pin pin)
+{
+	if (pin == SYSTEM_BACKUP_PIN_PSOK) {
+		SUPC->BBPS.reg |= SUPC_BBPS_PSOKEN;
+	} else {
+		SUPC->BKOUT.reg |= SUPC_BKOUT_EN(pin >> 1);
+	}
+}
+
+/**
+ *  \brief Disable the backup pin output.
+ *
+ *  The output is not enabled.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_disable(
+		enum system_backup_pin pin)
+{
+	if (pin == SYSTEM_BACKUP_PIN_PSOK) {
+		SUPC->BBPS.reg &= ~SUPC_BBPS_PSOKEN;
+	} else {
+		SUPC->BKOUT.reg &= ~SUPC_BKOUT_EN(pin >> 1);
+	}
+}
+
+/**
+ * \brief Check if backup pin output is enabled.
+ *
+ *  \param[in] pin Backup pin index
+ *
+ * \return The enabled status.
+ * \retval true The output is enabled
+ * \retval false The output is not enabled
+ */
+static inline bool system_backup_pin_output_is_enabled(
+		enum system_backup_pin pin)
+{
+	bool enabled = false;
+
+	if (pin == SYSTEM_BACKUP_PIN_PSOK) {
+		if (SUPC->BBPS.reg & SUPC_BBPS_PSOKEN) {
+			enabled = true;
+		}
+	} else {
+		if (SUPC->BKOUT.reg & SUPC_BKOUT_EN(pin >> 1)) {
+			enabled = true;
+		}
+	}
+	return enabled;
+}
+
+/**
+ *  \brief Enable the backup pin toggle on RTC event.
+ *
+ *  Toggle output on RTC event is enabled.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_enable_rtc_toggle(
+		enum system_backup_pin pin)
+{
+	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+
+	SUPC->BKOUT.reg |= SUPC_BKOUT_RTCTGL(pin >> 1);
+}
+
+/**
+ *  \brief Disable the backup pin toggle on RTC event.
+ *
+ *  Toggle output on RTC event is disabled.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_disable_rtc_toggle(
+		enum system_backup_pin pin)
+{
+	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+
+	SUPC->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(pin >> 1);
+}
+
+/**
+ *  \brief Set the backup pin.
+ *
+ *  Set the corresponding output pin.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_set(
+		enum system_backup_pin pin)
+{
+	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+
+	SUPC->BKOUT.reg |= SUPC_BKOUT_SET(pin >> 1);
+}
+
+/**
+ *  \brief Clear the backup pin.
+ *
+ *  Clear the corresponding output.
+ *
+ *  \param[in] pin Backup pin index
+ */
+static inline void system_backup_pin_output_clear(
+		enum system_backup_pin pin)
+{
+	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+
+	SUPC->BKOUT.reg |= SUPC_BKOUT_CLR(pin >> 1);
+}
+
+/**
+ *  \brief Get the backup I/O input values.
+ *
+ *  Get the backup I/O data input values. If the corresponding pin is enabled,
+ *  the I/O input value is given on the pin.
+ *
+ *  \param[in] pin Backup pin index
+ *
+ * \return The backup I/O input level value.
+ */
+static inline bool system_backup_pin_output_get(enum system_backup_pin pin)
+{
+	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+
+	return (SUPC->BKIN.reg & SUPC_BKIN_BKIN(pin >> 1));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Device Sleep Control
+ * @{
+ */
+
+/**
+ * \brief Set the sleep mode of the device.
+ *
+ * Sets the sleep mode of the device; the configured sleep mode will be entered
+ * upon the next call of the \ref system_sleep() function.
+ *
+ * For an overview of which systems are disabled in sleep for the different
+ * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode.
+ *
+ * \param[in] sleep_mode  Sleep mode to configure for the next sleep operation
+ */
+static inline void system_set_sleepmode(
+	const enum system_sleepmode sleep_mode)
+{
+	PM->SLEEPCFG.reg = sleep_mode;
+	while(PM->SLEEPCFG.reg != sleep_mode) ;
+}
+
+/**
+ * \brief Put the system to sleep waiting for interrupt.
+ *
+ * Executes a device DSB (Data Synchronization Barrier) instruction to ensure
+ * all ongoing memory accesses have completed. Further, a WFI (Wait For Interrupt)
+ * instruction is executed to place the device into the sleep mode specified by
+ * \ref system_set_sleepmode.
+ */
+static inline void system_sleep(void)
+{
+	__DSB();
+	__WFI();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Performance Level Control
+ * @{
+ */
+
+/**
+ * \brief Switch performance level.
+ *
+ *  The bus frequency must be reduced prior to scaling down the performance level,
+ *  in order to not exceed the maximum frequency allowed for the performance level.
+ *
+ *  When scaling up the performance level (for example from PL0 to PL2), the bus
+ *  frequency can be increased first when the performance level transition is
+ *  completed. Check the performance level status before increasing the frequency.
+ *
+ * \param[in] performance_level  Performance level to switch
+ *
+ * \retval STATUS_ERR_INVALID_ARG  Invalid parameter
+ * \retval STATUS_OK               Successfully
+ */
+static inline enum status_code system_switch_performance_level(
+					const enum system_performance_level performance_level)
+{
+
+	if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
+		return STATUS_OK;
+	}
+
+#if SAML22 || SAML21XXXB || SAMR34J || SAMR35J || (WLR089U0)
+	if (PM->PLCFG.reg & PM_PLCFG_PLDIS) {
+		return STATUS_ERR_INVALID_ARG;
+	}
+#endif
+
+	/* Clear performance level status */
+	PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
+
+	/* Switch performance level */
+	PM->PLCFG.reg = performance_level;
+
+	/* Waiting performance level ready */
+	while (!PM->INTFLAG.reg) {
+		;
+	}
+	return STATUS_OK;
+}
+
+#if SAML22 || SAML21XXXB || SAMR34J || SAMR35J || (WLR089U0)
+/**
+ * \brief Enable performance level switch.
+ *
+ * Enable performance level switch.
+ */
+static inline void system_performance_level_enable(void)
+{
+	PM->PLCFG.reg &= ~PM_PLCFG_PLDIS;
+}
+
+/**
+ * \brief Disable performance level switch.
+ *
+ * Disable performance level switch.
+ */
+static inline void system_performance_level_disable(void)
+{
+	PM->PLCFG.reg |= PM_PLCFG_PLDIS;
+}
+#endif
+
+/**
+ * \brief Get performance level.
+ *
+ * Get performance level.
+ *
+ * \return Current performance level.
+ */
+static inline enum system_performance_level system_get_performance_level(void)
+{
+	return (enum system_performance_level)PM->PLCFG.reg;
+}
+
+/**
+ * \brief Get performance level status.
+ *
+ * Get performance level status.
+ * \return Performance level status: Written to one when the performance level is ready.
+ */
+static inline uint8_t system_get_performance_level_status(void)
+{
+	return PM->INTFLAG.reg;
+}
+
+/**
+ * \brief Clear performance level status.
+ *
+ * Clear performance level status.
+ */
+static inline void system_clear_performance_level_status(void)
+{
+	PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Standby Configuration
+ * @{
+ */
+
+/**
+ * \brief Retrieve the default configuration for standby.
+ *
+ * Fills a configuration structure with the default configuration for standby:
+ *   - Retention back biasing mode for HMCRAMCLP
+ *   - Retention back biasing mode for HMCRAMCHS
+ *   - Power domains PD0/PD1/PD2 are not linked
+ *   - Automatic VREG switching is used
+ *   - Dynamic power gating for power domain 1 is disabled
+ *   - Dynamic power gating for power domain 0 is disabled
+ *   - All power domains switching are handled by hardware
+ *
+ * \param[out] config  Configuration structure to fill with default values
+ */
+static inline void system_standby_get_config_defaults(
+		struct system_standby_config *const config)
+{
+	Assert(config);
+#if SAML21 || SAMR30 || (SAMR34) || (SAMR35) || (WLR089)
+	config->power_domain        = SYSTEM_POWER_DOMAIN_DEFAULT;
+	config->enable_dpgpd0       = false;
+	config->enable_dpgpd1       = false;
+#if (SAML21XXXB) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+	config->vregs_mode          = SYSTEM_SYSTEM_VREG_SWITCH_AUTO;
+#else
+	config->disable_avregsd     = false;
+#endif
+	config->linked_power_domain = SYSTEM_LINKED_POWER_DOMAIN_DEFAULT;
+#elif SAML22
+	config->vreg_switch_mode    = SYSTEM_VREG_SWITCH_AUTO;
+#endif
+	config->hmcramchs_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION;
+	config->hmcramclp_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION;
+}
+
+/**
+ * \brief Configure standby mode.
+ *
+ * Configures standby with the given configuration.
+ *
+ * \param[in] config  Standby configuration structure containing
+ *                    the new config
+ */
+static inline void system_standby_set_config(
+		struct system_standby_config *const config)
+{
+	Assert(config);
+#if SAML21 || SAMR30 || (SAMR34) || (SAMR35) || (WLR089)
+	PM->STDBYCFG.reg = PM_STDBYCFG_PDCFG(config->power_domain)
+					 | (config->enable_dpgpd0 << PM_STDBYCFG_DPGPD0_Pos)
+					 | (config->enable_dpgpd1 << PM_STDBYCFG_DPGPD1_Pos)
+#if (SAML21XXXB) || (SAMR30) || (SAMR34) || (SAMR35) || (WLR089)
+					 | PM_STDBYCFG_VREGSMOD(config->vregs_mode)
+#else
+					 | (config->disable_avregsd << PM_STDBYCFG_AVREGSD_Pos)
+#endif
+					 | PM_STDBYCFG_LINKPD(config->linked_power_domain)
+					 | PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias)
+					 | PM_STDBYCFG_BBIASLP(config->hmcramclp_back_bias);
+#elif SAML22
+	PM->STDBYCFG.reg = PM_STDBYCFG_VREGSMOD(config->vreg_switch_mode) |
+					 PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias);
+#endif
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name I/O Retention
+ * @{
+ */
+
+/**
+ * \brief Enable I/O retention.
+ *
+ *  Enable I/O retention. After waking up from Backup mode, I/O lines are held
+ *  until the bit is written to 0.
+ */
+static inline void system_io_retension_enable(void)
+{
+	PM->CTRLA.reg = PM_CTRLA_IORET;
+}
+
+/**
+ * \brief Disable I/O retention.
+ *
+ * Disable IO retention. After waking up from Backup mode, I/O lines are not held.
+ */
+static inline void system_io_retension_disable(void)
+{
+	PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET);
+}
+
+/**
+ * @}
+ */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* POWER_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/reset/reset_sam_l/reset.h

@@ -0,0 +1,255 @@
+/**
+ * \file
+ *
+ * \brief SAM Reset functionality
+ *
+ * Copyright (c) 2014-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef RESET_H_INCLUDED
+#define RESET_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup asfdoc_sam0_system_group
+ * @{
+ */
+
+/**
+ * \brief Reset causes of the system.
+ *
+ * List of possible reset causes of the system.
+ */
+enum system_reset_cause {
+	/** The system was last reset by a backup reset */
+	SYSTEM_RESET_CAUSE_BACKUP         = RSTC_RCAUSE_BACKUP,
+	/** The system was last reset by a software reset */
+	SYSTEM_RESET_CAUSE_SOFTWARE       = RSTC_RCAUSE_SYST,
+	/** The system was last reset by the watchdog timer */
+	SYSTEM_RESET_CAUSE_WDT            = RSTC_RCAUSE_WDT,
+	/** The system was last reset because the external reset line was pulled low */
+	SYSTEM_RESET_CAUSE_EXTERNAL_RESET = RSTC_RCAUSE_EXT,
+#if SAML21 || SAMR30 || (SAMR34) || (SAMR35) || (WLR089)
+	/** The system was last reset by the BOD33. */
+	SYSTEM_RESET_CAUSE_BOD33          = RSTC_RCAUSE_BOD33,
+	/** The system was last reset by the BOD12 */
+	SYSTEM_RESET_CAUSE_BOD12          = RSTC_RCAUSE_BOD12,
+#else
+	/** The system was last reset by the BOD VDD. */
+	SYSTEM_RESET_CAUSE_BOD33          = RSTC_RCAUSE_BODVDD,
+	/** The system was last reset by the BOD CORE. */
+	SYSTEM_RESET_CAUSE_BOD12          = RSTC_RCAUSE_BODCORE,
+#endif
+	/** The system was last reset by the POR (Power on reset). */
+	SYSTEM_RESET_CAUSE_POR            = RSTC_RCAUSE_POR,
+};
+
+/**
+ * \brief Backup exit source after a backup reset occurs.
+ *
+ * List of possible backup exit source.
+ */
+enum system_reset_backup_exit_source {
+#if SAML21 || SAMR30 || (SAMR34) || (SAMR35) || (WLR089)
+	/** The backup exit source was external wakeup. */
+	SYSTEM_RESET_BACKKUP_EXIT_EXTWAKE    = RSTC_BKUPEXIT_EXTWAKE,
+#endif
+	/** The backup exit source was RTC interrupt. */
+	SYSTEM_RESET_BACKKUP_EXIT_RTC        = RSTC_BKUPEXIT_RTC,
+	/** The backup exit source was battery backup power switch */
+	SYSTEM_RESET_BACKKUP_EXIT_BBPS       = RSTC_BKUPEXIT_BBPS,
+};
+
+#if SAML21 || SAMR30 || (SAMR34) || (SAMR35) || (WLR089)
+/**
+ * \brief Wakeup debounce counter value.
+ *
+ * Wakeup debounce counter value when waking up by external wakeup pin from backup mode.
+ */
+enum system_wakeup_debounce_count {
+	/** No debouncing */
+	SYSTEM_WAKEUP_DEBOUNCE_OFF         = RSTC_WKDBCONF_WKDBCNT_OFF,
+	/** Input pin shall be active for at least two 32KHz clock period. */
+	SYSTEM_WAKEUP_DEBOUNCE_2CK32       = RSTC_WKDBCONF_WKDBCNT_2CK32,
+	/** Input pin shall be active for at least three 32KHz clock period. */
+	SYSTEM_WAKEUP_DEBOUNCE_3CK32       = RSTC_WKDBCONF_WKDBCNT_3CK32,
+	/** Input pin shall be active for at least 32 32KHz clock periods */
+	SYSTEM_WAKEUP_DEBOUNCE_32CK32      = RSTC_WKDBCONF_WKDBCNT_32CK32,
+	/** Input pin shall be active for at least 512 32KHz clock periods */
+	SYSTEM_WAKEUP_DEBOUNCE_512CK32     = RSTC_WKDBCONF_WKDBCNT_512CK32,
+	/** Input pin shall be active for at least 4096 32KHz clock periods */
+	SYSTEM_WAKEUP_DEBOUNCE_4096CK32    = RSTC_WKDBCONF_WKDBCNT_4096CK32,
+	/** Input pin shall be active for at least 32768 32KHz clock periods */
+	SYSTEM_WAKEUP_DEBOUNCE_32768CK32   = RSTC_WKDBCONF_WKDBCNT_32768CK32,
+};
+#endif
+
+/**
+ * \name Reset Control
+ * @{
+ */
+
+/**
+ * \brief Reset the MCU.
+ *
+ * Resets the MCU and all associated peripherals and registers, except RTC,
+ * OSC32KCTRL, RSTC, GCLK (if WRTLOCK is set), and I/O retention state of PM.
+ *
+ */
+static inline void system_reset(void)
+{
+	NVIC_SystemReset();
+}
+
+/**
+ * \brief Get the reset cause.
+ *
+ * Retrieves the cause of the last system reset.
+ *
+ * \return An enum value indicating the cause of the last system reset.
+ */
+static inline enum system_reset_cause system_get_reset_cause(void)
+{
+	return (enum system_reset_cause)RSTC->RCAUSE.reg;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name Backup Exit Control
+ * @{
+ */
+
+/**
+ * \brief Get the backup exit source.
+ *
+ * Get the backup exit source when a backup reset occurs.
+ *
+ * \return An enum value indicating the latest backup exit source.
+ */
+static inline enum system_reset_backup_exit_source system_get_backup_exit_source(void)
+{
+	return (enum system_reset_backup_exit_source)RSTC->BKUPEXIT.reg;
+}
+
+#if SAML21 || SAMR30 || (SAMR34) || (SAMR35) || (WLR089)
+/**
+ * \brief Set wakeup debounce counter.
+ *
+ * Set the wakeup debounce counter value with the given count.
+ *
+ * \param[in] wakeup_debounce_count Wakeup debounce counter value
+ */
+static inline void system_set_pin_wakeup_debounce_counter(
+					const enum system_wakeup_debounce_count wakeup_debounce_count)
+{
+	RSTC->WKDBCONF.reg = wakeup_debounce_count;
+}
+
+/**
+ * \brief Set low polarity of wakeup input pin.
+ *
+ * Set low polarity with the given wakeup input pin mask.
+ *
+ * \param[in] pin_mask Input pin mask
+ */
+static inline void system_set_pin_wakeup_polarity_low(const uint16_t pin_mask)
+{
+	RSTC->WKPOL.reg &= ~(RSTC_WKPOL_WKPOL(pin_mask));
+}
+
+/**
+ * \brief Set high polarity of wakeup input pin.
+ *
+ * Set high polarity with the given wakeup input pin mask.
+ *
+ * \param[in] pin_mask Input pin mask
+ */
+static inline void system_set_pin_wakeup_polarity_high(const uint16_t pin_mask)
+{
+	RSTC->WKPOL.reg |= RSTC_WKPOL_WKPOL(pin_mask);
+}
+
+/**
+ * \brief Enable wakeup of input pin from the backup mode.
+ *
+ * Enable pin wakeup from the backup mode with the given pin mask.
+ *
+ * \param[in] pin Input pin mask
+ */
+static inline void system_enable_pin_wakeup(const uint16_t pin_mask)
+{
+	RSTC->WKEN.reg |= RSTC_WKEN_WKEN(pin_mask);
+}
+
+/**
+ * \brief Disable wakeup of input pin from the backup mode.
+ *
+ * Disable pin wakeup from the backup mode with the given pin mask.
+ *
+ * \param[in] pin Input pin mask
+ */
+static inline void system_disable_pin_wakeup(const uint16_t pin_mask)
+{
+	RSTC->WKEN.reg &= ~(RSTC_WKEN_WKEN(pin_mask));
+}
+
+/**
+ * \brief Check whether any of the enabled wake up pins are active and caused the wakeup.
+ *
+ * Check whether any of the enabled wake up pins are active and caused the wakeup
+ *  from backup sleep mode when exiting backup mode.
+ *
+ * \return Pin mask, the corresponding pin is active when its pin mask is 1.
+ */
+static inline uint16_t system_get_pin_wakeup_cause(void)
+{
+	return (RSTC_WKCAUSE_MASK & (RSTC->WKCAUSE.reg >> RSTC_WKCAUSE_WKCAUSE_Pos));
+}
+#endif
+/**
+ * @}
+ */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RESET_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/system.c

@@ -0,0 +1,101 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <system.h>
+
+/**
+ * \internal
+ * Dummy initialization function, used as a weak alias target for the various
+ * init functions called by \ref system_init().
+ */
+void _system_dummy_init(void);
+void _system_dummy_init(void)
+{
+	return;
+}
+
+#if !defined(__DOXYGEN__)
+#  if defined(__GNUC__)
+void system_clock_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_events_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_extint_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+void _system_divas_init(void) WEAK __attribute__((alias("_system_dummy_init")));
+#  elif defined(__ICCARM__)
+void system_clock_init(void);
+void system_board_init(void);
+void _system_events_init(void);
+void _system_extint_init(void);
+void _system_divas_init(void);
+#    pragma weak system_clock_init=_system_dummy_init
+#    pragma weak system_board_init=_system_dummy_init
+#    pragma weak _system_events_init=_system_dummy_init
+#    pragma weak _system_extint_init=_system_dummy_init
+#    pragma weak _system_divas_init=_system_dummy_init
+#  endif
+#endif
+
+/**
+ * \brief Initialize system
+ *
+ * This function will call the various initialization functions within the
+ * system namespace. If a given optional system module is not available, the
+ * associated call will effectively be a NOP (No Operation).
+ *
+ * Currently the following initialization functions are supported:
+ *  - System clock initialization (via the SYSTEM CLOCK sub-module)
+ *  - Board hardware initialization (via the Board module)
+ *  - Event system driver initialization (via the EVSYS module)
+ *  - External Interrupt driver initialization (via the EXTINT module)
+ */
+void system_init(void)
+{
+	/* Configure GCLK and clock sources according to conf_clocks.h */
+	system_clock_init();
+
+	/* Initialize board hardware */
+	system_board_init();
+
+	/* Initialize EVSYS hardware */
+	_system_events_init();
+
+	/* Initialize External hardware */
+	_system_extint_init();
+	
+	/* Initialize DIVAS hardware */
+	_system_divas_init();
+}
+

firmware/SendcommCmdsys/src/ASF/sam0/drivers/system/system.h

@@ -0,0 +1,721 @@
+/**
+ * \file
+ *
+ * \brief SAM System related functionality
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef SYSTEM_H_INCLUDED
+#define SYSTEM_H_INCLUDED
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+#include <pinmux.h>
+#include <power.h>
+#include <reset.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup asfdoc_sam0_system_group SAM System (SYSTEM) Driver
+ *
+ * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
+ * and management of the device's system relation functionality, necessary for
+ * the basic device operation. This is not limited to a single peripheral, but
+ * extends across multiple hardware peripherals.
+ *
+ * The following peripherals are used by this module:
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  - PM (Power Manager)
+ *  - RSTC (Reset Controller)
+ *  - SUPC (Supply Controller)
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  - PM (Power Manager)
+ *  - RSTC (Reset Controller)
+ *  - SUPC (Supply Controller)
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  - SYSCTRL (System Control)
+ *  - PM (Power Manager)
+ * \endif
+ *
+ * The following devices can use this module:
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM L21
+ *  - Atmel | SMART SAM R30
+ *  - Atmel | SMART SAM R34
+ *  - Atmel | SMART SAM R35
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM C20/C21
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  - Atmel | SMART SAM D20/D21
+ *  - Atmel | SMART SAM R21
+ *  - Atmel | SMART SAM D09/D10/D11
+ *  - Atmel | SMART SAM DA1
+ * \endif
+ *
+ * The outline of this documentation is as follows:
+ *  - \ref asfdoc_sam0_system_prerequisites
+ *  - \ref asfdoc_sam0_system_module_overview
+ *  - \ref asfdoc_sam0_system_special_considerations
+ *  - \ref asfdoc_sam0_system_extra_info
+ *  - \ref asfdoc_sam0_system_examples
+ *  - \ref asfdoc_sam0_system_api_overview
+ *
+ *
+ * \section asfdoc_sam0_system_prerequisites Prerequisites
+ *
+ * There are no prerequisites for this module.
+ *
+ *
+ * \section asfdoc_sam0_system_module_overview Module Overview
+ *
+ * The System driver provides a collection of interfaces between the user
+ * application logic, and the core device functionality (such as clocks, reset
+ * cause determination, etc.) that is required for all applications. It contains
+ * a number of sub-modules that control one specific aspect of the device:
+ *
+ * - System Core (this module)
+ * - \ref asfdoc_sam0_system_clock_group "System Clock Control" (sub-module)
+ * - \ref asfdoc_sam0_system_interrupt_group "System Interrupt Control" (sub-module)
+ * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Control" (sub-module)
+ *
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * \subsection asfdoc_sam0_system_module_overview_vreg_l21 Voltage Regulator
+ * The SAM device controls the voltage regulators for the core (VDDCORE) and
+ * backup (VDDBU) domains. It sets the voltage regulators according to the sleep
+ * modes, the performance level, or the user configuration.
+ *
+ * In active mode, the voltage regulator can be chosen on the fly between a LDO
+ * or a Buck converter. In standby mode, the low power voltage regulator is used
+ * to supply VDDCORE.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_bbps Battery Backup Power Switch
+ * The SAM device supports connection of a battery backup to the VBAT power pin.
+ * It includes functionality that enables automatic power switching between main
+ * power and battery backup power. This will ensure power to the backup domain,
+ * when the main battery or power source is unavailable.
+ * \endif
+ *
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ * \subsection asfdoc_sam0_system_module_overview_vreg_c21 Voltage Regulator
+ * The SAM device controls the voltage regulators for the core (VDDCORE). It sets
+ * the voltage regulators according to the sleep modes.
+ *
+ * There are a selectable reference voltage and voltage dependent on the temperature
+ * which can be used by analog modules like the ADC.
+ * \endif
+ *
+ * \subsection asfdoc_sam0_system_module_overview_vref Voltage References
+ * The various analog modules within the SAM devices (such as AC, ADC, and
+ * DAC) require a voltage reference to be configured to act as a reference point
+ * for comparisons and conversions.
+ *
+ * The SAM devices contain multiple references, including an internal
+ * temperature sensor and a fixed band-gap voltage source. When enabled, the
+ * associated voltage reference can be selected within the desired peripheral
+ * where applicable.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_reset_cause System Reset Cause
+ * In some applications there may be a need to execute a different program
+ * flow based on how the device was reset. For example, if the cause of reset
+ * was the Watchdog timer (WDT), this might indicate an error in the application,
+ * and a form of error handling or error logging might be needed.
+ *
+ * For this reason, an API is provided to retrieve the cause of the last system
+ * reset, so that appropriate action can be taken.
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * There are three groups of reset sources:
+ *   - Power supply reset: Resets caused by an electrical issue. It covers POR and BOD reset.
+ *   - User reset: Resets caused by the application. It covers external reset,
+ *             system reset, and watchdog reset.
+ *   - Backup reset: Resets caused by a backup mode exit condition.
+ *
+ * \subsection asfdoc_sam0_system_module_overview_performance_level Performance Level
+ * Performance level allows the user to adjust the regulator output voltage to reduce
+ * power consumption. The user can on the fly select the most suitable performance
+ * level, depending on the application demands.
+ *
+ * The SAM device can operate at two different performance levels (PL0 and PL2).
+ * When operating at PL0, the voltage applied on the full logic area is reduced
+ * by voltage scaling. This voltage scaling technique allows to reduce the active
+ * power consumption while decreasing the maximum frequency of the device. When
+ * operating at PL2, the voltage regulator supplies the highest voltage, allowing
+ * the device to run at higher clock speeds.
+ *
+ * Performance level transition is possible only when the device is in active
+ * mode. After a reset, the device starts at the lowest performance level
+ * (lowest power consumption and lowest max. frequency). The application can then
+ * switch to another performance level at any time without any stop in the code
+ * execution. As shown in \ref asfdoc_sam0_system_performance_level_transition_figure.
+ *
+ * \note When scaling down the performance level, the bus frequency should first be
+ *  scaled down in order to not exceed the maximum frequency allowed for the
+ *  low performance level.
+ *  When scaling up the performance level (e.g. from PL0 to PL2), check the performance
+ *  level status before increasing the bus frequency. It can be increased only
+ *  when the performance level transition is completed.
+ *
+ * \anchor asfdoc_sam0_system_performance_level_transition_figure
+ * \image html performance_level_transition.svg "Performance Level Transition"
+ *
+ * \subsection asfdoc_sam0_system_module_overview_power_domain Power Domain Gating
+ * Power domain gating allows power saving by reducing the voltage in logic
+ * areas in the device to a low-power supply. The feature is available in
+ * Standby sleep mode and will reduce the voltage in domains where all peripherals
+ * are idle. Internal logic will maintain its content, meaning the corresponding
+ * peripherals will not need to be reconfigured when normal operating voltage
+ * is returned. Most power domains can be in the following three states:
+ *
+ * - Active state: The power domain is powered on.
+ * - Retention state: The main voltage supply for the power domain is switched off,
+ * while maintaining a secondary low-power supply for the sequential cells. The
+ * logic context is restored when waking up.
+ * - Off state: The power domain is entirely powered off. The logic context is lost.
+ *
+ * The SAM L21 device  contains three power domains which can be controlled using
+ * power domain gating, namely PD0, PD1, and PD2. These power domains can be
+ * configured to the following cases:
+ * - Default with no sleepwalking peripherals: A power domain is automatically set
+ * to retention state in standby sleep mode if no activity require it. The application
+ * can force all power domains to remain in active state during standby sleep mode
+ * in order to accelerate wakeup time.
+ * - Default with sleepwalking peripherals: If one or more peripherals are enabled
+ * to perform sleepwalking tasks in standby sleep mode, the corresponding power
+ * domain (PDn) remains in active state as well as all inferior power domains (<PDn).
+ * - Sleepwalking with dynamic power domain gating: During standby sleep mode, a
+ * power domain (PDn) in active can wake up a superior power domain (>PDn) in order
+ * to perform a sleepwalking task. The superior power domain is then automatically
+ * set to active state. At the end of the sleepwalking task, the device can either
+ * be woken up or the superior power domain can return to retention state.
+ *
+ * Power domains can be linked to each other, it allows a power domain (PDn) to be kept
+ * in active state if the inferior power domain (PDn-1) is in active state too.
+ *
+ * \ref asfdoc_sam0_system_power_domain_overview_table illustrates the
+ * four cases to consider in standby mode.
+ *
+ * \anchor asfdoc_sam0_system_power_domain_overview_table
+ * <table>
+ *  <caption>Sleep Mode versus Power Domain State Overview</caption>
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>PD0</th>
+ *      <th>PD1</th>
+ *      <th>PD2</th>
+ *      <th>PDTOP</th>
+ *      <th>PDBACKUP</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 1</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 2</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 3</td>
+ *      <td>active</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby - Case 4</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>retention</td>
+ *      <td>active</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Backup</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>active</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *      <td>off</td>
+ *  </tr>
+ * </table>
+ *
+ * \subsection asfdoc_sam0_system_module_overview_ram_state RAMs Low Power Mode
+ * By default, in standby sleep mode, RAM is in low power mode (back biased)
+ * if its power domain is in retention state.
+ * \ref asfdoc_sam0_system_power_ram_state_table lists RAMs low power mode.
+ *
+ * \anchor asfdoc_sam0_system_power_ram_state_table
+ * <table>
+ *  <caption>RAM Back-biasing Mode</caption>
+ *  <tr>
+ *      <th>RAM mode</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Retention Back-biasing mode</td>
+ *      <td>RAM is back-biased if its power domain is in retention mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby Back-biasing mode</td>
+ *      <td>RAM is back-biased if the device is in standby mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby OFF mode</td>
+ *      <td>RAM is OFF if the device is in standby mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Always OFF mode</td>
+ *      <td>RAM is OFF if the device is in RET mode</td>
+ *  </tr>
+ * </table>
+ *
+ * \endif
+ *
+ * \subsection asfdoc_sam0_system_module_overview_sleep_mode Sleep Modes
+ * The SAM devices have several sleep modes. The sleep mode controls
+ * which clock systems on the device will remain enabled or disabled when the
+ * device enters a low power sleep mode.
+ * \ref asfdoc_sam0_system_module_sleep_mode_table "The table below" lists the
+ * clock settings of the different sleep modes.
+ *
+ * \anchor asfdoc_sam0_system_module_sleep_mode_table
+ * <table>
+ *  <caption>SAM Device Sleep Modes</caption>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>System clock</th>
+ *      <th>CPU clock</th>
+ *      <th>AHB/AHB clock</th>
+ *      <th>GCLK clocks</th>
+ *      <th>Oscillators (ONDEMAND  = 0)</th>
+ *      <th>Oscillators (ONDEMAND  = 1)</th>
+ *      <th>Regulator mode</th>
+ *      <th>RAM mode</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle</td>
+ *      <td>Run</td>
+ *      <td>Stop</td>
+ *      <td>Run if requested</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run if requested</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run if requested</td>
+ *      <td>Run if requested</td>
+ *      <td>Run if requested or RUNSTDBY  = 1</td>
+ *      <td>Run if requested</td>
+ *      <td>Low pwer</td>
+ *      <td>Low pwer</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Backup</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Backup</td>
+ *      <td>Off</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *      <td>Off</td>
+ *  </tr>
+ * \else
+ *  <tr>
+ *      <th>Sleep mode</th>
+ *      <th>CPU clock</th>
+ *      <th>AHB clock</th>
+ *      <th>APB clocks</th>
+ *      <th>Clock sources</th>
+ *      <th>System clock</th>
+ *      <th>32KHz</th>
+ *      <th>Reg mode</th>
+ *      <th>RAM mode</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 0</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 1</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Idle 2</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Run</td>
+ *      <td>Normal</td>
+ *      <td>Normal</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Standby</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Stop</td>
+ *      <td>Low Power</td>
+ *      <td>Source/Drain biasing</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ * Before entering device sleep, one of the available sleep modes must be set.
+ * The device will automatically wake up in response to an interrupt being
+ * generated or upon any other sleep mode exit condition.
+ *
+ * Some peripheral clocks will remain enabled during sleep, depending on their
+ * configuration. If desired, the modules can remain clocked during sleep to allow
+ * them continue to operate while other parts of the system are powered down
+ * to save power.
+ *
+ *
+ * \section asfdoc_sam0_system_special_considerations Special Considerations
+ *
+ * Most of the functions in this driver have device specific restrictions and
+ * caveats; refer to your device datasheet.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_info Extra Information
+ *
+ * For extra information, see \ref asfdoc_sam0_system_extra. This includes:
+ *  - \ref asfdoc_sam0_system_extra_acronyms
+ *  - \ref asfdoc_sam0_system_extra_dependencies
+ *  - \ref asfdoc_sam0_system_extra_errata
+ *  - \ref asfdoc_sam0_system_extra_history
+ *
+ *
+ * \section asfdoc_sam0_system_examples Examples
+ *
+ * For SYSTEM module related examples, refer to the sub-modules listed in
+ * the \ref asfdoc_sam0_system_module_overview "Module Overview".
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * For a list of examples related to this driver, see
+ * \ref asfdoc_sam0_drivers_power_exqsg.
+ * \endif
+ *
+ *
+ * \section asfdoc_sam0_system_api_overview API Overview
+ * @{
+ */
+
+/**
+ * \name System Debugger
+ * @{
+ */
+
+/**
+ * \brief Check if debugger is present.
+ *
+ * Check if debugger is connected to the onboard debug system (DAP).
+ *
+ * \return A bool identifying if a debugger is present.
+ *
+ * \retval true  Debugger is connected to the system
+ * \retval false Debugger is not connected to the system
+ *
+ */
+static inline bool system_is_debugger_present(void)
+{
+	return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Identification
+ * @{
+ */
+
+/**
+ * \brief Retrieve the device identification signature.
+ *
+ * Retrieves the signature of the current device.
+ *
+ * \return Device ID signature as a 32-bit integer.
+ */
+static inline uint32_t system_get_device_id(void)
+{
+	return DSU->DID.reg;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * \name System Initialization
+ * @{
+ */
+
+void system_init(void);
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ *
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ * \page asfdoc_sam0_drivers_power_exqsg Examples for SYSTEM Driver
+ *
+ * This is a list of the available Quick Start Guides (QSGs) and example
+ * applications for \ref asfdoc_sam0_system_group. QSGs are simple examples with step-by-step instructions to
+ * configure and use this driver in a selection of
+ * use cases. Note that a QSG can be compiled as a standalone application or be
+ * added to the user application.
+ *
+ *  - \subpage asfdoc_sam0_power_basic_use_case
+ * \endif
+ *
+ * \page asfdoc_sam0_system_extra Extra Information for SYSTEM Driver
+ *
+ * \section asfdoc_sam0_system_extra_acronyms Acronyms
+ * Below is a table listing the acronyms used in this module, along with their
+ * intended meanings.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Definition</th>
+ *  </tr>
+ *  <tr>
+ *      <td>PM</td>
+ *      <td>Power Manager</td>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SUPC</td>
+ *      <td>Supply Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RSTC</td>
+ *      <td>Reset Controller</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SUPC</td>
+ *      <td>Supply Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RSTC</td>
+ *      <td>Reset Controller</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>SYSCTRL</td>
+ *      <td>System control interface</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ *
+ * \section asfdoc_sam0_system_extra_dependencies Dependencies
+ * This driver has the following dependencies:
+ *
+ *  - None
+ *
+ *
+ * \section asfdoc_sam0_system_extra_errata Errata
+ * There are no errata related to this driver.
+ *
+ *
+ * \section asfdoc_sam0_system_extra_history Module History
+ * An overview of the module history is presented in the table below, with
+ * details on the enhancements and fixes made to the module since its first
+ * release. The current version of this corresponds to the newest version in
+ * the table.
+ *
+ * <table>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>Added new \c system_reset() to reset the complete MCU with some exceptions</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added new \c system_get_device_id() function to retrieved the device
+ *          ID</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
+ * \endif
+ * </table>
+ *
+ * \page asfdoc_sam0_system_document_revision_history Document Revision History
+ *
+ * <table>
+ * <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ * \if DEVICE_SAML21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42449A</td>
+ *      <td>07/2015</td>
+ *      <td>Initial document release</td>
+ * </tr>
+ * \endif
+ * \if DEVICE_SAMC21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42484A</td>
+ *      <td>12/2015</td>
+ *      <td>Initial document release.</td>
+ * </tr>
+ * \endif
+ * \if DEVICE_SAMD21_SYSTEM_SUPPORT
+ *  <tr>
+ *      <td>42120E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM DA1 and SAM D09</td>
+ * </tr>
+ *  <tr>
+ *      <td>42120D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ * </tr>
+ * <tr>
+ *      <td>42120C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42120B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42120A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial document release</td>
+ *  </tr>
+ * \endif
+ * </table>
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_H_INCLUDED */
+

firmware/SendcommCmdsys/src/ASF/sam0/drivers/tc/tc_interrupt.c

@@ -0,0 +1,189 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Callback Driver
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "tc_interrupt.h"
+
+void *_tc_instances[TC_INST_NUM];
+
+void _tc_interrupt_handler(uint8_t instance);
+
+/**
+ * \brief Registers a callback.
+ *
+ * Registers a callback function which is implemented by the user.
+ *
+ * \note The callback must be enabled by \ref tc_enable_callback,
+ * in order for the interrupt handler to call it when the conditions for the
+ * callback type is met.
+ *
+ * \param[in]     module        Pointer to TC software instance struct
+ * \param[in]     callback_func Pointer to callback function
+ * \param[in]     callback_type Callback type given by an enum
+ */
+enum status_code tc_register_callback(
+		struct tc_module *const module,
+		tc_callback_t callback_func,
+		const enum tc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+	Assert(callback_func);
+
+	/* Register callback function */
+	module->callback[callback_type] = callback_func;
+
+	/* Set the bit corresponding to the callback_type */
+	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+		module->register_callback_mask |= TC_INTFLAG_MC(1);
+	}
+	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+		module->register_callback_mask |= TC_INTFLAG_MC(2);
+	}
+	else {
+		module->register_callback_mask |= (1 << callback_type);
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \brief Unregisters a callback.
+ *
+ * Unregisters a callback function implemented by the user. The callback should be
+ * disabled before it is unregistered.
+ *
+ * \param[in]     module        Pointer to TC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+enum status_code tc_unregister_callback(
+		struct tc_module *const module,
+		const enum tc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Unregister callback function */
+	module->callback[callback_type] = NULL;
+
+	/* Clear the bit corresponding to the callback_type */
+	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+		module->register_callback_mask &= ~TC_INTFLAG_MC(1);
+	}
+	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+		module->register_callback_mask &= ~TC_INTFLAG_MC(2);
+	}
+	else {
+		module->register_callback_mask &= ~(1 << callback_type);
+	}
+	return STATUS_OK;
+}
+
+/**
+ * \internal ISR handler for TC
+ *
+ * Auto-generate a set of interrupt handlers for each TC in the device.
+ */
+#define _TC_INTERRUPT_HANDLER(n, m) \
+		void TC##n##_Handler(void) \
+		{ \
+			_tc_interrupt_handler(m); \
+		}
+
+#if (SAML21E) || (SAML21G) || (SAMR30E) || (SAMR30G)
+	_TC_INTERRUPT_HANDLER(0,0)
+	_TC_INTERRUPT_HANDLER(1,1)
+	_TC_INTERRUPT_HANDLER(4,2)
+#else
+	MRECURSION(TC_INST_NUM, _TC_INTERRUPT_HANDLER, TC_INST_MAX_ID)
+#endif
+
+
+/**
+ * \internal Interrupt Handler for TC module
+ *
+ * Handles interrupts as they occur, it will run the callback functions
+ * that are registered and enabled.
+ *
+ * \param[in]  instance  ID of the TC instance calling the interrupt
+ *                       handler
+ */
+void _tc_interrupt_handler(
+		uint8_t instance)
+{
+	/* Temporary variable */
+	uint8_t interrupt_and_callback_status_mask;
+
+	/* Get device instance from the look-up table */
+	struct tc_module *module
+			= (struct tc_module *)_tc_instances[instance];
+
+	/* Read and mask interrupt flag register */
+	interrupt_and_callback_status_mask = module->hw->COUNT8.INTFLAG.reg &
+			module->register_callback_mask &
+			module->enable_callback_mask;
+
+	/* Check if an Overflow interrupt has occurred */
+	if (interrupt_and_callback_status_mask & TC_INTFLAG_OVF) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[TC_CALLBACK_OVERFLOW])(module);
+		/* Clear interrupt flag */
+		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF;
+	}
+
+	/* Check if an Error interrupt has occurred */
+	if (interrupt_and_callback_status_mask & TC_INTFLAG_ERR) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[TC_CALLBACK_ERROR])(module);
+		/* Clear interrupt flag */
+		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR;
+	}
+
+	/* Check if an Match/Capture Channel 0 interrupt has occurred */
+	if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(1)) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[TC_CALLBACK_CC_CHANNEL0])(module);
+		/* Clear interrupt flag */
+		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(1);
+	}
+
+	/* Check if an Match/Capture Channel 1 interrupt has occurred */
+	if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(2)) {
+		/* Invoke registered and enabled callback function */
+		(module->callback[TC_CALLBACK_CC_CHANNEL1])(module);
+		/* Clear interrupt flag */
+		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(2);
+	}
+}

firmware/SendcommCmdsys/src/ASF/sam0/drivers/tc/tc_interrupt.h

@@ -0,0 +1,169 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Callback Driver
+ *
+ * Copyright (c) 2013-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef TC_INTERRUPT_H_INCLUDED
+#define TC_INTERRUPT_H_INCLUDED
+
+#include "tc.h"
+#include <system_interrupt.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__DOXYGEN__)
+extern void *_tc_instances[TC_INST_NUM];
+
+#  define _TC_INTERRUPT_VECT_NUM(n, unused) \
+		  SYSTEM_INTERRUPT_MODULE_TC##n,
+/**
+ * \internal Get the interrupt vector for the given device instance
+ *
+ * \param[in] TC module instance number
+ *
+ * \return Interrupt vector for of the given TC module instance.
+ */
+static enum system_interrupt_vector _tc_interrupt_get_interrupt_vector(
+		uint32_t inst_num)
+{
+	static uint8_t tc_interrupt_vectors[TC_INST_NUM] =
+		{
+#if (SAML21E) || (SAML21G) || (SAMR30E) || (SAMR30G)
+			SYSTEM_INTERRUPT_MODULE_TC0,
+			SYSTEM_INTERRUPT_MODULE_TC1,
+			SYSTEM_INTERRUPT_MODULE_TC4
+#else
+			MRECURSION(TC_INST_NUM, _TC_INTERRUPT_VECT_NUM, TC_INST_MAX_ID)
+#endif
+		};
+
+	return (enum system_interrupt_vector)tc_interrupt_vectors[inst_num];
+}
+#endif /* !defined(__DOXYGEN__) */
+
+/**
+ * \name Callback Management
+ * {@
+ */
+
+enum status_code tc_register_callback(
+		struct tc_module *const module,
+		tc_callback_t callback_func,
+		const enum tc_callback callback_type);
+
+enum status_code tc_unregister_callback(
+		struct tc_module *const module,
+		const enum tc_callback callback_type);
+
+/**
+ * \brief Enables callback.
+ *
+ * Enables the callback function registered by the \ref
+ * tc_register_callback. The callback function will be called from the
+ * interrupt handler when the conditions for the callback type are
+ * met. This function will also enable the appropriate interrupts.
+ *
+ * \param[in]     module        Pointer to TC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+static inline void tc_enable_callback(
+		struct tc_module *const module,
+		const enum tc_callback callback_type)
+{
+	/* Sanity check arguments */
+	Assert(module);
+
+
+	/* Enable interrupts for this TC module */
+	system_interrupt_enable(_tc_interrupt_get_interrupt_vector(_tc_get_inst_index(module->hw)));
+
+	/* Enable callback */
+	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+		module->enable_callback_mask |= TC_INTFLAG_MC(1);
+		module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(1);
+	}
+	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+		module->enable_callback_mask |= TC_INTFLAG_MC(2);
+		module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(2);
+	}
+	else {
+		module->enable_callback_mask |= (1 << callback_type);
+		module->hw->COUNT8.INTENSET.reg = (1 << callback_type);
+	}
+}
+
+/**
+ * \brief Disables callback.
+ *
+ * Disables the callback function registered by the \ref
+ * tc_register_callback, and the callback will not be called from the
+ * interrupt routine. The function will also disable the appropriate
+ * interrupts.
+ *
+ * \param[in]     module        Pointer to TC software instance struct
+ * \param[in]     callback_type Callback type given by an enum
+ */
+static inline void tc_disable_callback(
+		struct tc_module *const module,
+		const enum tc_callback callback_type){
+	/* Sanity check arguments */
+	Assert(module);
+
+	/* Disable callback */
+	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
+		module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1);
+		module->enable_callback_mask &= ~TC_INTFLAG_MC(1);
+	}
+	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
+		module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2);
+		module->enable_callback_mask &= ~TC_INTFLAG_MC(2);
+	}
+	else {
+		module->hw->COUNT8.INTENCLR.reg = (1 << callback_type);
+		module->enable_callback_mask &= ~(1 << callback_type);
+	}
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TC_INTERRUPT_H_INCLUDED */

firmware/SendcommCmdsys/src/ASF/sam0/drivers/tc/tc_sam_l_c/tc.c

@@ -0,0 +1,713 @@
+/**
+ * \file
+ *
+ * \brief SAM TC - Timer Counter Driver
+ *
+ * Copyright (c) 2014-2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "tc.h"
+
+#if TC_ASYNC == true
+#  include "tc_interrupt.h"
+#  include <system_interrupt.h>
+#endif
+
+/**
+ * \internal Find the index of given TC module instance.
+ *
+ * \param[in] TC module instance pointer
+ *
+ * \return Index of the given TC module instance.
+ */
+uint8_t _tc_get_inst_index(
+		Tc *const hw)
+{
+	/* List of available TC modules. */
+	Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
+
+	/* Find index for TC instance. */
+	for (uint32_t i = 0; i < TC_INST_NUM; i++) {
+		if (hw == tc_modules[i]) {
+			return i;
+		}
+	}
+
+	/* Invalid data given. */
+	Assert(false);
+	return 0;
+}
+
+
+/**
+ * \brief Initializes a hardware TC module instance.
+ *
+ * Enables the clock and initializes the TC module, based on the given
+ * configuration values.
+ *
+ * \param[in,out] module_inst  Pointer to the software module instance struct
+ * \param[in]     hw           Pointer to the TC hardware module
+ * \param[in]     config       Pointer to the TC configuration options struct
+ *
+ * \return Status of the initialization procedure.
+ *
+ * \retval STATUS_OK           The module was initialized successfully
+ * \retval STATUS_BUSY         Hardware module was busy when the
+ *                             initialization procedure was attempted
+ * \retval STATUS_INVALID_ARG  An invalid configuration option or argument
+ *                             was supplied
+ * \retval STATUS_ERR_DENIED   Hardware module was already enabled, or the
+ *                             hardware module is configured in 32-bit
+ *                             slave mode
+ */
+enum status_code tc_init(
+		struct tc_module *const module_inst,
+		Tc *const hw,
+		const struct tc_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(hw);
+	Assert(module_inst);
+	Assert(config);
+
+	/* Temporary variable to hold all updates to the CTRLA
+	 * register before they are written to it */
+	uint32_t ctrla_tmp = 0;
+	/* Temporary variable to hold all updates to the CTRLBSET
+	 * register before they are written to it */
+	uint8_t ctrlbset_tmp = 0;
+	/* Temporary variable to hold TC instance number */
+	uint8_t instance = _tc_get_inst_index(hw);
+
+#if (SAMC20) || (SAMC21)
+	/* Array of GLCK ID for different TC instances */
+	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID};
+	/* Array of MCLK APB mask bit position for different TC instances */
+	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC4};
+#elif (SAML21J) || (SAMR34J) || (SAMR35J) || (WLR089U0)
+	/* Array of GLCK ID for different TC instances */
+	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID};
+	/* Array of MCLK APB mask bit position for different TC instances */
+	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3,
+									SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4};
+#elif (SAML22)
+	/* Array of GLCK ID for different TC instances */
+	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID};
+	/* Array of MCLK APB mask bit position for different TC instances */
+	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3};
+#else
+	/* Array of GLCK ID for different TC instances */
+	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC4_GCLK_ID};
+	/* Array of PM APB mask bit position for different TC instances */
+	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+									SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4};
+#endif
+
+	struct system_pinmux_config pin_config;
+	struct system_gclk_chan_config gclk_chan_config;
+
+#if TC_ASYNC == true
+	/* Initialize parameters */
+	for (uint8_t i = 0; i < TC_CALLBACK_N; i++) {
+		module_inst->callback[i]        = NULL;
+	}
+	module_inst->register_callback_mask     = 0x00;
+	module_inst->enable_callback_mask       = 0x00;
+
+	/* Register this instance for callbacks*/
+	_tc_instances[instance] = module_inst;
+#endif
+
+	/* Associate the given device instance with the hardware module */
+	module_inst->hw = hw;
+
+	module_inst->double_buffering_enabled = config->double_buffering_enabled;
+
+	/* Check if odd numbered TC modules are being configured in 32-bit
+	 * counter size. Only even numbered counters are allowed to be
+	 * configured in 32-bit counter size.
+	 */
+	if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
+			((instance + TC_INSTANCE_OFFSET) & 0x01)) {
+		Assert(false);
+		return STATUS_ERR_INVALID_ARG;
+	}
+
+	/* Make the counter size variable in the module_inst struct reflect
+	 * the counter size in the module
+	 */
+	module_inst->counter_size = config->counter_size;
+
+	if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) {
+		/* We are in the middle of a reset. Abort. */
+		return STATUS_BUSY;
+	}
+
+	if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) {
+		/* Module is used as a slave */
+		return STATUS_ERR_DENIED;
+	}
+
+	if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) {
+		/* Module must be disabled before initialization. Abort. */
+		return STATUS_ERR_DENIED;
+	}
+
+	/* Set up the TC PWM out pin for channel 0 */
+	if (config->pwm_channel[0].enabled) {
+		system_pinmux_get_config_defaults(&pin_config);
+		pin_config.mux_position = config->pwm_channel[0].pin_mux;
+		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+		system_pinmux_pin_set_config(
+				config->pwm_channel[0].pin_out, &pin_config);
+	}
+
+	/* Set up the TC PWM out pin for channel 1 */
+	if (config->pwm_channel[1].enabled) {
+		system_pinmux_get_config_defaults(&pin_config);
+		pin_config.mux_position = config->pwm_channel[1].pin_mux;
+		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+		system_pinmux_pin_set_config(
+				config->pwm_channel[1].pin_out, &pin_config);
+	}
+
+	/* Enable the user interface clock in the MCLK */
+	system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[instance*2],
+			inst_mclk_apbmask[2*instance+1]);
+
+	/* Enable the slave counter if counter_size is 32-bit */
+	if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && (instance+1 < TC_INST_NUM))
+	{
+		/* Enable the user interface clock in the MCLK */
+		system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[(instance+1)*2],
+				inst_mclk_apbmask[(instance+1)*2+1]);
+	}
+
+
+	/* Setup clock for module */
+	system_gclk_chan_get_config_defaults(&gclk_chan_config);
+	gclk_chan_config.source_generator = config->clock_source;
+	system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config);
+	system_gclk_chan_enable(inst_gclk_id[instance]);
+
+	/* Set ctrla register */
+	ctrla_tmp =
+			(uint32_t)config->counter_size |
+			(uint32_t)config->reload_action |
+			(uint32_t)config->clock_prescaler;
+
+	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
+		if (config->enable_capture_on_channel[i] == true) {
+			ctrla_tmp |= (TC_CTRLA_CAPTEN(1) << i);
+		}
+	}
+
+	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
+		if (config->enable_capture_on_IO[i] == true) {
+			ctrla_tmp |= (TC_CTRLA_COPEN(1) << i);
+		}
+	}
+
+	ctrla_tmp |= (config->run_in_standby << TC_CTRLA_RUNSTDBY_Pos)
+				|(config->on_demand << TC_CTRLA_ONDEMAND_Pos);
+
+	/* Write configuration to register */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+	hw->COUNT8.CTRLA.reg = ctrla_tmp;
+
+	/* Write configuration to register */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+	hw->COUNT8.WAVE.reg = config->wave_generation;
+
+	/* Set ctrlb register */
+	if (config->oneshot) {
+		ctrlbset_tmp = TC_CTRLBSET_ONESHOT;
+	}
+
+	if (config->count_direction) {
+		ctrlbset_tmp |= TC_CTRLBSET_DIR;
+	}
+
+	/* Clear old ctrlb configuration */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+	hw->COUNT8.CTRLBCLR.reg = 0xFF;
+
+	/* Check if we actually need to go into a wait state. */
+	if (ctrlbset_tmp) {
+		while (tc_is_syncing(module_inst)) {
+			/* Wait for sync */
+		}
+		/* Write configuration to register */
+		hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp;
+	}
+
+	/* Set drvvtrl register*/
+	hw->COUNT8.DRVCTRL.reg = config->waveform_invert_output;
+
+	/* Write configuration to register */
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Switch for TC counter size  */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.COUNT.reg =
+					config->counter_8_bit.value;
+
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.PER.reg =
+					config->counter_8_bit.period;
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.CC[0].reg =
+					config->counter_8_bit.compare_capture_channel[0];
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT8.CC[1].reg =
+					config->counter_8_bit.compare_capture_channel[1];
+
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_16BIT:
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT16.COUNT.reg
+				= config->counter_16_bit.value;
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT16.CC[0].reg =
+					config->counter_16_bit.compare_capture_channel[0];
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT16.CC[1].reg =
+					config->counter_16_bit.compare_capture_channel[1];
+
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_32BIT:
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT32.COUNT.reg
+				= config->counter_32_bit.value;
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT32.CC[0].reg =
+					config->counter_32_bit.compare_capture_channel[0];
+
+			while (tc_is_syncing(module_inst)) {
+				/* Wait for sync */
+			}
+
+			hw->COUNT32.CC[1].reg =
+					config->counter_32_bit.compare_capture_channel[1];
+
+			return STATUS_OK;
+	}
+
+	Assert(false);
+	return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Sets TC module count value.
+ *
+ * Sets the current timer count value of a initialized TC module. The
+ * specified TC module may be started or stopped.
+ *
+ * \param[in] module_inst  Pointer to the software module instance struct
+ * \param[in] count        New timer count value to set
+ *
+ * \return Status of the count update procedure.
+ *
+ * \retval STATUS_OK               The timer count was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG  An invalid timer counter size was specified
+ */
+enum status_code tc_set_count_value(
+		const struct tc_module *const module_inst,
+		const uint32_t count)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance*/
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Write to based on the TC counter_size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			tc_module->COUNT8.COUNT.reg  = (uint8_t)count;
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_16BIT:
+			tc_module->COUNT16.COUNT.reg = (uint16_t)count;
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_32BIT:
+			tc_module->COUNT32.COUNT.reg = (uint32_t)count;
+			return STATUS_OK;
+
+		default:
+			return STATUS_ERR_INVALID_ARG;
+	}
+}
+
+/**
+ * \brief Get TC module count value.
+ *
+ * Retrieves the current count value of a TC module. The specified TC module
+ * may be started or stopped.
+ *
+ * \param[in] module_inst  Pointer to the software module instance struct
+ *
+ * \return Count value of the specified TC module.
+ */
+uint32_t tc_get_count_value(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Read synchronization */
+	tc_sync_read_count(module_inst);
+	
+	/* Get a pointer to the module's hardware instance */
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Read from based on the TC counter size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			return (uint32_t)tc_module->COUNT8.COUNT.reg;
+
+		case TC_COUNTER_SIZE_16BIT:
+			return (uint32_t)tc_module->COUNT16.COUNT.reg;
+
+		case TC_COUNTER_SIZE_32BIT:
+			return tc_module->COUNT32.COUNT.reg;
+	}
+
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \brief Gets the TC module capture value.
+ *
+ * Retrieves the capture value in the indicated TC module capture channel.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ * \param[in]  channel_index  Index of the Compare Capture channel to read
+ *
+ * \return Capture value stored in the specified timer channel.
+ */
+uint32_t tc_get_capture_value(
+		const struct tc_module *const module_inst,
+		const enum tc_compare_capture_channel channel_index)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module's hardware instance */
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Read out based on the TC counter size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				return tc_module->COUNT8.CC[channel_index].reg;
+			}
+
+		case TC_COUNTER_SIZE_16BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				return tc_module->COUNT16.CC[channel_index].reg;
+			}
+
+		case TC_COUNTER_SIZE_32BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				return tc_module->COUNT32.CC[channel_index].reg;
+			}
+	}
+
+	Assert(false);
+	return 0;
+}
+
+/**
+ * \brief Sets a TC module compare value.
+ *
+ * Writes a compare value to the given TC module compare/capture channel.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ * \param[in]  channel_index  Index of the compare channel to write to
+ * \param[in]  compare        New compare value to set
+ *
+ * \return Status of the compare update procedure.
+ *
+ * \retval  STATUS_OK               The compare value was updated successfully
+ * \retval  STATUS_ERR_INVALID_ARG  An invalid channel index was supplied
+ */
+enum status_code tc_set_compare_value(
+		const struct tc_module *const module_inst,
+		const enum tc_compare_capture_channel channel_index,
+		const uint32_t compare)
+{
+	/* Sanity check arguments */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(compare);
+
+	/* Get a pointer to the module's hardware instance */
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	/* Read out based on the TC counter size */
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				if (module_inst->double_buffering_enabled){
+					tc_module->COUNT8.CCBUF[channel_index].reg =
+							(uint8_t)compare;
+				} else {
+					tc_module->COUNT8.CC[channel_index].reg  =
+							(uint8_t)compare;
+				}
+				return STATUS_OK;
+			}
+		case TC_COUNTER_SIZE_16BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				if (module_inst->double_buffering_enabled){
+					tc_module->COUNT16.CCBUF[channel_index].reg =
+							(uint16_t)compare;
+				} else {
+					tc_module->COUNT16.CC[channel_index].reg =
+							(uint16_t)compare;
+				}
+				return STATUS_OK;
+			}
+
+		case TC_COUNTER_SIZE_32BIT:
+			if (channel_index <
+					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
+				if (module_inst->double_buffering_enabled){
+					tc_module->COUNT32.CCBUF[channel_index].reg =
+							(uint32_t)compare;
+				} else {
+					tc_module->COUNT32.CC[channel_index].reg =
+						(uint32_t)compare;
+				}
+				return STATUS_OK;
+			}
+	}
+
+	return STATUS_ERR_INVALID_ARG;
+}
+
+/**
+ * \brief Resets the TC module.
+ *
+ * Resets the TC module, restoring all hardware module registers to their
+ * default values and disabling the module. The TC module will not be
+ * accessible while the reset is being performed.
+ *
+ * \note When resetting a 32-bit counter only the master TC module's instance
+ *       structure should be passed to the function.
+ *
+ * \param[in]  module_inst    Pointer to the software module instance struct
+ *
+ * \return Status of the procedure.
+ * \retval STATUS_OK                   The module was reset successfully
+ * \retval STATUS_ERR_UNSUPPORTED_DEV  A 32-bit slave TC module was passed to
+ *                                     the function. Only use reset on master
+ *                                     TC
+ */
+enum status_code tc_reset(
+		const struct tc_module *const module_inst)
+{
+	/* Sanity check arguments  */
+	Assert(module_inst);
+	Assert(module_inst->hw);
+
+	/* Get a pointer to the module hardware instance */
+	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+	if (tc_module->STATUS.reg & TC_STATUS_SLAVE) {
+		return STATUS_ERR_UNSUPPORTED_DEV;
+	}
+
+	/* Disable this module if it is running */
+	if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) {
+		tc_disable(module_inst);
+		while (tc_is_syncing(module_inst)) {
+			/* wait while module is disabling */
+		}
+	}
+
+	/* Reset this TC module */
+	tc_module->CTRLA.reg  |= TC_CTRLA_SWRST;
+
+	return STATUS_OK;
+}
+
+/**
+ * \brief Set the timer TOP/period value.
+ *
+ * For 8-bit counter size this function writes the top value to the period
+ * register.
+ *
+ * For 16- and 32-bit counter size this function writes the top value to
+ * Capture Compare register 0. The value in this register can not be used for
+ * any other purpose.
+ *
+ * \note This function is designed to be used in PWM or frequency
+ *       match modes only, when the counter is set to 16- or 32-bit counter
+ *       size. In 8-bit counter size it will always be possible to change the
+ *       top value even in normal mode.
+ *
+ * \param[in]  module_inst   Pointer to the software module instance struct
+ * \param[in]  top_value     New timer TOP value to set
+ *
+ * \return Status of the TOP set procedure.
+ *
+ * \retval STATUS_OK              The timer TOP value was updated successfully
+ * \retval STATUS_ERR_INVALID_ARG The configured TC module counter size in the
+ *                                module instance is invalid
+ */
+enum status_code tc_set_top_value (
+		const struct tc_module *const module_inst,
+		const uint32_t top_value)
+{
+	Assert(module_inst);
+	Assert(module_inst->hw);
+	Assert(top_value);
+
+	Tc *const tc_module = module_inst->hw;
+
+	while (tc_is_syncing(module_inst)) {
+		/* Wait for sync */
+	}
+
+	switch (module_inst->counter_size) {
+		case TC_COUNTER_SIZE_8BIT:
+			if (module_inst->double_buffering_enabled){
+				tc_module->COUNT8.PERBUF.reg = (uint8_t)top_value;
+			} else {
+				tc_module->COUNT8.PER.reg = (uint8_t)top_value;
+			}
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_16BIT:
+			if (module_inst->double_buffering_enabled){
+				tc_module->COUNT16.CCBUF[0].reg = (uint16_t)top_value;
+			} else {
+				tc_module->COUNT16.CC[0].reg = (uint16_t)top_value;
+			}
+			return STATUS_OK;
+
+		case TC_COUNTER_SIZE_32BIT:
+			if (module_inst->double_buffering_enabled){
+				tc_module->COUNT32.CCBUF[0].reg = (uint32_t)top_value;
+			} else {
+				tc_module->COUNT32.CC[0].reg = (uint32_t)top_value;
+			}
+			return STATUS_OK;
+
+		default:
+			Assert(false);
+			return STATUS_ERR_INVALID_ARG;
+	}
+}

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/ac.h

@@ -0,0 +1,586 @@
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_AC_COMPONENT_
+#define _SAMR34_AC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAMR34_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2245
+#define REV_AC                      0x101
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET             0x00         /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE         _U_(0x00)    /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos          0            /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST              (_U_(0x1) << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos         1            /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE             (_U_(0x1) << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_MASK               _U_(0x03)    /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  START0:1;         /*!< bit:      0  Comparator 0 Start Comparison      */
+    uint8_t  START1:1;         /*!< bit:      1  Comparator 1 Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  START:2;          /*!< bit:  0.. 1  Comparator x Start Comparison      */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET             0x01         /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE         _U_(0x00)    /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos         0            /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0             (_U_(1) << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos         1            /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1             (_U_(1) << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos          0            /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk          (_U_(0x3) << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value)       (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
+#define AC_CTRLB_MASK               _U_(0x03)    /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t COMPEO0:1;        /*!< bit:      0  Comparator 0 Event Output Enable   */
+    uint16_t COMPEO1:1;        /*!< bit:      1  Comparator 1 Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO0:1;         /*!< bit:      4  Window 0 Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI0:1;        /*!< bit:      8  Comparator 0 Event Input Enable    */
+    uint16_t COMPEI1:1;        /*!< bit:      9  Comparator 1 Event Input Enable    */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t INVEI0:1;         /*!< bit:     12  Comparator 0 Input Event Invert Enable */
+    uint16_t INVEI1:1;         /*!< bit:     13  Comparator 1 Input Event Invert Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint16_t COMPEO:2;         /*!< bit:  0.. 1  Comparator x Event Output Enable   */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t WINEO:1;          /*!< bit:      4  Window x Event Output Enable       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t COMPEI:2;         /*!< bit:  8.. 9  Comparator x Event Input Enable    */
+    uint16_t :2;               /*!< bit: 10..11  Reserved                           */
+    uint16_t INVEI:2;          /*!< bit: 12..13  Comparator x Input Event Invert Enable */
+    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET            0x02         /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE        _U_(0x0000)  /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos       0            /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0           (_U_(1) << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos       1            /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1           (_U_(1) << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos        0            /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk        (_U_(0x3) << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value)     (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
+#define AC_EVCTRL_WINEO0_Pos        4            /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0            (_U_(1) << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos         4            /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk         (_U_(0x1) << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value)      (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
+#define AC_EVCTRL_COMPEI0_Pos       8            /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */
+#define AC_EVCTRL_COMPEI0           (_U_(1) << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos       9            /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */
+#define AC_EVCTRL_COMPEI1           (_U_(1) << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos        8            /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */
+#define AC_EVCTRL_COMPEI_Msk        (_U_(0x3) << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value)     (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
+#define AC_EVCTRL_INVEI0_Pos        12           /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */
+#define AC_EVCTRL_INVEI0            (_U_(1) << AC_EVCTRL_INVEI0_Pos)
+#define AC_EVCTRL_INVEI1_Pos        13           /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */
+#define AC_EVCTRL_INVEI1            (_U_(1) << AC_EVCTRL_INVEI1_Pos)
+#define AC_EVCTRL_INVEI_Pos         12           /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */
+#define AC_EVCTRL_INVEI_Msk         (_U_(0x3) << AC_EVCTRL_INVEI_Pos)
+#define AC_EVCTRL_INVEI(value)      (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
+#define AC_EVCTRL_MASK              _U_(0x3313)  /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET          0x04         /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE      _U_(0x00)    /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos       0            /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0           (_U_(1) << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos       1            /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1           (_U_(1) << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos        0            /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk        (_U_(0x3) << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value)     (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
+#define AC_INTENCLR_WIN0_Pos        4            /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0            (_U_(1) << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos         4            /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk         (_U_(0x1) << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value)      (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
+#define AC_INTENCLR_MASK            _U_(0x13)    /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0 Interrupt Enable      */
+    uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1 Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN0:1;           /*!< bit:      4  Window 0 Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x Interrupt Enable      */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WIN:1;            /*!< bit:      4  Window x Interrupt Enable          */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET          0x05         /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE      _U_(0x00)    /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos       0            /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0           (_U_(1) << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos       1            /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1           (_U_(1) << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos        0            /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk        (_U_(0x3) << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value)     (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
+#define AC_INTENSET_WIN0_Pos        4            /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0            (_U_(1) << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos         4            /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk         (_U_(0x1) << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value)      (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
+#define AC_INTENSET_MASK            _U_(0x13)    /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0                       */
+    __I uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1                       */
+    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint8_t  WIN0:1;           /*!< bit:      4  Window 0                           */
+    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  COMP:2;           /*!< bit:  0.. 1  Comparator x                       */
+    __I uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    __I uint8_t  WIN:1;            /*!< bit:      4  Window x                           */
+    __I uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET           0x06         /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE       _U_(0x00)    /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos        0            /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0            (_U_(1) << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos        1            /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1            (_U_(1) << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos         0            /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk         (_U_(0x3) << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value)      (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
+#define AC_INTFLAG_WIN0_Pos         4            /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0             (_U_(1) << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos          4            /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk          (_U_(0x1) << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value)       (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
+#define AC_INTFLAG_MASK             _U_(0x13)    /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x07) (R/   8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STATE0:1;         /*!< bit:      0  Comparator 0 Current State         */
+    uint8_t  STATE1:1;         /*!< bit:      1  Comparator 1 Current State         */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  WSTATE0:2;        /*!< bit:  4.. 5  Window 0 Current State             */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STATE:2;          /*!< bit:  0.. 1  Comparator x Current State         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET           0x07         /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE       _U_(0x00)    /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos       0            /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0           (_U_(1) << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos       1            /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1           (_U_(1) << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos        0            /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk        (_U_(0x3) << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value)     (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
+#define AC_STATUSA_WSTATE0_Pos      4            /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk      (_U_(0x3) << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value)   (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
+#define   AC_STATUSA_WSTATE0_ABOVE_Val    _U_(0x0)   /**< \brief (AC_STATUSA) Signal is above window */
+#define   AC_STATUSA_WSTATE0_INSIDE_Val   _U_(0x1)   /**< \brief (AC_STATUSA) Signal is inside window */
+#define   AC_STATUSA_WSTATE0_BELOW_Val    _U_(0x2)   /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE    (AC_STATUSA_WSTATE0_ABOVE_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE   (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW    (AC_STATUSA_WSTATE0_BELOW_Val  << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK             _U_(0x33)    /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x08) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY0:1;         /*!< bit:      0  Comparator 0 Ready                 */
+    uint8_t  READY1:1;         /*!< bit:      1  Comparator 1 Ready                 */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  READY:2;          /*!< bit:  0.. 1  Comparator x Ready                 */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET           0x08         /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE       _U_(0x00)    /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos       0            /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0           (_U_(1) << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos       1            /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1           (_U_(1) << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos        0            /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk        (_U_(0x3) << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value)     (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
+#define AC_STATUSB_MASK             _U_(0x03)    /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_DBGCTRL_OFFSET           0x09         /**< \brief (AC_DBGCTRL offset) Debug Control */
+#define AC_DBGCTRL_RESETVALUE       _U_(0x00)    /**< \brief (AC_DBGCTRL reset_value) Debug Control */
+
+#define AC_DBGCTRL_DBGRUN_Pos       0            /**< \brief (AC_DBGCTRL) Debug Run */
+#define AC_DBGCTRL_DBGRUN           (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos)
+#define AC_DBGCTRL_MASK             _U_(0x01)    /**< \brief (AC_DBGCTRL) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W  8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  WEN0:1;           /*!< bit:      0  Window 0 Mode Enable               */
+    uint8_t  WINTSEL0:2;       /*!< bit:  1.. 2  Window 0 Interrupt Selection       */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET           0x0A         /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE       _U_(0x00)    /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos         0            /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0             (_U_(0x1) << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos     1            /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk     (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value)  (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
+#define   AC_WINCTRL_WINTSEL0_ABOVE_Val   _U_(0x0)   /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define   AC_WINCTRL_WINTSEL0_INSIDE_Val  _U_(0x1)   /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define   AC_WINCTRL_WINTSEL0_BELOW_Val   _U_(0x2)   /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define   AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3)   /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE   (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE  (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW   (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK             _U_(0x07)    /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W  8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  VALUE:6;          /*!< bit:  0.. 5  Scaler Value                       */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET            0x0C         /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE        _U_(0x00)    /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos         0            /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk         (_U_(0x3F) << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value)      (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
+#define AC_SCALER_MASK              _U_(0x3F)    /**< \brief (AC_SCALER) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t SINGLE:1;         /*!< bit:      2  Single-Shot Mode                   */
+    uint32_t INTSEL:2;         /*!< bit:  3.. 4  Interrupt Selection                */
+    uint32_t :1;               /*!< bit:      5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t MUXNEG:3;         /*!< bit:  8..10  Negative Input Mux Selection       */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t MUXPOS:3;         /*!< bit: 12..14  Positive Input Mux Selection       */
+    uint32_t SWAP:1;           /*!< bit:     15  Swap Inputs and Invert             */
+    uint32_t SPEED:2;          /*!< bit: 16..17  Speed Selection                    */
+    uint32_t :1;               /*!< bit:     18  Reserved                           */
+    uint32_t HYSTEN:1;         /*!< bit:     19  Hysteresis Enable                  */
+    uint32_t HYST:2;           /*!< bit: 20..21  Hysteresis Level                   */
+    uint32_t :2;               /*!< bit: 22..23  Reserved                           */
+    uint32_t FLEN:3;           /*!< bit: 24..26  Filter Length                      */
+    uint32_t :1;               /*!< bit:     27  Reserved                           */
+    uint32_t OUT:2;            /*!< bit: 28..29  Output                             */
+    uint32_t :2;               /*!< bit: 30..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET          0x10         /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos      1            /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE          (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos      2            /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE          (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_INTSEL_Pos      3            /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk      (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value)   (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
+#define   AC_COMPCTRL_INTSEL_TOGGLE_Val   _U_(0x0)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define   AC_COMPCTRL_INTSEL_RISING_Val   _U_(0x1)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define   AC_COMPCTRL_INTSEL_FALLING_Val  _U_(0x2)   /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define   AC_COMPCTRL_INTSEL_EOC_Val      _U_(0x3)   /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE   (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING   (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING  (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC      (AC_COMPCTRL_INTSEL_EOC_Val    << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_RUNSTDBY_Pos    6            /**< \brief (AC_COMPCTRL) Run in Standby */
+#define AC_COMPCTRL_RUNSTDBY        (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos      8            /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk      (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value)   (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
+#define   AC_COMPCTRL_MUXNEG_PIN0_Val     _U_(0x0)   /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXNEG_PIN1_Val     _U_(0x1)   /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXNEG_PIN2_Val     _U_(0x2)   /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXNEG_PIN3_Val     _U_(0x3)   /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define   AC_COMPCTRL_MUXNEG_GND_Val      _U_(0x4)   /**< \brief (AC_COMPCTRL) Ground */
+#define   AC_COMPCTRL_MUXNEG_VSCALE_Val   _U_(0x5)   /**< \brief (AC_COMPCTRL) VDD scaler */
+#define   AC_COMPCTRL_MUXNEG_BANDGAP_Val  _U_(0x6)   /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define   AC_COMPCTRL_MUXNEG_DAC_Val      _U_(0x7)   /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0     (AC_COMPCTRL_MUXNEG_PIN0_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1     (AC_COMPCTRL_MUXNEG_PIN1_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2     (AC_COMPCTRL_MUXNEG_PIN2_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3     (AC_COMPCTRL_MUXNEG_PIN3_Val   << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND      (AC_COMPCTRL_MUXNEG_GND_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE   (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP  (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC      (AC_COMPCTRL_MUXNEG_DAC_Val    << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos      12           /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk      (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value)   (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
+#define   AC_COMPCTRL_MUXPOS_PIN0_Val     _U_(0x0)   /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define   AC_COMPCTRL_MUXPOS_PIN1_Val     _U_(0x1)   /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define   AC_COMPCTRL_MUXPOS_PIN2_Val     _U_(0x2)   /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define   AC_COMPCTRL_MUXPOS_PIN3_Val     _U_(0x3)   /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define   AC_COMPCTRL_MUXPOS_VSCALE_Val   _U_(0x4)   /**< \brief (AC_COMPCTRL) VDD Scaler */
+#define AC_COMPCTRL_MUXPOS_PIN0     (AC_COMPCTRL_MUXPOS_PIN0_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1     (AC_COMPCTRL_MUXPOS_PIN1_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2     (AC_COMPCTRL_MUXPOS_PIN2_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3     (AC_COMPCTRL_MUXPOS_PIN3_Val   << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_VSCALE   (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos        15           /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP            (_U_(0x1) << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_SPEED_Pos       16           /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk       (_U_(0x3) << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value)    (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
+#define   AC_COMPCTRL_SPEED_LOW_Val       _U_(0x0)   /**< \brief (AC_COMPCTRL) Low speed */
+#define   AC_COMPCTRL_SPEED_MEDLOW_Val    _U_(0x1)   /**< \brief (AC_COMPCTRL) Medium low speed */
+#define   AC_COMPCTRL_SPEED_MEDHIGH_Val   _U_(0x2)   /**< \brief (AC_COMPCTRL) Medium high speed */
+#define   AC_COMPCTRL_SPEED_HIGH_Val      _U_(0x3)   /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_LOW       (AC_COMPCTRL_SPEED_LOW_Val     << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_MEDLOW    (AC_COMPCTRL_SPEED_MEDLOW_Val  << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_MEDHIGH   (AC_COMPCTRL_SPEED_MEDHIGH_Val << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_HIGH      (AC_COMPCTRL_SPEED_HIGH_Val    << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_HYSTEN_Pos      19           /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYSTEN          (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos)
+#define AC_COMPCTRL_HYST_Pos        20           /**< \brief (AC_COMPCTRL) Hysteresis Level */
+#define AC_COMPCTRL_HYST_Msk        (_U_(0x3) << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST(value)     (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))
+#define   AC_COMPCTRL_HYST_HYST50_Val     _U_(0x0)   /**< \brief (AC_COMPCTRL) 50mV */
+#define   AC_COMPCTRL_HYST_HYST70_Val     _U_(0x1)   /**< \brief (AC_COMPCTRL) 70mV */
+#define   AC_COMPCTRL_HYST_HYST90_Val     _U_(0x2)   /**< \brief (AC_COMPCTRL) 90mV */
+#define   AC_COMPCTRL_HYST_HYST110_Val    _U_(0x3)   /**< \brief (AC_COMPCTRL) 110mV */
+#define AC_COMPCTRL_HYST_HYST50     (AC_COMPCTRL_HYST_HYST50_Val   << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST_HYST70     (AC_COMPCTRL_HYST_HYST70_Val   << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST_HYST90     (AC_COMPCTRL_HYST_HYST90_Val   << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_HYST_HYST110    (AC_COMPCTRL_HYST_HYST110_Val  << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos        24           /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk        (_U_(0x7) << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value)     (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
+#define   AC_COMPCTRL_FLEN_OFF_Val        _U_(0x0)   /**< \brief (AC_COMPCTRL) No filtering */
+#define   AC_COMPCTRL_FLEN_MAJ3_Val       _U_(0x1)   /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define   AC_COMPCTRL_FLEN_MAJ5_Val       _U_(0x2)   /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF        (AC_COMPCTRL_FLEN_OFF_Val      << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3       (AC_COMPCTRL_FLEN_MAJ3_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5       (AC_COMPCTRL_FLEN_MAJ5_Val     << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_OUT_Pos         28           /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk         (_U_(0x3) << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value)      (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
+#define   AC_COMPCTRL_OUT_OFF_Val         _U_(0x0)   /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_ASYNC_Val       _U_(0x1)   /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define   AC_COMPCTRL_OUT_SYNC_Val        _U_(0x2)   /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF         (AC_COMPCTRL_OUT_OFF_Val       << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC       (AC_COMPCTRL_OUT_ASYNC_Val     << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC        (AC_COMPCTRL_OUT_SYNC_Val      << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_MASK            _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchronization Busy */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable Synchronization Busy        */
+    uint32_t WINCTRL:1;        /*!< bit:      2  WINCTRL Synchronization Busy       */
+    uint32_t COMPCTRL0:1;      /*!< bit:      3  COMPCTRL 0 Synchronization Busy    */
+    uint32_t COMPCTRL1:1;      /*!< bit:      4  COMPCTRL 1 Synchronization Busy    */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :3;               /*!< bit:  0.. 2  Reserved                           */
+    uint32_t COMPCTRL:2;       /*!< bit:  3.. 4  COMPCTRL x Synchronization Busy    */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} AC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SYNCBUSY_OFFSET          0x20         /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */
+#define AC_SYNCBUSY_RESETVALUE      _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define AC_SYNCBUSY_SWRST_Pos       0            /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */
+#define AC_SYNCBUSY_SWRST           (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos)
+#define AC_SYNCBUSY_ENABLE_Pos      1            /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */
+#define AC_SYNCBUSY_ENABLE          (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos)
+#define AC_SYNCBUSY_WINCTRL_Pos     2            /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */
+#define AC_SYNCBUSY_WINCTRL         (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)
+#define AC_SYNCBUSY_COMPCTRL0_Pos   3            /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL0       (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos)
+#define AC_SYNCBUSY_COMPCTRL1_Pos   4            /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL1       (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos)
+#define AC_SYNCBUSY_COMPCTRL_Pos    3            /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */
+#define AC_SYNCBUSY_COMPCTRL_Msk    (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos)
+#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
+#define AC_SYNCBUSY_MASK            _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO AC_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __O  AC_CTRLB_Type             CTRLB;       /**< \brief Offset: 0x01 ( /W  8) Control B */
+  __IO AC_EVCTRL_Type            EVCTRL;      /**< \brief Offset: 0x02 (R/W 16) Event Control */
+  __IO AC_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO AC_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO AC_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+  __I  AC_STATUSA_Type           STATUSA;     /**< \brief Offset: 0x07 (R/   8) Status A */
+  __I  AC_STATUSB_Type           STATUSB;     /**< \brief Offset: 0x08 (R/   8) Status B */
+  __IO AC_DBGCTRL_Type           DBGCTRL;     /**< \brief Offset: 0x09 (R/W  8) Debug Control */
+  __IO AC_WINCTRL_Type           WINCTRL;     /**< \brief Offset: 0x0A (R/W  8) Window Control */
+       RoReg8                    Reserved1[0x1];
+  __IO AC_SCALER_Type            SCALER[2];   /**< \brief Offset: 0x0C (R/W  8) Scaler n */
+       RoReg8                    Reserved2[0x2];
+  __IO AC_COMPCTRL_Type          COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+       RoReg8                    Reserved3[0x8];
+  __I  AC_SYNCBUSY_Type          SYNCBUSY;    /**< \brief Offset: 0x20 (R/  32) Synchronization Busy */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_AC_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/adc.h

@@ -0,0 +1,728 @@
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_ADC_COMPONENT_
+#define _SAMR34_ADC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAMR34_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2247
+#define REV_ADC                     0x111
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
+    uint8_t  ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET            0x00         /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos         0            /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST             (_U_(0x1) << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos        1            /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE            (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos      6            /**< \brief (ADC_CTRLA) Run during Standby */
+#define ADC_CTRLA_RUNSTDBY          (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_ONDEMAND_Pos      7            /**< \brief (ADC_CTRLA) On Demand Control */
+#define ADC_CTRLA_ONDEMAND          (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)
+#define ADC_CTRLA_MASK              _U_(0xC3)    /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PRESCALER:3;      /*!< bit:  0.. 2  Prescaler Configuration            */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET            0x01         /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE        _U_(0x00)    /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_PRESCALER_Pos     0            /**< \brief (ADC_CTRLB) Prescaler Configuration */
+#define ADC_CTRLB_PRESCALER_Msk     (_U_(0x7) << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER(value)  (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
+#define   ADC_CTRLB_PRESCALER_DIV2_Val    _U_(0x0)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */
+#define   ADC_CTRLB_PRESCALER_DIV4_Val    _U_(0x1)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
+#define   ADC_CTRLB_PRESCALER_DIV8_Val    _U_(0x2)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
+#define   ADC_CTRLB_PRESCALER_DIV16_Val   _U_(0x3)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
+#define   ADC_CTRLB_PRESCALER_DIV32_Val   _U_(0x4)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
+#define   ADC_CTRLB_PRESCALER_DIV64_Val   _U_(0x5)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
+#define   ADC_CTRLB_PRESCALER_DIV128_Val  _U_(0x6)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
+#define   ADC_CTRLB_PRESCALER_DIV256_Val  _U_(0x7)   /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
+#define ADC_CTRLB_PRESCALER_DIV2    (ADC_CTRLB_PRESCALER_DIV2_Val  << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV4    (ADC_CTRLB_PRESCALER_DIV4_Val  << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV8    (ADC_CTRLB_PRESCALER_DIV8_Val  << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV16   (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV32   (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV64   (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV128  (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV256  (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_MASK              _U_(0x07)    /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W  8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  REFSEL:4;         /*!< bit:  0.. 3  Reference Selection                */
+    uint8_t  :3;               /*!< bit:  4.. 6  Reserved                           */
+    uint8_t  REFCOMP:1;        /*!< bit:      7  Reference Buffer Offset Compensation Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET          0x02         /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE      _U_(0x00)    /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos      0            /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk      (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value)   (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
+#define   ADC_REFCTRL_REFSEL_INTREF_Val   _U_(0x0)   /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */
+#define   ADC_REFCTRL_REFSEL_INTVCC0_Val  _U_(0x1)   /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */
+#define   ADC_REFCTRL_REFSEL_INTVCC1_Val  _U_(0x2)   /**< \brief (ADC_REFCTRL) 1/2 VDDANA */
+#define   ADC_REFCTRL_REFSEL_AREFA_Val    _U_(0x3)   /**< \brief (ADC_REFCTRL) External Reference */
+#define   ADC_REFCTRL_REFSEL_AREFB_Val    _U_(0x4)   /**< \brief (ADC_REFCTRL) External Reference */
+#define   ADC_REFCTRL_REFSEL_INTVCC2_Val  _U_(0x5)   /**< \brief (ADC_REFCTRL) VCCANA */
+#define ADC_REFCTRL_REFSEL_INTREF   (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0  (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1  (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA    (ADC_REFCTRL_REFSEL_AREFA_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB    (ADC_REFCTRL_REFSEL_AREFB_Val  << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC2  (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos     7            /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP         (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK            _U_(0x8F)    /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLUSHEI:1;        /*!< bit:      0  Flush Event Input Enable           */
+    uint8_t  STARTEI:1;        /*!< bit:      1  Start Conversion Event Input Enable */
+    uint8_t  FLUSHINV:1;       /*!< bit:      2  Flush Event Invert Enable          */
+    uint8_t  STARTINV:1;       /*!< bit:      3  Satrt Event Invert Enable          */
+    uint8_t  RESRDYEO:1;       /*!< bit:      4  Result Ready Event Out             */
+    uint8_t  WINMONEO:1;       /*!< bit:      5  Window Monitor Event Out           */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET           0x03         /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_FLUSHEI_Pos      0            /**< \brief (ADC_EVCTRL) Flush Event Input Enable */
+#define ADC_EVCTRL_FLUSHEI          (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)
+#define ADC_EVCTRL_STARTEI_Pos      1            /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */
+#define ADC_EVCTRL_STARTEI          (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_FLUSHINV_Pos     2            /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */
+#define ADC_EVCTRL_FLUSHINV         (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)
+#define ADC_EVCTRL_STARTINV_Pos     3            /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */
+#define ADC_EVCTRL_STARTINV         (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos     4            /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO         (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos     5            /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO         (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK             _U_(0x3F)    /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Disable     */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Disable          */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Disable   */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET         0x04         /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos     0            /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */
+#define ADC_INTENCLR_RESRDY         (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos    1            /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */
+#define ADC_INTENCLR_OVERRUN        (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos     2            /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */
+#define ADC_INTENCLR_WINMON         (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_MASK           _U_(0x07)    /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Enable      */
+    uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Enable           */
+    uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Enable    */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET         0x05         /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos     0            /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY         (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos    1            /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN        (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos     2            /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON         (_U_(0x1) << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_MASK           _U_(0x07)    /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready Interrupt Flag        */
+    __I uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun Interrupt Flag             */
+    __I uint8_t  WINMON:1;         /*!< bit:      2  Window Monitor Interrupt Flag      */
+    __I uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET          0x06         /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos      0            /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */
+#define ADC_INTFLAG_RESRDY          (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos     1            /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */
+#define ADC_INTFLAG_OVERRUN         (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos      2            /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */
+#define ADC_INTFLAG_WINMON          (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_MASK            _U_(0x07)    /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/   8) Sequence Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SEQSTATE:5;       /*!< bit:  0.. 4  Sequence State                     */
+    uint8_t  :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint8_t  SEQBUSY:1;        /*!< bit:      7  Sequence Busy                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SEQSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SEQSTATUS_OFFSET        0x07         /**< \brief (ADC_SEQSTATUS offset) Sequence Status */
+#define ADC_SEQSTATUS_RESETVALUE    _U_(0x00)    /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */
+
+#define ADC_SEQSTATUS_SEQSTATE_Pos  0            /**< \brief (ADC_SEQSTATUS) Sequence State */
+#define ADC_SEQSTATUS_SEQSTATE_Msk  (_U_(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos)
+#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos))
+#define ADC_SEQSTATUS_SEQBUSY_Pos   7            /**< \brief (ADC_SEQSTATUS) Sequence Busy */
+#define ADC_SEQSTATUS_SEQBUSY       (_U_(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos)
+#define ADC_SEQSTATUS_MASK          _U_(0x9F)    /**< \brief (ADC_SEQSTATUS) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t MUXPOS:5;         /*!< bit:  0.. 4  Positive Mux Input Selection       */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t MUXNEG:5;         /*!< bit:  8..12  Negative Mux Input Selection       */
+    uint16_t :3;               /*!< bit: 13..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET        0x08         /**< \brief (ADC_INPUTCTRL offset) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE    _U_(0x0000)  /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos    0            /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk    (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
+#define   ADC_INPUTCTRL_MUXPOS_AIN0_Val   _U_(0x0)   /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN1_Val   _U_(0x1)   /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN2_Val   _U_(0x2)   /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN3_Val   _U_(0x3)   /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN4_Val   _U_(0x4)   /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN5_Val   _U_(0x5)   /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN6_Val   _U_(0x6)   /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN7_Val   _U_(0x7)   /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN8_Val   _U_(0x8)   /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN9_Val   _U_(0x9)   /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN10_Val  _U_(0xA)   /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN11_Val  _U_(0xB)   /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN12_Val  _U_(0xC)   /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN13_Val  _U_(0xD)   /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN14_Val  _U_(0xE)   /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN15_Val  _U_(0xF)   /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN16_Val  _U_(0x10)   /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN17_Val  _U_(0x11)   /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN18_Val  _U_(0x12)   /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_AIN19_Val  _U_(0x13)   /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define   ADC_INPUTCTRL_MUXPOS_TEMP_Val   _U_(0x18)   /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
+#define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x19)   /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x1A)   /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
+#define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1B)   /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
+#define ADC_INPUTCTRL_MUXPOS_AIN0   (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN1   (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN2   (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN3   (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN4   (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN5   (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN6   (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN7   (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN8   (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN9   (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN10  (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN11  (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN12  (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN13  (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN14  (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN15  (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN16  (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN17  (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN18  (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_AIN19  (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_TEMP   (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos    8            /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk    (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
+#define   ADC_INPUTCTRL_MUXNEG_AIN0_Val   _U_(0x0)   /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN1_Val   _U_(0x1)   /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN2_Val   _U_(0x2)   /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN3_Val   _U_(0x3)   /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN4_Val   _U_(0x4)   /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_AIN5_Val   _U_(0x5)   /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define   ADC_INPUTCTRL_MUXNEG_GND_Val    _U_(0x18)   /**< \brief (ADC_INPUTCTRL) Internal ground */
+#define ADC_INPUTCTRL_MUXNEG_AIN0   (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN1   (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN2   (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN3   (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN4   (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_AIN5   (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND    (ADC_INPUTCTRL_MUXNEG_GND_Val  << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MASK          _U_(0x1F1F)  /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DIFFMODE:1;       /*!< bit:      0  Differential Mode                  */
+    uint16_t LEFTADJ:1;        /*!< bit:      1  Left-Adjusted Result               */
+    uint16_t FREERUN:1;        /*!< bit:      2  Free Running Mode                  */
+    uint16_t CORREN:1;         /*!< bit:      3  Digital Correction Logic Enable    */
+    uint16_t RESSEL:2;         /*!< bit:  4.. 5  Conversion Result Resolution       */
+    uint16_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint16_t WINMODE:3;        /*!< bit:  8..10  Window Monitor Mode                */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLC_OFFSET            0x0A         /**< \brief (ADC_CTRLC offset) Control C */
+#define ADC_CTRLC_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_CTRLC reset_value) Control C */
+
+#define ADC_CTRLC_DIFFMODE_Pos      0            /**< \brief (ADC_CTRLC) Differential Mode */
+#define ADC_CTRLC_DIFFMODE          (_U_(0x1) << ADC_CTRLC_DIFFMODE_Pos)
+#define ADC_CTRLC_LEFTADJ_Pos       1            /**< \brief (ADC_CTRLC) Left-Adjusted Result */
+#define ADC_CTRLC_LEFTADJ           (_U_(0x1) << ADC_CTRLC_LEFTADJ_Pos)
+#define ADC_CTRLC_FREERUN_Pos       2            /**< \brief (ADC_CTRLC) Free Running Mode */
+#define ADC_CTRLC_FREERUN           (_U_(0x1) << ADC_CTRLC_FREERUN_Pos)
+#define ADC_CTRLC_CORREN_Pos        3            /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */
+#define ADC_CTRLC_CORREN            (_U_(0x1) << ADC_CTRLC_CORREN_Pos)
+#define ADC_CTRLC_RESSEL_Pos        4            /**< \brief (ADC_CTRLC) Conversion Result Resolution */
+#define ADC_CTRLC_RESSEL_Msk        (_U_(0x3) << ADC_CTRLC_RESSEL_Pos)
+#define ADC_CTRLC_RESSEL(value)     (ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos))
+#define   ADC_CTRLC_RESSEL_12BIT_Val      _U_(0x0)   /**< \brief (ADC_CTRLC) 12-bit result */
+#define   ADC_CTRLC_RESSEL_16BIT_Val      _U_(0x1)   /**< \brief (ADC_CTRLC) For averaging mode output */
+#define   ADC_CTRLC_RESSEL_10BIT_Val      _U_(0x2)   /**< \brief (ADC_CTRLC) 10-bit result */
+#define   ADC_CTRLC_RESSEL_8BIT_Val       _U_(0x3)   /**< \brief (ADC_CTRLC) 8-bit result */
+#define ADC_CTRLC_RESSEL_12BIT      (ADC_CTRLC_RESSEL_12BIT_Val    << ADC_CTRLC_RESSEL_Pos)
+#define ADC_CTRLC_RESSEL_16BIT      (ADC_CTRLC_RESSEL_16BIT_Val    << ADC_CTRLC_RESSEL_Pos)
+#define ADC_CTRLC_RESSEL_10BIT      (ADC_CTRLC_RESSEL_10BIT_Val    << ADC_CTRLC_RESSEL_Pos)
+#define ADC_CTRLC_RESSEL_8BIT       (ADC_CTRLC_RESSEL_8BIT_Val     << ADC_CTRLC_RESSEL_Pos)
+#define ADC_CTRLC_WINMODE_Pos       8            /**< \brief (ADC_CTRLC) Window Monitor Mode */
+#define ADC_CTRLC_WINMODE_Msk       (_U_(0x7) << ADC_CTRLC_WINMODE_Pos)
+#define ADC_CTRLC_WINMODE(value)    (ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos))
+#define   ADC_CTRLC_WINMODE_DISABLE_Val   _U_(0x0)   /**< \brief (ADC_CTRLC) No window mode (default) */
+#define   ADC_CTRLC_WINMODE_MODE1_Val     _U_(0x1)   /**< \brief (ADC_CTRLC) RESULT > WINLT */
+#define   ADC_CTRLC_WINMODE_MODE2_Val     _U_(0x2)   /**< \brief (ADC_CTRLC) RESULT < WINUT */
+#define   ADC_CTRLC_WINMODE_MODE3_Val     _U_(0x3)   /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */
+#define   ADC_CTRLC_WINMODE_MODE4_Val     _U_(0x4)   /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */
+#define ADC_CTRLC_WINMODE_DISABLE   (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos)
+#define ADC_CTRLC_WINMODE_MODE1     (ADC_CTRLC_WINMODE_MODE1_Val   << ADC_CTRLC_WINMODE_Pos)
+#define ADC_CTRLC_WINMODE_MODE2     (ADC_CTRLC_WINMODE_MODE2_Val   << ADC_CTRLC_WINMODE_Pos)
+#define ADC_CTRLC_WINMODE_MODE3     (ADC_CTRLC_WINMODE_MODE3_Val   << ADC_CTRLC_WINMODE_Pos)
+#define ADC_CTRLC_WINMODE_MODE4     (ADC_CTRLC_WINMODE_MODE4_Val   << ADC_CTRLC_WINMODE_Pos)
+#define ADC_CTRLC_MASK              _U_(0x073F)  /**< \brief (ADC_CTRLC) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W  8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLENUM:4;      /*!< bit:  0.. 3  Number of Samples to be Collected  */
+    uint8_t  ADJRES:3;         /*!< bit:  4.. 6  Adjusting Result / Division Coefficient */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET          0x0C         /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos   0            /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk   (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
+#define   ADC_AVGCTRL_SAMPLENUM_1_Val     _U_(0x0)   /**< \brief (ADC_AVGCTRL) 1 sample */
+#define   ADC_AVGCTRL_SAMPLENUM_2_Val     _U_(0x1)   /**< \brief (ADC_AVGCTRL) 2 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_4_Val     _U_(0x2)   /**< \brief (ADC_AVGCTRL) 4 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_8_Val     _U_(0x3)   /**< \brief (ADC_AVGCTRL) 8 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_16_Val    _U_(0x4)   /**< \brief (ADC_AVGCTRL) 16 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_32_Val    _U_(0x5)   /**< \brief (ADC_AVGCTRL) 32 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_64_Val    _U_(0x6)   /**< \brief (ADC_AVGCTRL) 64 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_128_Val   _U_(0x7)   /**< \brief (ADC_AVGCTRL) 128 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_256_Val   _U_(0x8)   /**< \brief (ADC_AVGCTRL) 256 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_512_Val   _U_(0x9)   /**< \brief (ADC_AVGCTRL) 512 samples */
+#define   ADC_AVGCTRL_SAMPLENUM_1024_Val  _U_(0xA)   /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1     (ADC_AVGCTRL_SAMPLENUM_1_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2     (ADC_AVGCTRL_SAMPLENUM_2_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4     (ADC_AVGCTRL_SAMPLENUM_4_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8     (ADC_AVGCTRL_SAMPLENUM_8_Val   << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16    (ADC_AVGCTRL_SAMPLENUM_16_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32    (ADC_AVGCTRL_SAMPLENUM_32_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64    (ADC_AVGCTRL_SAMPLENUM_64_Val  << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128   (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256   (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512   (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024  (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos      4            /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk      (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value)   (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
+#define ADC_AVGCTRL_MASK            _U_(0x7F)    /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W  8) Sample Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SAMPLEN:6;        /*!< bit:  0.. 5  Sampling Time Length               */
+    uint8_t  :1;               /*!< bit:      6  Reserved                           */
+    uint8_t  OFFCOMP:1;        /*!< bit:      7  Comparator Offset Compensation Enable */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET         0x0D         /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */
+#define ADC_SAMPCTRL_RESETVALUE     _U_(0x00)    /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos    0            /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk    (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
+#define ADC_SAMPCTRL_OFFCOMP_Pos    7            /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */
+#define ADC_SAMPCTRL_OFFCOMP        (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)
+#define ADC_SAMPCTRL_MASK           _U_(0xBF)    /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINLT:16;         /*!< bit:  0..15  Window Lower Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET            0x0E         /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos         0            /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk         (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value)      (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
+#define ADC_WINLT_MASK              _U_(0xFFFF)  /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t WINUT:16;         /*!< bit:  0..15  Window Upper Threshold             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET            0x10         /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos         0            /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk         (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value)      (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
+#define ADC_WINUT_MASK              _U_(0xFFFF)  /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t GAINCORR:12;      /*!< bit:  0..11  Gain Correction Value              */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET         0x12         /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE     _U_(0x0000)  /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos   0            /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk   (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
+#define ADC_GAINCORR_MASK           _U_(0x0FFF)  /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t OFFSETCORR:12;    /*!< bit:  0..11  Offset Correction Value            */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET       0x14         /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE   _U_(0x0000)  /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0            /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
+#define ADC_OFFSETCORR_MASK         _U_(0x0FFF)  /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W  8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  FLUSH:1;          /*!< bit:      0  ADC Flush                          */
+    uint8_t  START:1;          /*!< bit:      1  Start ADC Conversion               */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET           0x18         /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE       _U_(0x00)    /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos        0            /**< \brief (ADC_SWTRIG) ADC Flush */
+#define ADC_SWTRIG_FLUSH            (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos        1            /**< \brief (ADC_SWTRIG) Start ADC Conversion */
+#define ADC_SWTRIG_START            (_U_(0x1) << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK             _U_(0x03)    /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET          0x1C         /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN          (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK            _U_(0x01)    /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/  16) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t SWRST:1;          /*!< bit:      0  SWRST Synchronization Busy         */
+    uint16_t ENABLE:1;         /*!< bit:      1  ENABLE Synchronization Busy        */
+    uint16_t INPUTCTRL:1;      /*!< bit:      2  INPUTCTRL Synchronization Busy     */
+    uint16_t CTRLC:1;          /*!< bit:      3  CTRLC Synchronization Busy         */
+    uint16_t AVGCTRL:1;        /*!< bit:      4  AVGCTRL Synchronization Busy       */
+    uint16_t SAMPCTRL:1;       /*!< bit:      5  SAMPCTRL Synchronization Busy      */
+    uint16_t WINLT:1;          /*!< bit:      6  WINLT Synchronization Busy         */
+    uint16_t WINUT:1;          /*!< bit:      7  WINUT Synchronization Busy         */
+    uint16_t GAINCORR:1;       /*!< bit:      8  GAINCORR Synchronization Busy      */
+    uint16_t OFFSETCORR:1;     /*!< bit:      9  OFFSETCTRL Synchronization Busy    */
+    uint16_t SWTRIG:1;         /*!< bit:     10  SWTRG Synchronization Busy         */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SYNCBUSY_OFFSET         0x20         /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */
+#define ADC_SYNCBUSY_RESETVALUE     _U_(0x0000)  /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define ADC_SYNCBUSY_SWRST_Pos      0            /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */
+#define ADC_SYNCBUSY_SWRST          (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)
+#define ADC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */
+#define ADC_SYNCBUSY_ENABLE         (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)
+#define ADC_SYNCBUSY_INPUTCTRL_Pos  2            /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */
+#define ADC_SYNCBUSY_INPUTCTRL      (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)
+#define ADC_SYNCBUSY_CTRLC_Pos      3            /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */
+#define ADC_SYNCBUSY_CTRLC          (_U_(0x1) << ADC_SYNCBUSY_CTRLC_Pos)
+#define ADC_SYNCBUSY_AVGCTRL_Pos    4            /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */
+#define ADC_SYNCBUSY_AVGCTRL        (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)
+#define ADC_SYNCBUSY_SAMPCTRL_Pos   5            /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */
+#define ADC_SYNCBUSY_SAMPCTRL       (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)
+#define ADC_SYNCBUSY_WINLT_Pos      6            /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */
+#define ADC_SYNCBUSY_WINLT          (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)
+#define ADC_SYNCBUSY_WINUT_Pos      7            /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */
+#define ADC_SYNCBUSY_WINUT          (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)
+#define ADC_SYNCBUSY_GAINCORR_Pos   8            /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */
+#define ADC_SYNCBUSY_GAINCORR       (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)
+#define ADC_SYNCBUSY_OFFSETCORR_Pos 9            /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */
+#define ADC_SYNCBUSY_OFFSETCORR     (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)
+#define ADC_SYNCBUSY_SWTRIG_Pos     10           /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */
+#define ADC_SYNCBUSY_SWTRIG         (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)
+#define ADC_SYNCBUSY_MASK           _U_(0x07FF)  /**< \brief (ADC_SYNCBUSY) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/  16) Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t RESULT:16;        /*!< bit:  0..15  Result Value                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET           0x24         /**< \brief (ADC_RESULT offset) Result */
+#define ADC_RESULT_RESETVALUE       _U_(0x0000)  /**< \brief (ADC_RESULT reset_value) Result */
+
+#define ADC_RESULT_RESULT_Pos       0            /**< \brief (ADC_RESULT) Result Value */
+#define ADC_RESULT_RESULT_Msk       (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value)    (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
+#define ADC_RESULT_MASK             _U_(0xFFFF)  /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SEQEN:32;         /*!< bit:  0..31  Enable Positive Input in the Sequence */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} ADC_SEQCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SEQCTRL_OFFSET          0x28         /**< \brief (ADC_SEQCTRL offset) Sequence Control */
+#define ADC_SEQCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */
+
+#define ADC_SEQCTRL_SEQEN_Pos       0            /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */
+#define ADC_SEQCTRL_SEQEN_Msk       (_U_(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos)
+#define ADC_SEQCTRL_SEQEN(value)    (ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos))
+#define ADC_SEQCTRL_MASK            _U_(0xFFFFFFFF) /**< \brief (ADC_SEQCTRL) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t BIASCOMP:3;       /*!< bit:  0.. 2  Bias Comparator Scaling            */
+    uint16_t :5;               /*!< bit:  3.. 7  Reserved                           */
+    uint16_t BIASREFBUF:3;     /*!< bit:  8..10  Bias  Reference Buffer Scaling     */
+    uint16_t :5;               /*!< bit: 11..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET            0x2C         /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE        _U_(0x0000)  /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_BIASCOMP_Pos      0            /**< \brief (ADC_CALIB) Bias Comparator Scaling */
+#define ADC_CALIB_BIASCOMP_Msk      (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)
+#define ADC_CALIB_BIASCOMP(value)   (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
+#define ADC_CALIB_BIASREFBUF_Pos    8            /**< \brief (ADC_CALIB) Bias  Reference Buffer Scaling */
+#define ADC_CALIB_BIASREFBUF_Msk    (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)
+#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
+#define ADC_CALIB_MASK              _U_(0x0707)  /**< \brief (ADC_CALIB) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO ADC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __IO ADC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x01 (R/W  8) Control B */
+  __IO ADC_REFCTRL_Type          REFCTRL;     /**< \brief Offset: 0x02 (R/W  8) Reference Control */
+  __IO ADC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x03 (R/W  8) Event Control */
+  __IO ADC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO ADC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO ADC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+  __I  ADC_SEQSTATUS_Type        SEQSTATUS;   /**< \brief Offset: 0x07 (R/   8) Sequence Status */
+  __IO ADC_INPUTCTRL_Type        INPUTCTRL;   /**< \brief Offset: 0x08 (R/W 16) Input Control */
+  __IO ADC_CTRLC_Type            CTRLC;       /**< \brief Offset: 0x0A (R/W 16) Control C */
+  __IO ADC_AVGCTRL_Type          AVGCTRL;     /**< \brief Offset: 0x0C (R/W  8) Average Control */
+  __IO ADC_SAMPCTRL_Type         SAMPCTRL;    /**< \brief Offset: 0x0D (R/W  8) Sample Time Control */
+  __IO ADC_WINLT_Type            WINLT;       /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */
+  __IO ADC_WINUT_Type            WINUT;       /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */
+  __IO ADC_GAINCORR_Type         GAINCORR;    /**< \brief Offset: 0x12 (R/W 16) Gain Correction */
+  __IO ADC_OFFSETCORR_Type       OFFSETCORR;  /**< \brief Offset: 0x14 (R/W 16) Offset Correction */
+       RoReg8                    Reserved1[0x2];
+  __IO ADC_SWTRIG_Type           SWTRIG;      /**< \brief Offset: 0x18 (R/W  8) Software Trigger */
+       RoReg8                    Reserved2[0x3];
+  __IO ADC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x1C (R/W  8) Debug Control */
+       RoReg8                    Reserved3[0x3];
+  __I  ADC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x20 (R/  16) Synchronization Busy */
+       RoReg8                    Reserved4[0x2];
+  __I  ADC_RESULT_Type           RESULT;      /**< \brief Offset: 0x24 (R/  16) Result */
+       RoReg8                    Reserved5[0x2];
+  __IO ADC_SEQCTRL_Type          SEQCTRL;     /**< \brief Offset: 0x28 (R/W 32) Sequence Control */
+  __IO ADC_CALIB_Type            CALIB;       /**< \brief Offset: 0x2C (R/W 16) Calibration */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_ADC_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/aes.h

@@ -0,0 +1,325 @@
+/**
+ * \file
+ *
+ * \brief Component description for AES
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_AES_COMPONENT_
+#define _SAMR34_AES_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR AES */
+/* ========================================================================== */
+/** \addtogroup SAMR34_AES Advanced Encryption Standard */
+/*@{*/
+
+#define AES_U2238
+#define REV_AES                     0x200
+
+/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint32_t AESMODE:3;        /*!< bit:  2.. 4  AES Modes of operation             */
+    uint32_t CFBS:3;           /*!< bit:  5.. 7  CFB Types                          */
+    uint32_t KEYSIZE:2;        /*!< bit:  8.. 9  Keysize                            */
+    uint32_t CIPHER:1;         /*!< bit:     10  Cipher mode                        */
+    uint32_t STARTMODE:1;      /*!< bit:     11  Start mode                         */
+    uint32_t LOD:1;            /*!< bit:     12  LOD Enable                         */
+    uint32_t KEYGEN:1;         /*!< bit:     13  Last key generation                */
+    uint32_t XORKEY:1;         /*!< bit:     14  Xor Key operation                  */
+    uint32_t :1;               /*!< bit:     15  Reserved                           */
+    uint32_t CTYPE:4;          /*!< bit: 16..19  Counter measure types              */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CTRLA_OFFSET            0x00         /**< \brief (AES_CTRLA offset) Control A */
+#define AES_CTRLA_RESETVALUE        _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
+
+#define AES_CTRLA_SWRST_Pos         0            /**< \brief (AES_CTRLA) Software Reset */
+#define AES_CTRLA_SWRST             (_U_(0x1) << AES_CTRLA_SWRST_Pos)
+#define AES_CTRLA_ENABLE_Pos        1            /**< \brief (AES_CTRLA) Enable */
+#define AES_CTRLA_ENABLE            (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
+#define AES_CTRLA_AESMODE_Pos       2            /**< \brief (AES_CTRLA) AES Modes of operation */
+#define AES_CTRLA_AESMODE_Msk       (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
+#define AES_CTRLA_AESMODE(value)    (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
+#define AES_CTRLA_CFBS_Pos          5            /**< \brief (AES_CTRLA) CFB Types */
+#define AES_CTRLA_CFBS_Msk          (_U_(0x7) << AES_CTRLA_CFBS_Pos)
+#define AES_CTRLA_CFBS(value)       (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
+#define AES_CTRLA_KEYSIZE_Pos       8            /**< \brief (AES_CTRLA) Keysize */
+#define AES_CTRLA_KEYSIZE_Msk       (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
+#define AES_CTRLA_KEYSIZE(value)    (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
+#define AES_CTRLA_CIPHER_Pos        10           /**< \brief (AES_CTRLA) Cipher mode */
+#define AES_CTRLA_CIPHER            (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
+#define AES_CTRLA_STARTMODE_Pos     11           /**< \brief (AES_CTRLA) Start mode */
+#define AES_CTRLA_STARTMODE         (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
+#define AES_CTRLA_LOD_Pos           12           /**< \brief (AES_CTRLA) LOD Enable */
+#define AES_CTRLA_LOD               (_U_(0x1) << AES_CTRLA_LOD_Pos)
+#define AES_CTRLA_KEYGEN_Pos        13           /**< \brief (AES_CTRLA) Last key generation */
+#define AES_CTRLA_KEYGEN            (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
+#define AES_CTRLA_XORKEY_Pos        14           /**< \brief (AES_CTRLA) Xor Key operation */
+#define AES_CTRLA_XORKEY            (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
+#define AES_CTRLA_CTYPE_Pos         16           /**< \brief (AES_CTRLA) Counter measure types */
+#define AES_CTRLA_CTYPE_Msk         (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
+#define AES_CTRLA_CTYPE(value)      (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
+#define AES_CTRLA_MASK              _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
+
+/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  START:1;          /*!< bit:      0  Manual Start                       */
+    uint8_t  NEWMSG:1;         /*!< bit:      1  New message                        */
+    uint8_t  EOM:1;            /*!< bit:      2  End of message                     */
+    uint8_t  GFMUL:1;          /*!< bit:      3  GF Multiplication                  */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CTRLB_OFFSET            0x04         /**< \brief (AES_CTRLB offset) Control B */
+#define AES_CTRLB_RESETVALUE        _U_(0x00)    /**< \brief (AES_CTRLB reset_value) Control B */
+
+#define AES_CTRLB_START_Pos         0            /**< \brief (AES_CTRLB) Manual Start */
+#define AES_CTRLB_START             (_U_(0x1) << AES_CTRLB_START_Pos)
+#define AES_CTRLB_NEWMSG_Pos        1            /**< \brief (AES_CTRLB) New message */
+#define AES_CTRLB_NEWMSG            (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
+#define AES_CTRLB_EOM_Pos           2            /**< \brief (AES_CTRLB) End of message */
+#define AES_CTRLB_EOM               (_U_(0x1) << AES_CTRLB_EOM_Pos)
+#define AES_CTRLB_GFMUL_Pos         3            /**< \brief (AES_CTRLB) GF Multiplication */
+#define AES_CTRLB_GFMUL             (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
+#define AES_CTRLB_MASK              _U_(0x0F)    /**< \brief (AES_CTRLB) MASK Register */
+
+/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete                */
+    uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTENCLR_OFFSET         0x05         /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
+#define AES_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AES_INTENCLR_ENCCMP_Pos     0            /**< \brief (AES_INTENCLR) Encryption Complete */
+#define AES_INTENCLR_ENCCMP         (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
+#define AES_INTENCLR_GFMCMP_Pos     1            /**< \brief (AES_INTENCLR) GF Multiplication Complete */
+#define AES_INTENCLR_GFMCMP         (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
+#define AES_INTENCLR_MASK           _U_(0x03)    /**< \brief (AES_INTENCLR) MASK Register */
+
+/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete                */
+    uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete         */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTENSET_OFFSET         0x06         /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
+#define AES_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
+
+#define AES_INTENSET_ENCCMP_Pos     0            /**< \brief (AES_INTENSET) Encryption Complete */
+#define AES_INTENSET_ENCCMP         (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
+#define AES_INTENSET_GFMCMP_Pos     1            /**< \brief (AES_INTENSET) GF Multiplication Complete */
+#define AES_INTENSET_GFMCMP         (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
+#define AES_INTENSET_MASK           _U_(0x03)    /**< \brief (AES_INTENSET) MASK Register */
+
+/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W  8) Interrupt Flag Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete                */
+    __I uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete         */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTFLAG_OFFSET          0x07         /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
+#define AES_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
+
+#define AES_INTFLAG_ENCCMP_Pos      0            /**< \brief (AES_INTFLAG) Encryption Complete */
+#define AES_INTFLAG_ENCCMP          (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
+#define AES_INTFLAG_GFMCMP_Pos      1            /**< \brief (AES_INTFLAG) GF Multiplication Complete */
+#define AES_INTFLAG_GFMCMP          (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
+#define AES_INTFLAG_MASK            _U_(0x03)    /**< \brief (AES_INTFLAG) MASK Register */
+
+/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W  8) Data buffer pointer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  INDATAPTR:2;      /*!< bit:  0.. 1  Input Data Pointer                 */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_DATABUFPTR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_DATABUFPTR_OFFSET       0x08         /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
+#define AES_DATABUFPTR_RESETVALUE   _U_(0x00)    /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
+
+#define AES_DATABUFPTR_INDATAPTR_Pos 0            /**< \brief (AES_DATABUFPTR) Input Data Pointer */
+#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
+#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
+#define AES_DATABUFPTR_MASK         _U_(0x03)    /**< \brief (AES_DATABUFPTR) MASK Register */
+
+/* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W  8) Debug control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} AES_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_DBGCTRL_OFFSET          0x09         /**< \brief (AES_DBGCTRL offset) Debug control */
+#define AES_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (AES_DBGCTRL reset_value) Debug control */
+
+#define AES_DBGCTRL_DBGRUN_Pos      0            /**< \brief (AES_DBGCTRL) Debug Run */
+#define AES_DBGCTRL_DBGRUN          (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
+#define AES_DBGCTRL_MASK            _U_(0x01)    /**< \brief (AES_DBGCTRL) MASK Register */
+
+/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_KEYWORD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_KEYWORD_OFFSET          0x0C         /**< \brief (AES_KEYWORD offset) Keyword n */
+#define AES_KEYWORD_RESETVALUE      _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
+#define AES_KEYWORD_MASK            _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
+
+/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_INDATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INDATA_OFFSET           0x38         /**< \brief (AES_INDATA offset) Indata */
+#define AES_INDATA_RESETVALUE       _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
+#define AES_INDATA_MASK             _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
+
+/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_INTVECTV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_INTVECTV_OFFSET         0x3C         /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
+#define AES_INTVECTV_RESETVALUE     _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
+#define AES_INTVECTV_MASK           _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
+
+/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_HASHKEY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_HASHKEY_OFFSET          0x5C         /**< \brief (AES_HASHKEY offset) Hash key n */
+#define AES_HASHKEY_RESETVALUE      _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
+#define AES_HASHKEY_MASK            _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
+
+/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_GHASH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_GHASH_OFFSET            0x6C         /**< \brief (AES_GHASH offset) Galois Hash n */
+#define AES_GHASH_RESETVALUE        _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
+#define AES_GHASH_MASK              _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
+
+/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_CIPLEN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_CIPLEN_OFFSET           0x80         /**< \brief (AES_CIPLEN offset) Cipher Length */
+#define AES_CIPLEN_RESETVALUE       _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
+#define AES_CIPLEN_MASK             _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
+
+/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} AES_RANDSEED_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AES_RANDSEED_OFFSET         0x84         /**< \brief (AES_RANDSEED offset) Random Seed */
+#define AES_RANDSEED_RESETVALUE     _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
+#define AES_RANDSEED_MASK           _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
+
+/** \brief AES hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO AES_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
+  __IO AES_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x04 (R/W  8) Control B */
+  __IO AES_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Clear */
+  __IO AES_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x06 (R/W  8) Interrupt Enable Set */
+  __IO AES_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x07 (R/W  8) Interrupt Flag Status */
+  __IO AES_DATABUFPTR_Type       DATABUFPTR;  /**< \brief Offset: 0x08 (R/W  8) Data buffer pointer */
+  __O  AES_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x09 ( /W  8) Debug control */
+       RoReg8                    Reserved1[0x2];
+  __O  AES_KEYWORD_Type          KEYWORD[8];  /**< \brief Offset: 0x0C ( /W 32) Keyword n */
+       RoReg8                    Reserved2[0xC];
+  __IO AES_INDATA_Type           INDATA;      /**< \brief Offset: 0x38 (R/W 32) Indata */
+  __O  AES_INTVECTV_Type         INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
+       RoReg8                    Reserved3[0x10];
+  __IO AES_HASHKEY_Type          HASHKEY[4];  /**< \brief Offset: 0x5C (R/W 32) Hash key n */
+  __IO AES_GHASH_Type            GHASH[4];    /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
+       RoReg8                    Reserved4[0x4];
+  __IO AES_CIPLEN_Type           CIPLEN;      /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
+  __IO AES_RANDSEED_Type         RANDSEED;    /**< \brief Offset: 0x84 (R/W 32) Random Seed */
+} Aes;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_AES_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/ccl.h

@@ -0,0 +1,188 @@
+/**
+ * \file
+ *
+ * \brief Component description for CCL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_CCL_COMPONENT_
+#define _SAMR34_CCL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR CCL */
+/* ========================================================================== */
+/** \addtogroup SAMR34_CCL Configurable Custom Logic */
+/*@{*/
+
+#define CCL_U2225
+#define REV_CCL                     0x101
+
+/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run during Standby                 */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} CCL_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_CTRL_OFFSET             0x0          /**< \brief (CCL_CTRL offset) Control */
+#define CCL_CTRL_RESETVALUE         _U_(0x00)    /**< \brief (CCL_CTRL reset_value) Control */
+
+#define CCL_CTRL_SWRST_Pos          0            /**< \brief (CCL_CTRL) Software Reset */
+#define CCL_CTRL_SWRST              (_U_(0x1) << CCL_CTRL_SWRST_Pos)
+#define CCL_CTRL_ENABLE_Pos         1            /**< \brief (CCL_CTRL) Enable */
+#define CCL_CTRL_ENABLE             (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
+#define CCL_CTRL_RUNSTDBY_Pos       6            /**< \brief (CCL_CTRL) Run during Standby */
+#define CCL_CTRL_RUNSTDBY           (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
+#define CCL_CTRL_MASK               _U_(0x43)    /**< \brief (CCL_CTRL) MASK Register */
+
+/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W  8) SEQ Control x -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SEQSEL:4;         /*!< bit:  0.. 3  Sequential Selection               */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} CCL_SEQCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_SEQCTRL_OFFSET          0x4          /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
+#define CCL_SEQCTRL_RESETVALUE      _U_(0x00)    /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
+
+#define CCL_SEQCTRL_SEQSEL_Pos      0            /**< \brief (CCL_SEQCTRL) Sequential Selection */
+#define CCL_SEQCTRL_SEQSEL_Msk      (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL(value)   (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
+#define   CCL_SEQCTRL_SEQSEL_DISABLE_Val  _U_(0x0)   /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
+#define   CCL_SEQCTRL_SEQSEL_DFF_Val      _U_(0x1)   /**< \brief (CCL_SEQCTRL) D flip flop */
+#define   CCL_SEQCTRL_SEQSEL_JK_Val       _U_(0x2)   /**< \brief (CCL_SEQCTRL) JK flip flop */
+#define   CCL_SEQCTRL_SEQSEL_LATCH_Val    _U_(0x3)   /**< \brief (CCL_SEQCTRL) D latch */
+#define   CCL_SEQCTRL_SEQSEL_RS_Val       _U_(0x4)   /**< \brief (CCL_SEQCTRL) RS latch */
+#define CCL_SEQCTRL_SEQSEL_DISABLE  (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_DFF      (CCL_SEQCTRL_SEQSEL_DFF_Val    << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_JK       (CCL_SEQCTRL_SEQSEL_JK_Val     << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_LATCH    (CCL_SEQCTRL_SEQSEL_LATCH_Val  << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_SEQSEL_RS       (CCL_SEQCTRL_SEQSEL_RS_Val     << CCL_SEQCTRL_SEQSEL_Pos)
+#define CCL_SEQCTRL_MASK            _U_(0x0F)    /**< \brief (CCL_SEQCTRL) MASK Register */
+
+/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  LUT Enable                         */
+    uint32_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint32_t FILTSEL:2;        /*!< bit:  4.. 5  Filter Selection                   */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t EDGESEL:1;        /*!< bit:      7  Edge Selection                     */
+    uint32_t INSEL0:4;         /*!< bit:  8..11  Input Selection 0                  */
+    uint32_t INSEL1:4;         /*!< bit: 12..15  Input Selection 1                  */
+    uint32_t INSEL2:4;         /*!< bit: 16..19  Input Selection 2                  */
+    uint32_t INVEI:1;          /*!< bit:     20  Input Event Invert                 */
+    uint32_t LUTEI:1;          /*!< bit:     21  Event Input Enable                 */
+    uint32_t LUTEO:1;          /*!< bit:     22  Event Output Enable                */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t TRUTH:8;          /*!< bit: 24..31  Truth Value                        */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} CCL_LUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define CCL_LUTCTRL_OFFSET          0x8          /**< \brief (CCL_LUTCTRL offset) LUT Control x */
+#define CCL_LUTCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
+
+#define CCL_LUTCTRL_ENABLE_Pos      1            /**< \brief (CCL_LUTCTRL) LUT Enable */
+#define CCL_LUTCTRL_ENABLE          (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
+#define CCL_LUTCTRL_FILTSEL_Pos     4            /**< \brief (CCL_LUTCTRL) Filter Selection */
+#define CCL_LUTCTRL_FILTSEL_Msk     (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL(value)  (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
+#define   CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0)   /**< \brief (CCL_LUTCTRL) Filter disabled */
+#define   CCL_LUTCTRL_FILTSEL_SYNCH_Val   _U_(0x1)   /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
+#define   CCL_LUTCTRL_FILTSEL_FILTER_Val  _U_(0x2)   /**< \brief (CCL_LUTCTRL) Filter enabled */
+#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL_SYNCH   (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_FILTSEL_FILTER  (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
+#define CCL_LUTCTRL_EDGESEL_Pos     7            /**< \brief (CCL_LUTCTRL) Edge Selection */
+#define CCL_LUTCTRL_EDGESEL         (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
+#define CCL_LUTCTRL_INSEL0_Pos      8            /**< \brief (CCL_LUTCTRL) Input Selection 0 */
+#define CCL_LUTCTRL_INSEL0_Msk      (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0(value)   (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
+#define   CCL_LUTCTRL_INSEL0_MASK_Val     _U_(0x0)   /**< \brief (CCL_LUTCTRL) Masked input */
+#define   CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1)   /**< \brief (CCL_LUTCTRL) Feedback input source */
+#define   CCL_LUTCTRL_INSEL0_LINK_Val     _U_(0x2)   /**< \brief (CCL_LUTCTRL) Linked LUT input source */
+#define   CCL_LUTCTRL_INSEL0_EVENT_Val    _U_(0x3)   /**< \brief (CCL_LUTCTRL) Event in put source */
+#define   CCL_LUTCTRL_INSEL0_IO_Val       _U_(0x4)   /**< \brief (CCL_LUTCTRL) I/O pin input source */
+#define   CCL_LUTCTRL_INSEL0_AC_Val       _U_(0x5)   /**< \brief (CCL_LUTCTRL) AC input source */
+#define   CCL_LUTCTRL_INSEL0_TC_Val       _U_(0x6)   /**< \brief (CCL_LUTCTRL) TC input source */
+#define   CCL_LUTCTRL_INSEL0_ALTTC_Val    _U_(0x7)   /**< \brief (CCL_LUTCTRL) Alternate TC input source */
+#define   CCL_LUTCTRL_INSEL0_TCC_Val      _U_(0x8)   /**< \brief (CCL_LUTCTRL) TCC input source */
+#define   CCL_LUTCTRL_INSEL0_SERCOM_Val   _U_(0x9)   /**< \brief (CCL_LUTCTRL) SERCOM inout source */
+#define CCL_LUTCTRL_INSEL0_MASK     (CCL_LUTCTRL_INSEL0_MASK_Val   << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_LINK     (CCL_LUTCTRL_INSEL0_LINK_Val   << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_EVENT    (CCL_LUTCTRL_INSEL0_EVENT_Val  << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_IO       (CCL_LUTCTRL_INSEL0_IO_Val     << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_AC       (CCL_LUTCTRL_INSEL0_AC_Val     << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_TC       (CCL_LUTCTRL_INSEL0_TC_Val     << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_ALTTC    (CCL_LUTCTRL_INSEL0_ALTTC_Val  << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_TCC      (CCL_LUTCTRL_INSEL0_TCC_Val    << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL0_SERCOM   (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
+#define CCL_LUTCTRL_INSEL1_Pos      12           /**< \brief (CCL_LUTCTRL) Input Selection 1 */
+#define CCL_LUTCTRL_INSEL1_Msk      (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
+#define CCL_LUTCTRL_INSEL1(value)   (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
+#define CCL_LUTCTRL_INSEL2_Pos      16           /**< \brief (CCL_LUTCTRL) Input Selection 2 */
+#define CCL_LUTCTRL_INSEL2_Msk      (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
+#define CCL_LUTCTRL_INSEL2(value)   (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
+#define CCL_LUTCTRL_INVEI_Pos       20           /**< \brief (CCL_LUTCTRL) Input Event Invert */
+#define CCL_LUTCTRL_INVEI           (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
+#define CCL_LUTCTRL_LUTEI_Pos       21           /**< \brief (CCL_LUTCTRL) Event Input Enable */
+#define CCL_LUTCTRL_LUTEI           (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
+#define CCL_LUTCTRL_LUTEO_Pos       22           /**< \brief (CCL_LUTCTRL) Event Output Enable */
+#define CCL_LUTCTRL_LUTEO           (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
+#define CCL_LUTCTRL_TRUTH_Pos       24           /**< \brief (CCL_LUTCTRL) Truth Value */
+#define CCL_LUTCTRL_TRUTH_Msk       (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
+#define CCL_LUTCTRL_TRUTH(value)    (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
+#define CCL_LUTCTRL_MASK            _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
+
+/** \brief CCL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO CCL_CTRL_Type             CTRL;        /**< \brief Offset: 0x0 (R/W  8) Control */
+       RoReg8                    Reserved1[0x3];
+  __IO CCL_SEQCTRL_Type          SEQCTRL[2];  /**< \brief Offset: 0x4 (R/W  8) SEQ Control x */
+       RoReg8                    Reserved2[0x2];
+  __IO CCL_LUTCTRL_Type          LUTCTRL[4];  /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
+} Ccl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_CCL_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/dac.h

@@ -0,0 +1,455 @@
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_DAC_COMPONENT_
+#define _SAMR34_DAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAMR34_DAC Digital-to-Analog Converter */
+/*@{*/
+
+#define DAC_U2244
+#define REV_DAC                     0x112
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable DAC Controller              */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET            0x00         /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos         0            /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST             (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos        1            /**< \brief (DAC_CTRLA) Enable DAC Controller */
+#define DAC_CTRLA_ENABLE            (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_MASK              _U_(0x03)    /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W  8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DIFF:1;           /*!< bit:      0  Differential mode enable           */
+    uint8_t  REFSEL:2;         /*!< bit:  1.. 2  Reference Selection for DAC0/1     */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET            0x01         /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE        _U_(0x00)    /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_DIFF_Pos          0            /**< \brief (DAC_CTRLB) Differential mode enable */
+#define DAC_CTRLB_DIFF              (_U_(0x1) << DAC_CTRLB_DIFF_Pos)
+#define DAC_CTRLB_REFSEL_Pos        1            /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */
+#define DAC_CTRLB_REFSEL_Msk        (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value)     (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
+#define   DAC_CTRLB_REFSEL_VREFPU_Val     _U_(0x0)   /**< \brief (DAC_CTRLB) External reference unbuffered */
+#define   DAC_CTRLB_REFSEL_VDDANA_Val     _U_(0x1)   /**< \brief (DAC_CTRLB) Analog supply */
+#define   DAC_CTRLB_REFSEL_VREFPB_Val     _U_(0x2)   /**< \brief (DAC_CTRLB) External reference buffered */
+#define   DAC_CTRLB_REFSEL_INTREF_Val     _U_(0x3)   /**< \brief (DAC_CTRLB) Internal bandgap reference */
+#define DAC_CTRLB_REFSEL_VREFPU     (DAC_CTRLB_REFSEL_VREFPU_Val   << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VDDANA     (DAC_CTRLB_REFSEL_VDDANA_Val   << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFPB     (DAC_CTRLB_REFSEL_VREFPB_Val   << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_INTREF     (DAC_CTRLB_REFSEL_INTREF_Val   << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK              _U_(0x07)    /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W  8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  STARTEI0:1;       /*!< bit:      0  Start Conversion Event Input DAC 0 */
+    uint8_t  STARTEI1:1;       /*!< bit:      1  Start Conversion Event Input DAC 1 */
+    uint8_t  EMPTYEO0:1;       /*!< bit:      2  Data Buffer Empty Event Output DAC 0 */
+    uint8_t  EMPTYEO1:1;       /*!< bit:      3  Data Buffer Empty Event Output DAC 1 */
+    uint8_t  INVEI0:1;         /*!< bit:      4  Enable Invertion of DAC 0 input event */
+    uint8_t  INVEI1:1;         /*!< bit:      5  Enable Invertion of DAC 1 input event */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  STARTEI:2;        /*!< bit:  0.. 1  Start Conversion Event Input DAC x */
+    uint8_t  EMPTYEO:2;        /*!< bit:  2.. 3  Data Buffer Empty Event Output DAC x */
+    uint8_t  INVEI:2;          /*!< bit:  4.. 5  Enable Invertion of DAC x input event */
+    uint8_t  :2;               /*!< bit:  6.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET           0x02         /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI0_Pos     0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */
+#define DAC_EVCTRL_STARTEI0         (_U_(1) << DAC_EVCTRL_STARTEI0_Pos)
+#define DAC_EVCTRL_STARTEI1_Pos     1            /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */
+#define DAC_EVCTRL_STARTEI1         (_U_(1) << DAC_EVCTRL_STARTEI1_Pos)
+#define DAC_EVCTRL_STARTEI_Pos      0            /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */
+#define DAC_EVCTRL_STARTEI_Msk      (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_STARTEI(value)   (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))
+#define DAC_EVCTRL_EMPTYEO0_Pos     2            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */
+#define DAC_EVCTRL_EMPTYEO0         (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos)
+#define DAC_EVCTRL_EMPTYEO1_Pos     3            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */
+#define DAC_EVCTRL_EMPTYEO1         (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos      2            /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */
+#define DAC_EVCTRL_EMPTYEO_Msk      (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_EMPTYEO(value)   (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))
+#define DAC_EVCTRL_INVEI0_Pos       4            /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */
+#define DAC_EVCTRL_INVEI0           (_U_(1) << DAC_EVCTRL_INVEI0_Pos)
+#define DAC_EVCTRL_INVEI1_Pos       5            /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */
+#define DAC_EVCTRL_INVEI1           (_U_(1) << DAC_EVCTRL_INVEI1_Pos)
+#define DAC_EVCTRL_INVEI_Pos        4            /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */
+#define DAC_EVCTRL_INVEI_Msk        (_U_(0x3) << DAC_EVCTRL_INVEI_Pos)
+#define DAC_EVCTRL_INVEI(value)     (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))
+#define DAC_EVCTRL_MASK             _U_(0x3F)    /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN0:1;      /*!< bit:      0  Underrun Interrupt Enable for DAC 0 */
+    uint8_t  UNDERRUN1:1;      /*!< bit:      1  Underrun Interrupt Enable for DAC 1 */
+    uint8_t  EMPTY0:1;         /*!< bit:      2  Data Buffer 0 Empty Interrupt Enable */
+    uint8_t  EMPTY1:1;         /*!< bit:      3  Data Buffer 1 Empty Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  UNDERRUN:2;       /*!< bit:  0.. 1  Underrun Interrupt Enable for DAC x */
+    uint8_t  EMPTY:2;          /*!< bit:  2.. 3  Data Buffer x Empty Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET         0x04         /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN0_Pos  0            /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 0 */
+#define DAC_INTENCLR_UNDERRUN0      (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos)
+#define DAC_INTENCLR_UNDERRUN1_Pos  1            /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 1 */
+#define DAC_INTENCLR_UNDERRUN1      (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos)
+#define DAC_INTENCLR_UNDERRUN_Pos   0            /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC x */
+#define DAC_INTENCLR_UNDERRUN_Msk   (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))
+#define DAC_INTENCLR_EMPTY0_Pos     2            /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY0         (_U_(1) << DAC_INTENCLR_EMPTY0_Pos)
+#define DAC_INTENCLR_EMPTY1_Pos     3            /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY1         (_U_(1) << DAC_INTENCLR_EMPTY1_Pos)
+#define DAC_INTENCLR_EMPTY_Pos      2            /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY_Msk      (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_EMPTY(value)   (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))
+#define DAC_INTENCLR_MASK           _U_(0x0F)    /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  UNDERRUN0:1;      /*!< bit:      0  Underrun Interrupt Enable for DAC 0 */
+    uint8_t  UNDERRUN1:1;      /*!< bit:      1  Underrun Interrupt Enable for DAC 1 */
+    uint8_t  EMPTY0:1;         /*!< bit:      2  Data Buffer 0 Empty Interrupt Enable */
+    uint8_t  EMPTY1:1;         /*!< bit:      3  Data Buffer 1 Empty Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  UNDERRUN:2;       /*!< bit:  0.. 1  Underrun Interrupt Enable for DAC x */
+    uint8_t  EMPTY:2;          /*!< bit:  2.. 3  Data Buffer x Empty Interrupt Enable */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET         0x05         /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN0_Pos  0            /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 0 */
+#define DAC_INTENSET_UNDERRUN0      (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos)
+#define DAC_INTENSET_UNDERRUN1_Pos  1            /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 1 */
+#define DAC_INTENSET_UNDERRUN1      (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos)
+#define DAC_INTENSET_UNDERRUN_Pos   0            /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC x */
+#define DAC_INTENSET_UNDERRUN_Msk   (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))
+#define DAC_INTENSET_EMPTY0_Pos     2            /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY0         (_U_(1) << DAC_INTENSET_EMPTY0_Pos)
+#define DAC_INTENSET_EMPTY1_Pos     3            /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY1         (_U_(1) << DAC_INTENSET_EMPTY1_Pos)
+#define DAC_INTENSET_EMPTY_Pos      2            /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY_Msk      (_U_(0x3) << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_EMPTY(value)   (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))
+#define DAC_INTENSET_MASK           _U_(0x0F)    /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  UNDERRUN0:1;      /*!< bit:      0  DAC 0 Underrun                     */
+    __I uint8_t  UNDERRUN1:1;      /*!< bit:      1  DAC 1 Underrun                     */
+    __I uint8_t  EMPTY0:1;         /*!< bit:      2  Data Buffer 0 Empty                */
+    __I uint8_t  EMPTY1:1;         /*!< bit:      3  Data Buffer 1 Empty                */
+    __I uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint8_t  UNDERRUN:2;       /*!< bit:  0.. 1  DAC x Underrun                     */
+    __I uint8_t  EMPTY:2;          /*!< bit:  2.. 3  Data Buffer x Empty                */
+    __I uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET          0x06         /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE      _U_(0x00)    /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN0_Pos   0            /**< \brief (DAC_INTFLAG) DAC 0 Underrun */
+#define DAC_INTFLAG_UNDERRUN0       (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos)
+#define DAC_INTFLAG_UNDERRUN1_Pos   1            /**< \brief (DAC_INTFLAG) DAC 1 Underrun */
+#define DAC_INTFLAG_UNDERRUN1       (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos)
+#define DAC_INTFLAG_UNDERRUN_Pos    0            /**< \brief (DAC_INTFLAG) DAC x Underrun */
+#define DAC_INTFLAG_UNDERRUN_Msk    (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))
+#define DAC_INTFLAG_EMPTY0_Pos      2            /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */
+#define DAC_INTFLAG_EMPTY0          (_U_(1) << DAC_INTFLAG_EMPTY0_Pos)
+#define DAC_INTFLAG_EMPTY1_Pos      3            /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */
+#define DAC_INTFLAG_EMPTY1          (_U_(1) << DAC_INTFLAG_EMPTY1_Pos)
+#define DAC_INTFLAG_EMPTY_Pos       2            /**< \brief (DAC_INTFLAG) Data Buffer x Empty */
+#define DAC_INTFLAG_EMPTY_Msk       (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_EMPTY(value)    (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))
+#define DAC_INTFLAG_MASK            _U_(0x0F)    /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/   8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY0:1;         /*!< bit:      0  DAC 0 Startup Ready                */
+    uint8_t  READY1:1;         /*!< bit:      1  DAC 1 Startup Ready                */
+    uint8_t  EOC0:1;           /*!< bit:      2  DAC 0 End of Conversion            */
+    uint8_t  EOC1:1;           /*!< bit:      3  DAC 1 End of Conversion            */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  READY:2;          /*!< bit:  0.. 1  DAC x Startup Ready                */
+    uint8_t  EOC:2;            /*!< bit:  2.. 3  DAC x End of Conversion            */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET           0x07         /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE       _U_(0x00)    /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_READY0_Pos       0            /**< \brief (DAC_STATUS) DAC 0 Startup Ready */
+#define DAC_STATUS_READY0           (_U_(1) << DAC_STATUS_READY0_Pos)
+#define DAC_STATUS_READY1_Pos       1            /**< \brief (DAC_STATUS) DAC 1 Startup Ready */
+#define DAC_STATUS_READY1           (_U_(1) << DAC_STATUS_READY1_Pos)
+#define DAC_STATUS_READY_Pos        0            /**< \brief (DAC_STATUS) DAC x Startup Ready */
+#define DAC_STATUS_READY_Msk        (_U_(0x3) << DAC_STATUS_READY_Pos)
+#define DAC_STATUS_READY(value)     (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))
+#define DAC_STATUS_EOC0_Pos         2            /**< \brief (DAC_STATUS) DAC 0 End of Conversion */
+#define DAC_STATUS_EOC0             (_U_(1) << DAC_STATUS_EOC0_Pos)
+#define DAC_STATUS_EOC1_Pos         3            /**< \brief (DAC_STATUS) DAC 1 End of Conversion */
+#define DAC_STATUS_EOC1             (_U_(1) << DAC_STATUS_EOC1_Pos)
+#define DAC_STATUS_EOC_Pos          2            /**< \brief (DAC_STATUS) DAC x End of Conversion */
+#define DAC_STATUS_EOC_Msk          (_U_(0x3) << DAC_STATUS_EOC_Pos)
+#define DAC_STATUS_EOC(value)       (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))
+#define DAC_STATUS_MASK             _U_(0x0F)    /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint32_t ENABLE:1;         /*!< bit:      1  DAC Enable Status                  */
+    uint32_t DATA0:1;          /*!< bit:      2  Data DAC 0                         */
+    uint32_t DATA1:1;          /*!< bit:      3  Data DAC 1                         */
+    uint32_t DATABUF0:1;       /*!< bit:      4  Data Buffer DAC 0                  */
+    uint32_t DATABUF1:1;       /*!< bit:      5  Data Buffer DAC 1                  */
+    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t DATA:2;           /*!< bit:  2.. 3  Data DAC x                         */
+    uint32_t DATABUF:2;        /*!< bit:  4.. 5  Data Buffer DAC x                  */
+    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DAC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_SYNCBUSY_OFFSET         0x08         /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */
+#define DAC_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define DAC_SYNCBUSY_SWRST_Pos      0            /**< \brief (DAC_SYNCBUSY) Software Reset */
+#define DAC_SYNCBUSY_SWRST          (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)
+#define DAC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (DAC_SYNCBUSY) DAC Enable Status */
+#define DAC_SYNCBUSY_ENABLE         (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)
+#define DAC_SYNCBUSY_DATA0_Pos      2            /**< \brief (DAC_SYNCBUSY) Data DAC 0 */
+#define DAC_SYNCBUSY_DATA0          (_U_(1) << DAC_SYNCBUSY_DATA0_Pos)
+#define DAC_SYNCBUSY_DATA1_Pos      3            /**< \brief (DAC_SYNCBUSY) Data DAC 1 */
+#define DAC_SYNCBUSY_DATA1          (_U_(1) << DAC_SYNCBUSY_DATA1_Pos)
+#define DAC_SYNCBUSY_DATA_Pos       2            /**< \brief (DAC_SYNCBUSY) Data DAC x */
+#define DAC_SYNCBUSY_DATA_Msk       (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos)
+#define DAC_SYNCBUSY_DATA(value)    (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))
+#define DAC_SYNCBUSY_DATABUF0_Pos   4            /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */
+#define DAC_SYNCBUSY_DATABUF0       (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos)
+#define DAC_SYNCBUSY_DATABUF1_Pos   5            /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */
+#define DAC_SYNCBUSY_DATABUF1       (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos)
+#define DAC_SYNCBUSY_DATABUF_Pos    4            /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */
+#define DAC_SYNCBUSY_DATABUF_Msk    (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos)
+#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))
+#define DAC_SYNCBUSY_MASK           _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */
+
+/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LEFTADJ:1;        /*!< bit:      0  Left Adjusted Data                 */
+    uint16_t ENABLE:1;         /*!< bit:      1  Enable DAC0                        */
+    uint16_t CCTRL:2;          /*!< bit:  2.. 3  Current Control                    */
+    uint16_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t DITHER:1;         /*!< bit:      7  Dithering Mode                     */
+    uint16_t REFRESH:4;        /*!< bit:  8..11  Refresh period                     */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DACCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DACCTRL_OFFSET          0x0C         /**< \brief (DAC_DACCTRL offset) DAC n Control */
+#define DAC_DACCTRL_RESETVALUE      _U_(0x0000)  /**< \brief (DAC_DACCTRL reset_value) DAC n Control */
+
+#define DAC_DACCTRL_LEFTADJ_Pos     0            /**< \brief (DAC_DACCTRL) Left Adjusted Data */
+#define DAC_DACCTRL_LEFTADJ         (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos)
+#define DAC_DACCTRL_ENABLE_Pos      1            /**< \brief (DAC_DACCTRL) Enable DAC0 */
+#define DAC_DACCTRL_ENABLE          (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos)
+#define DAC_DACCTRL_CCTRL_Pos       2            /**< \brief (DAC_DACCTRL) Current Control */
+#define DAC_DACCTRL_CCTRL_Msk       (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL(value)    (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))
+#define   DAC_DACCTRL_CCTRL_CC100K_Val    _U_(0x0)   /**< \brief (DAC_DACCTRL) GCLK_DAC <= 1.2MHz (100kSPS) */
+#define   DAC_DACCTRL_CCTRL_CC1M_Val      _U_(0x1)   /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) */
+#define   DAC_DACCTRL_CCTRL_CC12M_Val     _U_(0x2)   /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC <=12MHz (1MSPS) */
+#define DAC_DACCTRL_CCTRL_CC100K    (DAC_DACCTRL_CCTRL_CC100K_Val  << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL_CC1M      (DAC_DACCTRL_CCTRL_CC1M_Val    << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_CCTRL_CC12M     (DAC_DACCTRL_CCTRL_CC12M_Val   << DAC_DACCTRL_CCTRL_Pos)
+#define DAC_DACCTRL_RUNSTDBY_Pos    6            /**< \brief (DAC_DACCTRL) Run in Standby */
+#define DAC_DACCTRL_RUNSTDBY        (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos)
+#define DAC_DACCTRL_DITHER_Pos      7            /**< \brief (DAC_DACCTRL) Dithering Mode */
+#define DAC_DACCTRL_DITHER          (_U_(0x1) << DAC_DACCTRL_DITHER_Pos)
+#define DAC_DACCTRL_REFRESH_Pos     8            /**< \brief (DAC_DACCTRL) Refresh period */
+#define DAC_DACCTRL_REFRESH_Msk     (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos)
+#define DAC_DACCTRL_REFRESH(value)  (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))
+#define DAC_DACCTRL_MASK            _U_(0x0FCF)  /**< \brief (DAC_DACCTRL) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATA:16;          /*!< bit:  0..15  DAC0 Data                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET             0x10         /**< \brief (DAC_DATA offset) DAC n Data */
+#define DAC_DATA_RESETVALUE         _U_(0x0000)  /**< \brief (DAC_DATA reset_value) DAC n Data */
+
+#define DAC_DATA_DATA_Pos           0            /**< \brief (DAC_DATA) DAC0 Data */
+#define DAC_DATA_DATA_Msk           (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value)        (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
+#define DAC_DATA_MASK               _U_(0xFFFF)  /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t DATABUF:16;       /*!< bit:  0..15  DAC0 Data Buffer                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET          0x14         /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */
+#define DAC_DATABUF_RESETVALUE      _U_(0x0000)  /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos     0            /**< \brief (DAC_DATABUF) DAC0 Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk     (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value)  (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
+#define DAC_DATABUF_MASK            _U_(0xFFFF)  /**< \brief (DAC_DATABUF) MASK Register */
+
+/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W  8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DBGCTRL_OFFSET          0x18         /**< \brief (DAC_DBGCTRL offset) Debug Control */
+#define DAC_DBGCTRL_RESETVALUE      _U_(0x00)    /**< \brief (DAC_DBGCTRL reset_value) Debug Control */
+
+#define DAC_DBGCTRL_DBGRUN_Pos      0            /**< \brief (DAC_DBGCTRL) Debug Run */
+#define DAC_DBGCTRL_DBGRUN          (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)
+#define DAC_DBGCTRL_MASK            _U_(0x01)    /**< \brief (DAC_DBGCTRL) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO DAC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __IO DAC_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x01 (R/W  8) Control B */
+  __IO DAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x02 (R/W  8) Event Control */
+       RoReg8                    Reserved1[0x1];
+  __IO DAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO DAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO DAC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+  __I  DAC_STATUS_Type           STATUS;      /**< \brief Offset: 0x07 (R/   8) Status */
+  __I  DAC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x08 (R/  32) Synchronization Busy */
+  __IO DAC_DACCTRL_Type          DACCTRL[2];  /**< \brief Offset: 0x0C (R/W 16) DAC n Control */
+  __O  DAC_DATA_Type             DATA[2];     /**< \brief Offset: 0x10 ( /W 16) DAC n Data */
+  __O  DAC_DATABUF_Type          DATABUF[2];  /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */
+  __IO DAC_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x18 (R/W  8) Debug Control */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_DAC_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/dsu.h

@@ -0,0 +1,629 @@
+/**
+ * \file
+ *
+ * \brief Component description for DSU
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_DSU_COMPONENT_
+#define _SAMR34_DSU_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR DSU */
+/* ========================================================================== */
+/** \addtogroup SAMR34_DSU Device Service Unit */
+/*@{*/
+
+#define DSU_U2209
+#define REV_DSU                     0x250
+
+/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :1;               /*!< bit:      1  Reserved                           */
+    uint8_t  CRC:1;            /*!< bit:      2  32-bit Cyclic Redundancy Code      */
+    uint8_t  MBIST:1;          /*!< bit:      3  Memory built-in self-test          */
+    uint8_t  CE:1;             /*!< bit:      4  Chip-Erase                         */
+    uint8_t  :1;               /*!< bit:      5  Reserved                           */
+    uint8_t  ARR:1;            /*!< bit:      6  Auxiliary Row Read                 */
+    uint8_t  SMSA:1;           /*!< bit:      7  Start Memory Stream Access         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CTRL_OFFSET             0x0000       /**< \brief (DSU_CTRL offset) Control */
+#define DSU_CTRL_RESETVALUE         _U_(0x00)    /**< \brief (DSU_CTRL reset_value) Control */
+
+#define DSU_CTRL_SWRST_Pos          0            /**< \brief (DSU_CTRL) Software Reset */
+#define DSU_CTRL_SWRST              (_U_(0x1) << DSU_CTRL_SWRST_Pos)
+#define DSU_CTRL_CRC_Pos            2            /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */
+#define DSU_CTRL_CRC                (_U_(0x1) << DSU_CTRL_CRC_Pos)
+#define DSU_CTRL_MBIST_Pos          3            /**< \brief (DSU_CTRL) Memory built-in self-test */
+#define DSU_CTRL_MBIST              (_U_(0x1) << DSU_CTRL_MBIST_Pos)
+#define DSU_CTRL_CE_Pos             4            /**< \brief (DSU_CTRL) Chip-Erase */
+#define DSU_CTRL_CE                 (_U_(0x1) << DSU_CTRL_CE_Pos)
+#define DSU_CTRL_ARR_Pos            6            /**< \brief (DSU_CTRL) Auxiliary Row Read */
+#define DSU_CTRL_ARR                (_U_(0x1) << DSU_CTRL_ARR_Pos)
+#define DSU_CTRL_SMSA_Pos           7            /**< \brief (DSU_CTRL) Start Memory Stream Access */
+#define DSU_CTRL_SMSA               (_U_(0x1) << DSU_CTRL_SMSA_Pos)
+#define DSU_CTRL_MASK               _U_(0xDD)    /**< \brief (DSU_CTRL) MASK Register */
+
+/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W  8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DONE:1;           /*!< bit:      0  Done                               */
+    uint8_t  CRSTEXT:1;        /*!< bit:      1  CPU Reset Phase Extension          */
+    uint8_t  BERR:1;           /*!< bit:      2  Bus Error                          */
+    uint8_t  FAIL:1;           /*!< bit:      3  Failure                            */
+    uint8_t  PERR:1;           /*!< bit:      4  Protection Error                   */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSA_OFFSET          0x0001       /**< \brief (DSU_STATUSA offset) Status A */
+#define DSU_STATUSA_RESETVALUE      _U_(0x00)    /**< \brief (DSU_STATUSA reset_value) Status A */
+
+#define DSU_STATUSA_DONE_Pos        0            /**< \brief (DSU_STATUSA) Done */
+#define DSU_STATUSA_DONE            (_U_(0x1) << DSU_STATUSA_DONE_Pos)
+#define DSU_STATUSA_CRSTEXT_Pos     1            /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
+#define DSU_STATUSA_CRSTEXT         (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos)
+#define DSU_STATUSA_BERR_Pos        2            /**< \brief (DSU_STATUSA) Bus Error */
+#define DSU_STATUSA_BERR            (_U_(0x1) << DSU_STATUSA_BERR_Pos)
+#define DSU_STATUSA_FAIL_Pos        3            /**< \brief (DSU_STATUSA) Failure */
+#define DSU_STATUSA_FAIL            (_U_(0x1) << DSU_STATUSA_FAIL_Pos)
+#define DSU_STATUSA_PERR_Pos        4            /**< \brief (DSU_STATUSA) Protection Error */
+#define DSU_STATUSA_PERR            (_U_(0x1) << DSU_STATUSA_PERR_Pos)
+#define DSU_STATUSA_MASK            _U_(0x1F)    /**< \brief (DSU_STATUSA) MASK Register */
+
+/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/   8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PROT:1;           /*!< bit:      0  Protected                          */
+    uint8_t  DBGPRES:1;        /*!< bit:      1  Debugger Present                   */
+    uint8_t  DCCD0:1;          /*!< bit:      2  Debug Communication Channel 0 Dirty */
+    uint8_t  DCCD1:1;          /*!< bit:      3  Debug Communication Channel 1 Dirty */
+    uint8_t  HPE:1;            /*!< bit:      4  Hot-Plugging Enable                */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  DCCD:2;           /*!< bit:  2.. 3  Debug Communication Channel x Dirty */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} DSU_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSB_OFFSET          0x0002       /**< \brief (DSU_STATUSB offset) Status B */
+#define DSU_STATUSB_RESETVALUE      _U_(0x00)    /**< \brief (DSU_STATUSB reset_value) Status B */
+
+#define DSU_STATUSB_PROT_Pos        0            /**< \brief (DSU_STATUSB) Protected */
+#define DSU_STATUSB_PROT            (_U_(0x1) << DSU_STATUSB_PROT_Pos)
+#define DSU_STATUSB_DBGPRES_Pos     1            /**< \brief (DSU_STATUSB) Debugger Present */
+#define DSU_STATUSB_DBGPRES         (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos)
+#define DSU_STATUSB_DCCD0_Pos       2            /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
+#define DSU_STATUSB_DCCD0           (_U_(1) << DSU_STATUSB_DCCD0_Pos)
+#define DSU_STATUSB_DCCD1_Pos       3            /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
+#define DSU_STATUSB_DCCD1           (_U_(1) << DSU_STATUSB_DCCD1_Pos)
+#define DSU_STATUSB_DCCD_Pos        2            /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
+#define DSU_STATUSB_DCCD_Msk        (_U_(0x3) << DSU_STATUSB_DCCD_Pos)
+#define DSU_STATUSB_DCCD(value)     (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
+#define DSU_STATUSB_HPE_Pos         4            /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
+#define DSU_STATUSB_HPE             (_U_(0x1) << DSU_STATUSB_HPE_Pos)
+#define DSU_STATUSB_MASK            _U_(0x1F)    /**< \brief (DSU_STATUSB) MASK Register */
+
+/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t AMOD:2;           /*!< bit:  0.. 1  Access Mode                        */
+    uint32_t ADDR:30;          /*!< bit:  2..31  Address                            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ADDR_OFFSET             0x0004       /**< \brief (DSU_ADDR offset) Address */
+#define DSU_ADDR_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */
+
+#define DSU_ADDR_AMOD_Pos           0            /**< \brief (DSU_ADDR) Access Mode */
+#define DSU_ADDR_AMOD_Msk           (_U_(0x3) << DSU_ADDR_AMOD_Pos)
+#define DSU_ADDR_AMOD(value)        (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))
+#define DSU_ADDR_ADDR_Pos           2            /**< \brief (DSU_ADDR) Address */
+#define DSU_ADDR_ADDR_Msk           (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos)
+#define DSU_ADDR_ADDR(value)        (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
+#define DSU_ADDR_MASK               _U_(0xFFFFFFFF) /**< \brief (DSU_ADDR) MASK Register */
+
+/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t LENGTH:30;        /*!< bit:  2..31  Length                             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_LENGTH_OFFSET           0x0008       /**< \brief (DSU_LENGTH offset) Length */
+#define DSU_LENGTH_RESETVALUE       _U_(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */
+
+#define DSU_LENGTH_LENGTH_Pos       2            /**< \brief (DSU_LENGTH) Length */
+#define DSU_LENGTH_LENGTH_Msk       (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos)
+#define DSU_LENGTH_LENGTH(value)    (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
+#define DSU_LENGTH_MASK             _U_(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */
+
+/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DATA_OFFSET             0x000C       /**< \brief (DSU_DATA offset) Data */
+#define DSU_DATA_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_DATA reset_value) Data */
+
+#define DSU_DATA_DATA_Pos           0            /**< \brief (DSU_DATA) Data */
+#define DSU_DATA_DATA_Msk           (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos)
+#define DSU_DATA_DATA(value)        (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
+#define DSU_DATA_MASK               _U_(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */
+
+/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DATA:32;          /*!< bit:  0..31  Data                               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCC_OFFSET              0x0010       /**< \brief (DSU_DCC offset) Debug Communication Channel n */
+#define DSU_DCC_RESETVALUE          _U_(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
+
+#define DSU_DCC_DATA_Pos            0            /**< \brief (DSU_DCC) Data */
+#define DSU_DCC_DATA_Msk            (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos)
+#define DSU_DCC_DATA(value)         (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
+#define DSU_DCC_MASK                _U_(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */
+
+/* -------- DSU_DID : (DSU Offset: 0x0018) (R/  32) Device Identification -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DEVSEL:8;         /*!< bit:  0.. 7  Device Select                      */
+    uint32_t REVISION:4;       /*!< bit:  8..11  Revision Number                    */
+    uint32_t DIE:4;            /*!< bit: 12..15  Die Number                         */
+    uint32_t SERIES:6;         /*!< bit: 16..21  Series                             */
+    uint32_t :1;               /*!< bit:     22  Reserved                           */
+    uint32_t FAMILY:5;         /*!< bit: 23..27  Family                             */
+    uint32_t PROCESSOR:4;      /*!< bit: 28..31  Processor                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DID_OFFSET              0x0018       /**< \brief (DSU_DID offset) Device Identification */
+
+#define DSU_DID_DEVSEL_Pos          0            /**< \brief (DSU_DID) Device Select */
+#define DSU_DID_DEVSEL_Msk          (_U_(0xFF) << DSU_DID_DEVSEL_Pos)
+#define DSU_DID_DEVSEL(value)       (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
+#define DSU_DID_REVISION_Pos        8            /**< \brief (DSU_DID) Revision Number */
+#define DSU_DID_REVISION_Msk        (_U_(0xF) << DSU_DID_REVISION_Pos)
+#define DSU_DID_REVISION(value)     (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
+#define DSU_DID_DIE_Pos             12           /**< \brief (DSU_DID) Die Number */
+#define DSU_DID_DIE_Msk             (_U_(0xF) << DSU_DID_DIE_Pos)
+#define DSU_DID_DIE(value)          (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
+#define DSU_DID_SERIES_Pos          16           /**< \brief (DSU_DID) Series */
+#define DSU_DID_SERIES_Msk          (_U_(0x3F) << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES(value)       (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
+#define   DSU_DID_SERIES_0_Val            _U_(0x0)   /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */
+#define   DSU_DID_SERIES_1_Val            _U_(0x1)   /**< \brief (DSU_DID) Cortex-M0+ processor, USB */
+#define DSU_DID_SERIES_0            (DSU_DID_SERIES_0_Val          << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES_1            (DSU_DID_SERIES_1_Val          << DSU_DID_SERIES_Pos)
+#define DSU_DID_FAMILY_Pos          23           /**< \brief (DSU_DID) Family */
+#define DSU_DID_FAMILY_Msk          (_U_(0x1F) << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY(value)       (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
+#define   DSU_DID_FAMILY_0_Val            _U_(0x0)   /**< \brief (DSU_DID) General purpose microcontroller */
+#define   DSU_DID_FAMILY_1_Val            _U_(0x1)   /**< \brief (DSU_DID) PicoPower */
+#define DSU_DID_FAMILY_0            (DSU_DID_FAMILY_0_Val          << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY_1            (DSU_DID_FAMILY_1_Val          << DSU_DID_FAMILY_Pos)
+#define DSU_DID_PROCESSOR_Pos       28           /**< \brief (DSU_DID) Processor */
+#define DSU_DID_PROCESSOR_Msk       (_U_(0xF) << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR(value)    (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
+#define   DSU_DID_PROCESSOR_0_Val         _U_(0x0)   /**< \brief (DSU_DID) Cortex-M0 */
+#define   DSU_DID_PROCESSOR_1_Val         _U_(0x1)   /**< \brief (DSU_DID) Cortex-M0+ */
+#define   DSU_DID_PROCESSOR_2_Val         _U_(0x2)   /**< \brief (DSU_DID) Cortex-M3 */
+#define   DSU_DID_PROCESSOR_3_Val         _U_(0x3)   /**< \brief (DSU_DID) Cortex-M4 */
+#define DSU_DID_PROCESSOR_0         (DSU_DID_PROCESSOR_0_Val       << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_1         (DSU_DID_PROCESSOR_1_Val       << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_2         (DSU_DID_PROCESSOR_2_Val       << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR_3         (DSU_DID_PROCESSOR_3_Val       << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_MASK                _U_(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */
+
+/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DCFG:32;          /*!< bit:  0..31  Device Configuration               */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_DCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCFG_OFFSET             0x00F0       /**< \brief (DSU_DCFG offset) Device Configuration */
+#define DSU_DCFG_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_DCFG reset_value) Device Configuration */
+
+#define DSU_DCFG_DCFG_Pos           0            /**< \brief (DSU_DCFG) Device Configuration */
+#define DSU_DCFG_DCFG_Msk           (_U_(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos)
+#define DSU_DCFG_DCFG(value)        (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos))
+#define DSU_DCFG_MASK               _U_(0xFFFFFFFF) /**< \brief (DSU_DCFG) MASK Register */
+
+/* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/  32) Coresight ROM Table Entry 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EPRES:1;          /*!< bit:      0  Entry Present                      */
+    uint32_t FMT:1;            /*!< bit:      1  Format                             */
+    uint32_t :10;              /*!< bit:  2..11  Reserved                           */
+    uint32_t ADDOFF:20;        /*!< bit: 12..31  Address Offset                     */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ENTRY0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY0_OFFSET           0x1000       /**< \brief (DSU_ENTRY0 offset) Coresight ROM Table Entry 0 */
+#define DSU_ENTRY0_RESETVALUE       _U_(0x9F0FC002) /**< \brief (DSU_ENTRY0 reset_value) Coresight ROM Table Entry 0 */
+
+#define DSU_ENTRY0_EPRES_Pos        0            /**< \brief (DSU_ENTRY0) Entry Present */
+#define DSU_ENTRY0_EPRES            (_U_(0x1) << DSU_ENTRY0_EPRES_Pos)
+#define DSU_ENTRY0_FMT_Pos          1            /**< \brief (DSU_ENTRY0) Format */
+#define DSU_ENTRY0_FMT              (_U_(0x1) << DSU_ENTRY0_FMT_Pos)
+#define DSU_ENTRY0_ADDOFF_Pos       12           /**< \brief (DSU_ENTRY0) Address Offset */
+#define DSU_ENTRY0_ADDOFF_Msk       (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos)
+#define DSU_ENTRY0_ADDOFF(value)    (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos))
+#define DSU_ENTRY0_MASK             _U_(0xFFFFF003) /**< \brief (DSU_ENTRY0) MASK Register */
+
+/* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) (R/  32) Coresight ROM Table Entry 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_ENTRY1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY1_OFFSET           0x1004       /**< \brief (DSU_ENTRY1 offset) Coresight ROM Table Entry 1 */
+#define DSU_ENTRY1_RESETVALUE       _U_(0x00003002) /**< \brief (DSU_ENTRY1 reset_value) Coresight ROM Table Entry 1 */
+#define DSU_ENTRY1_MASK             _U_(0xFFFFFFFF) /**< \brief (DSU_ENTRY1) MASK Register */
+
+/* -------- DSU_END : (DSU Offset: 0x1008) (R/  32) Coresight ROM Table End -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t END:32;           /*!< bit:  0..31  End Marker                         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_END_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_END_OFFSET              0x1008       /**< \brief (DSU_END offset) Coresight ROM Table End */
+#define DSU_END_RESETVALUE          _U_(0x00000000) /**< \brief (DSU_END reset_value) Coresight ROM Table End */
+
+#define DSU_END_END_Pos             0            /**< \brief (DSU_END) End Marker */
+#define DSU_END_END_Msk             (_U_(0xFFFFFFFF) << DSU_END_END_Pos)
+#define DSU_END_END(value)          (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
+#define DSU_END_MASK                _U_(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */
+
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/  32) Coresight ROM Table Memory Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SMEMP:1;          /*!< bit:      0  System Memory Present              */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_MEMTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MEMTYPE_OFFSET          0x1FCC       /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
+#define DSU_MEMTYPE_RESETVALUE      _U_(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
+
+#define DSU_MEMTYPE_SMEMP_Pos       0            /**< \brief (DSU_MEMTYPE) System Memory Present */
+#define DSU_MEMTYPE_SMEMP           (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos)
+#define DSU_MEMTYPE_MASK            _U_(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */
+
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/  32) Peripheral Identification 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPCC:4;          /*!< bit:  0.. 3  JEP-106 Continuation Code          */
+    uint32_t FKBC:4;           /*!< bit:  4.. 7  4KB count                          */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID4_OFFSET             0x1FD0       /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
+#define DSU_PID4_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
+
+#define DSU_PID4_JEPCC_Pos          0            /**< \brief (DSU_PID4) JEP-106 Continuation Code */
+#define DSU_PID4_JEPCC_Msk          (_U_(0xF) << DSU_PID4_JEPCC_Pos)
+#define DSU_PID4_JEPCC(value)       (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
+#define DSU_PID4_FKBC_Pos           4            /**< \brief (DSU_PID4) 4KB count */
+#define DSU_PID4_FKBC_Msk           (_U_(0xF) << DSU_PID4_FKBC_Pos)
+#define DSU_PID4_FKBC(value)        (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
+#define DSU_PID4_MASK               _U_(0x000000FF) /**< \brief (DSU_PID4) MASK Register */
+
+/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/  32) Peripheral Identification 5 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID5_OFFSET             0x1FD4       /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */
+#define DSU_PID5_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID5 reset_value) Peripheral Identification 5 */
+#define DSU_PID5_MASK               _U_(0x00000000) /**< \brief (DSU_PID5) MASK Register */
+
+/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/  32) Peripheral Identification 6 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID6_OFFSET             0x1FD8       /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */
+#define DSU_PID6_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID6 reset_value) Peripheral Identification 6 */
+#define DSU_PID6_MASK               _U_(0x00000000) /**< \brief (DSU_PID6) MASK Register */
+
+/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/  32) Peripheral Identification 7 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID7_OFFSET             0x1FDC       /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */
+#define DSU_PID7_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID7 reset_value) Peripheral Identification 7 */
+#define DSU_PID7_MASK               _U_(0x00000000) /**< \brief (DSU_PID7) MASK Register */
+
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/  32) Peripheral Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBL:8;        /*!< bit:  0.. 7  Part Number Low                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID0_OFFSET             0x1FE0       /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
+#define DSU_PID0_RESETVALUE         _U_(0x000000D0) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
+
+#define DSU_PID0_PARTNBL_Pos        0            /**< \brief (DSU_PID0) Part Number Low */
+#define DSU_PID0_PARTNBL_Msk        (_U_(0xFF) << DSU_PID0_PARTNBL_Pos)
+#define DSU_PID0_PARTNBL(value)     (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
+#define DSU_PID0_MASK               _U_(0x000000FF) /**< \brief (DSU_PID0) MASK Register */
+
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/  32) Peripheral Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PARTNBH:4;        /*!< bit:  0.. 3  Part Number High                   */
+    uint32_t JEPIDCL:4;        /*!< bit:  4.. 7  Low part of the JEP-106 Identity Code */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID1_OFFSET             0x1FE4       /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
+#define DSU_PID1_RESETVALUE         _U_(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
+
+#define DSU_PID1_PARTNBH_Pos        0            /**< \brief (DSU_PID1) Part Number High */
+#define DSU_PID1_PARTNBH_Msk        (_U_(0xF) << DSU_PID1_PARTNBH_Pos)
+#define DSU_PID1_PARTNBH(value)     (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
+#define DSU_PID1_JEPIDCL_Pos        4            /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
+#define DSU_PID1_JEPIDCL_Msk        (_U_(0xF) << DSU_PID1_JEPIDCL_Pos)
+#define DSU_PID1_JEPIDCL(value)     (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
+#define DSU_PID1_MASK               _U_(0x000000FF) /**< \brief (DSU_PID1) MASK Register */
+
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/  32) Peripheral Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t JEPIDCH:3;        /*!< bit:  0.. 2  JEP-106 Identity Code High         */
+    uint32_t JEPU:1;           /*!< bit:      3  JEP-106 Identity Code is used      */
+    uint32_t REVISION:4;       /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID2_OFFSET             0x1FE8       /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
+#define DSU_PID2_RESETVALUE         _U_(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
+
+#define DSU_PID2_JEPIDCH_Pos        0            /**< \brief (DSU_PID2) JEP-106 Identity Code High */
+#define DSU_PID2_JEPIDCH_Msk        (_U_(0x7) << DSU_PID2_JEPIDCH_Pos)
+#define DSU_PID2_JEPIDCH(value)     (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
+#define DSU_PID2_JEPU_Pos           3            /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
+#define DSU_PID2_JEPU               (_U_(0x1) << DSU_PID2_JEPU_Pos)
+#define DSU_PID2_REVISION_Pos       4            /**< \brief (DSU_PID2) Revision Number */
+#define DSU_PID2_REVISION_Msk       (_U_(0xF) << DSU_PID2_REVISION_Pos)
+#define DSU_PID2_REVISION(value)    (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
+#define DSU_PID2_MASK               _U_(0x000000FF) /**< \brief (DSU_PID2) MASK Register */
+
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/  32) Peripheral Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CUSMOD:4;         /*!< bit:  0.. 3  ARM CUSMOD                         */
+    uint32_t REVAND:4;         /*!< bit:  4.. 7  Revision Number                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID3_OFFSET             0x1FEC       /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
+#define DSU_PID3_RESETVALUE         _U_(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
+
+#define DSU_PID3_CUSMOD_Pos         0            /**< \brief (DSU_PID3) ARM CUSMOD */
+#define DSU_PID3_CUSMOD_Msk         (_U_(0xF) << DSU_PID3_CUSMOD_Pos)
+#define DSU_PID3_CUSMOD(value)      (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
+#define DSU_PID3_REVAND_Pos         4            /**< \brief (DSU_PID3) Revision Number */
+#define DSU_PID3_REVAND_Msk         (_U_(0xF) << DSU_PID3_REVAND_Pos)
+#define DSU_PID3_REVAND(value)      (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
+#define DSU_PID3_MASK               _U_(0x000000FF) /**< \brief (DSU_PID3) MASK Register */
+
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/  32) Component Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB0:8;     /*!< bit:  0.. 7  Preamble Byte 0                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID0_OFFSET             0x1FF0       /**< \brief (DSU_CID0 offset) Component Identification 0 */
+#define DSU_CID0_RESETVALUE         _U_(0x0000000D) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
+
+#define DSU_CID0_PREAMBLEB0_Pos     0            /**< \brief (DSU_CID0) Preamble Byte 0 */
+#define DSU_CID0_PREAMBLEB0_Msk     (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos)
+#define DSU_CID0_PREAMBLEB0(value)  (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
+#define DSU_CID0_MASK               _U_(0x000000FF) /**< \brief (DSU_CID0) MASK Register */
+
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/  32) Component Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLE:4;       /*!< bit:  0.. 3  Preamble                           */
+    uint32_t CCLASS:4;         /*!< bit:  4.. 7  Component Class                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID1_OFFSET             0x1FF4       /**< \brief (DSU_CID1 offset) Component Identification 1 */
+#define DSU_CID1_RESETVALUE         _U_(0x00000010) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
+
+#define DSU_CID1_PREAMBLE_Pos       0            /**< \brief (DSU_CID1) Preamble */
+#define DSU_CID1_PREAMBLE_Msk       (_U_(0xF) << DSU_CID1_PREAMBLE_Pos)
+#define DSU_CID1_PREAMBLE(value)    (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
+#define DSU_CID1_CCLASS_Pos         4            /**< \brief (DSU_CID1) Component Class */
+#define DSU_CID1_CCLASS_Msk         (_U_(0xF) << DSU_CID1_CCLASS_Pos)
+#define DSU_CID1_CCLASS(value)      (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
+#define DSU_CID1_MASK               _U_(0x000000FF) /**< \brief (DSU_CID1) MASK Register */
+
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/  32) Component Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB2:8;     /*!< bit:  0.. 7  Preamble Byte 2                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID2_OFFSET             0x1FF8       /**< \brief (DSU_CID2 offset) Component Identification 2 */
+#define DSU_CID2_RESETVALUE         _U_(0x00000005) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
+
+#define DSU_CID2_PREAMBLEB2_Pos     0            /**< \brief (DSU_CID2) Preamble Byte 2 */
+#define DSU_CID2_PREAMBLEB2_Msk     (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos)
+#define DSU_CID2_PREAMBLEB2(value)  (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
+#define DSU_CID2_MASK               _U_(0x000000FF) /**< \brief (DSU_CID2) MASK Register */
+
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/  32) Component Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PREAMBLEB3:8;     /*!< bit:  0.. 7  Preamble Byte 3                    */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} DSU_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID3_OFFSET             0x1FFC       /**< \brief (DSU_CID3 offset) Component Identification 3 */
+#define DSU_CID3_RESETVALUE         _U_(0x000000B1) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
+
+#define DSU_CID3_PREAMBLEB3_Pos     0            /**< \brief (DSU_CID3) Preamble Byte 3 */
+#define DSU_CID3_PREAMBLEB3_Msk     (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos)
+#define DSU_CID3_PREAMBLEB3(value)  (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
+#define DSU_CID3_MASK               _U_(0x000000FF) /**< \brief (DSU_CID3) MASK Register */
+
+/** \brief DSU hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __O  DSU_CTRL_Type             CTRL;        /**< \brief Offset: 0x0000 ( /W  8) Control */
+  __IO DSU_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x0001 (R/W  8) Status A */
+  __I  DSU_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x0002 (R/   8) Status B */
+       RoReg8                    Reserved1[0x1];
+  __IO DSU_ADDR_Type             ADDR;        /**< \brief Offset: 0x0004 (R/W 32) Address */
+  __IO DSU_LENGTH_Type           LENGTH;      /**< \brief Offset: 0x0008 (R/W 32) Length */
+  __IO DSU_DATA_Type             DATA;        /**< \brief Offset: 0x000C (R/W 32) Data */
+  __IO DSU_DCC_Type              DCC[2];      /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+  __I  DSU_DID_Type              DID;         /**< \brief Offset: 0x0018 (R/  32) Device Identification */
+       RoReg8                    Reserved2[0xD4];
+  __IO DSU_DCFG_Type             DCFG[2];     /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */
+       RoReg8                    Reserved3[0xF08];
+  __I  DSU_ENTRY0_Type           ENTRY0;      /**< \brief Offset: 0x1000 (R/  32) Coresight ROM Table Entry 0 */
+  __I  DSU_ENTRY1_Type           ENTRY1;      /**< \brief Offset: 0x1004 (R/  32) Coresight ROM Table Entry 1 */
+  __I  DSU_END_Type              END;         /**< \brief Offset: 0x1008 (R/  32) Coresight ROM Table End */
+       RoReg8                    Reserved4[0xFC0];
+  __I  DSU_MEMTYPE_Type          MEMTYPE;     /**< \brief Offset: 0x1FCC (R/  32) Coresight ROM Table Memory Type */
+  __I  DSU_PID4_Type             PID4;        /**< \brief Offset: 0x1FD0 (R/  32) Peripheral Identification 4 */
+  __I  DSU_PID5_Type             PID5;        /**< \brief Offset: 0x1FD4 (R/  32) Peripheral Identification 5 */
+  __I  DSU_PID6_Type             PID6;        /**< \brief Offset: 0x1FD8 (R/  32) Peripheral Identification 6 */
+  __I  DSU_PID7_Type             PID7;        /**< \brief Offset: 0x1FDC (R/  32) Peripheral Identification 7 */
+  __I  DSU_PID0_Type             PID0;        /**< \brief Offset: 0x1FE0 (R/  32) Peripheral Identification 0 */
+  __I  DSU_PID1_Type             PID1;        /**< \brief Offset: 0x1FE4 (R/  32) Peripheral Identification 1 */
+  __I  DSU_PID2_Type             PID2;        /**< \brief Offset: 0x1FE8 (R/  32) Peripheral Identification 2 */
+  __I  DSU_PID3_Type             PID3;        /**< \brief Offset: 0x1FEC (R/  32) Peripheral Identification 3 */
+  __I  DSU_CID0_Type             CID0;        /**< \brief Offset: 0x1FF0 (R/  32) Component Identification 0 */
+  __I  DSU_CID1_Type             CID1;        /**< \brief Offset: 0x1FF4 (R/  32) Component Identification 1 */
+  __I  DSU_CID2_Type             CID2;        /**< \brief Offset: 0x1FF8 (R/  32) Component Identification 2 */
+  __I  DSU_CID3_Type             CID3;        /**< \brief Offset: 0x1FFC (R/  32) Component Identification 3 */
+} Dsu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_DSU_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/eic.h

@@ -0,0 +1,422 @@
+/**
+ * \file
+ *
+ * \brief Component description for EIC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_EIC_COMPONENT_
+#define _SAMR34_EIC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EIC */
+/* ========================================================================== */
+/** \addtogroup SAMR34_EIC External Interrupt Controller */
+/*@{*/
+
+#define EIC_U2254
+#define REV_EIC                     0x202
+
+/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint8_t  CKSEL:1;          /*!< bit:      4  Clock Selection                    */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CTRLA_OFFSET            0x00         /**< \brief (EIC_CTRLA offset) Control */
+#define EIC_CTRLA_RESETVALUE        _U_(0x00)    /**< \brief (EIC_CTRLA reset_value) Control */
+
+#define EIC_CTRLA_SWRST_Pos         0            /**< \brief (EIC_CTRLA) Software Reset */
+#define EIC_CTRLA_SWRST             (_U_(0x1) << EIC_CTRLA_SWRST_Pos)
+#define EIC_CTRLA_ENABLE_Pos        1            /**< \brief (EIC_CTRLA) Enable */
+#define EIC_CTRLA_ENABLE            (_U_(0x1) << EIC_CTRLA_ENABLE_Pos)
+#define EIC_CTRLA_CKSEL_Pos         4            /**< \brief (EIC_CTRLA) Clock Selection */
+#define EIC_CTRLA_CKSEL             (_U_(0x1) << EIC_CTRLA_CKSEL_Pos)
+#define EIC_CTRLA_MASK              _U_(0x13)    /**< \brief (EIC_CTRLA) MASK Register */
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W  8) NMI Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  NMISENSE:3;       /*!< bit:  0.. 2  NMI Input Sense Configuration      */
+    uint8_t  NMIFILTEN:1;      /*!< bit:      3  NMI Filter Enable                  */
+    uint8_t  NMIASYNCH:1;      /*!< bit:      4  NMI Asynchronous edge Detection Enable */
+    uint8_t  :3;               /*!< bit:  5.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EIC_NMICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMICTRL_OFFSET          0x01         /**< \brief (EIC_NMICTRL offset) NMI Control */
+#define EIC_NMICTRL_RESETVALUE      _U_(0x00)    /**< \brief (EIC_NMICTRL reset_value) NMI Control */
+
+#define EIC_NMICTRL_NMISENSE_Pos    0            /**< \brief (EIC_NMICTRL) NMI Input Sense Configuration */
+#define EIC_NMICTRL_NMISENSE_Msk    (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
+#define   EIC_NMICTRL_NMISENSE_NONE_Val   _U_(0x0)   /**< \brief (EIC_NMICTRL) No detection */
+#define   EIC_NMICTRL_NMISENSE_RISE_Val   _U_(0x1)   /**< \brief (EIC_NMICTRL) Rising edge detection */
+#define   EIC_NMICTRL_NMISENSE_FALL_Val   _U_(0x2)   /**< \brief (EIC_NMICTRL) Falling edge detection */
+#define   EIC_NMICTRL_NMISENSE_BOTH_Val   _U_(0x3)   /**< \brief (EIC_NMICTRL) Both edges detection */
+#define   EIC_NMICTRL_NMISENSE_HIGH_Val   _U_(0x4)   /**< \brief (EIC_NMICTRL) High level detection */
+#define   EIC_NMICTRL_NMISENSE_LOW_Val    _U_(0x5)   /**< \brief (EIC_NMICTRL) Low level detection */
+#define EIC_NMICTRL_NMISENSE_NONE   (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_RISE   (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_FALL   (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_BOTH   (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_HIGH   (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_LOW    (EIC_NMICTRL_NMISENSE_LOW_Val  << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMIFILTEN_Pos   3            /**< \brief (EIC_NMICTRL) NMI Filter Enable */
+#define EIC_NMICTRL_NMIFILTEN       (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_NMIASYNCH_Pos   4            /**< \brief (EIC_NMICTRL) NMI Asynchronous edge Detection Enable */
+#define EIC_NMICTRL_NMIASYNCH       (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)
+#define EIC_NMICTRL_MASK            _U_(0x1F)    /**< \brief (EIC_NMICTRL) MASK Register */
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) NMI Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t NMI:1;            /*!< bit:      0  NMI Interrupt Flag                 */
+    uint16_t :15;              /*!< bit:  1..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} EIC_NMIFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMIFLAG_OFFSET          0x02         /**< \brief (EIC_NMIFLAG offset) NMI Interrupt Flag */
+#define EIC_NMIFLAG_RESETVALUE      _U_(0x0000)  /**< \brief (EIC_NMIFLAG reset_value) NMI Interrupt Flag */
+
+#define EIC_NMIFLAG_NMI_Pos         0            /**< \brief (EIC_NMIFLAG) NMI Interrupt Flag */
+#define EIC_NMIFLAG_NMI             (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK            _U_(0x0001)  /**< \brief (EIC_NMIFLAG) MASK Register */
+
+/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/  32) Syncbusy register -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software reset synchronisation     */
+    uint32_t ENABLE:1;         /*!< bit:      1  Enable synchronisation             */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_SYNCBUSY_OFFSET         0x04         /**< \brief (EIC_SYNCBUSY offset) Syncbusy register */
+#define EIC_SYNCBUSY_RESETVALUE     _U_(0x00000000) /**< \brief (EIC_SYNCBUSY reset_value) Syncbusy register */
+
+#define EIC_SYNCBUSY_SWRST_Pos      0            /**< \brief (EIC_SYNCBUSY) Software reset synchronisation */
+#define EIC_SYNCBUSY_SWRST          (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos)
+#define EIC_SYNCBUSY_ENABLE_Pos     1            /**< \brief (EIC_SYNCBUSY) Enable synchronisation */
+#define EIC_SYNCBUSY_ENABLE         (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)
+#define EIC_SYNCBUSY_MASK           _U_(0x00000003) /**< \brief (EIC_SYNCBUSY) MASK Register */
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINTEO:16;      /*!< bit:  0..15  External Interrupt Event Output Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_EVCTRL_OFFSET           0x08         /**< \brief (EIC_EVCTRL offset) Event Control */
+#define EIC_EVCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */
+
+#define EIC_EVCTRL_EXTINTEO_Pos     0            /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO_Msk     (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO(value)  (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
+#define EIC_EVCTRL_MASK             _U_(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt Disable         */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENCLR_OFFSET         0x0C         /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE     _U_(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EIC_INTENCLR_EXTINT_Pos     0            /**< \brief (EIC_INTENCLR) External Interrupt Disable */
+#define EIC_INTENCLR_EXTINT_Msk     (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT(value)  (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
+#define EIC_INTENCLR_MASK           _U_(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt Disable         */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENSET_OFFSET         0x10         /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE     _U_(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+
+#define EIC_INTENSET_EXTINT_Pos     0            /**< \brief (EIC_INTENSET) External Interrupt Disable */
+#define EIC_INTENSET_EXTINT_Msk     (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT(value)  (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
+#define EIC_INTENSET_MASK           _U_(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t EXTINT:16;        /*!< bit:  0..15  External Interrupt Flag            */
+    __I uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTFLAG_OFFSET          0x14         /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE      _U_(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EIC_INTFLAG_EXTINT_Pos      0            /**< \brief (EIC_INTFLAG) External Interrupt Flag */
+#define EIC_INTFLAG_EXTINT_Msk      (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT(value)   (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
+#define EIC_INTFLAG_MASK            _U_(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */
+
+/* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) EIC Asynchronous edge Detection Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ASYNCH:16;        /*!< bit:  0..15  EIC Asynchronous edge Detection Enable */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_ASYNCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_ASYNCH_OFFSET           0x18         /**< \brief (EIC_ASYNCH offset) EIC Asynchronous edge Detection Enable */
+#define EIC_ASYNCH_RESETVALUE       _U_(0x00000000) /**< \brief (EIC_ASYNCH reset_value) EIC Asynchronous edge Detection Enable */
+
+#define EIC_ASYNCH_ASYNCH_Pos       0            /**< \brief (EIC_ASYNCH) EIC Asynchronous edge Detection Enable */
+#define EIC_ASYNCH_ASYNCH_Msk       (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)
+#define EIC_ASYNCH_ASYNCH(value)    (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))
+#define EIC_ASYNCH_MASK             _U_(0x0000FFFF) /**< \brief (EIC_ASYNCH) MASK Register */
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SENSE0:3;         /*!< bit:  0.. 2  Input Sense Configuration 0        */
+    uint32_t FILTEN0:1;        /*!< bit:      3  Filter Enable 0                    */
+    uint32_t SENSE1:3;         /*!< bit:  4.. 6  Input Sense Configuration 1        */
+    uint32_t FILTEN1:1;        /*!< bit:      7  Filter Enable 1                    */
+    uint32_t SENSE2:3;         /*!< bit:  8..10  Input Sense Configuration 2        */
+    uint32_t FILTEN2:1;        /*!< bit:     11  Filter Enable 2                    */
+    uint32_t SENSE3:3;         /*!< bit: 12..14  Input Sense Configuration 3        */
+    uint32_t FILTEN3:1;        /*!< bit:     15  Filter Enable 3                    */
+    uint32_t SENSE4:3;         /*!< bit: 16..18  Input Sense Configuration 4        */
+    uint32_t FILTEN4:1;        /*!< bit:     19  Filter Enable 4                    */
+    uint32_t SENSE5:3;         /*!< bit: 20..22  Input Sense Configuration 5        */
+    uint32_t FILTEN5:1;        /*!< bit:     23  Filter Enable 5                    */
+    uint32_t SENSE6:3;         /*!< bit: 24..26  Input Sense Configuration 6        */
+    uint32_t FILTEN6:1;        /*!< bit:     27  Filter Enable 6                    */
+    uint32_t SENSE7:3;         /*!< bit: 28..30  Input Sense Configuration 7        */
+    uint32_t FILTEN7:1;        /*!< bit:     31  Filter Enable 7                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EIC_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CONFIG_OFFSET           0x1C         /**< \brief (EIC_CONFIG offset) Configuration n */
+#define EIC_CONFIG_RESETVALUE       _U_(0x00000000) /**< \brief (EIC_CONFIG reset_value) Configuration n */
+
+#define EIC_CONFIG_SENSE0_Pos       0            /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */
+#define EIC_CONFIG_SENSE0_Msk       (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0(value)    (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
+#define   EIC_CONFIG_SENSE0_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE0_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE0_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE0_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE0_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE0_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE0_NONE      (EIC_CONFIG_SENSE0_NONE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_RISE      (EIC_CONFIG_SENSE0_RISE_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_FALL      (EIC_CONFIG_SENSE0_FALL_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_BOTH      (EIC_CONFIG_SENSE0_BOTH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_HIGH      (EIC_CONFIG_SENSE0_HIGH_Val    << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_LOW       (EIC_CONFIG_SENSE0_LOW_Val     << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_FILTEN0_Pos      3            /**< \brief (EIC_CONFIG) Filter Enable 0 */
+#define EIC_CONFIG_FILTEN0          (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_SENSE1_Pos       4            /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */
+#define EIC_CONFIG_SENSE1_Msk       (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1(value)    (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
+#define   EIC_CONFIG_SENSE1_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE1_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE1_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE1_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE1_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE1_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE1_NONE      (EIC_CONFIG_SENSE1_NONE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_RISE      (EIC_CONFIG_SENSE1_RISE_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_FALL      (EIC_CONFIG_SENSE1_FALL_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_BOTH      (EIC_CONFIG_SENSE1_BOTH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_HIGH      (EIC_CONFIG_SENSE1_HIGH_Val    << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_LOW       (EIC_CONFIG_SENSE1_LOW_Val     << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_FILTEN1_Pos      7            /**< \brief (EIC_CONFIG) Filter Enable 1 */
+#define EIC_CONFIG_FILTEN1          (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_SENSE2_Pos       8            /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */
+#define EIC_CONFIG_SENSE2_Msk       (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2(value)    (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
+#define   EIC_CONFIG_SENSE2_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE2_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE2_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE2_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE2_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE2_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE2_NONE      (EIC_CONFIG_SENSE2_NONE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_RISE      (EIC_CONFIG_SENSE2_RISE_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_FALL      (EIC_CONFIG_SENSE2_FALL_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_BOTH      (EIC_CONFIG_SENSE2_BOTH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_HIGH      (EIC_CONFIG_SENSE2_HIGH_Val    << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_LOW       (EIC_CONFIG_SENSE2_LOW_Val     << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_FILTEN2_Pos      11           /**< \brief (EIC_CONFIG) Filter Enable 2 */
+#define EIC_CONFIG_FILTEN2          (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_SENSE3_Pos       12           /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */
+#define EIC_CONFIG_SENSE3_Msk       (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3(value)    (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
+#define   EIC_CONFIG_SENSE3_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE3_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE3_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE3_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE3_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE3_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE3_NONE      (EIC_CONFIG_SENSE3_NONE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_RISE      (EIC_CONFIG_SENSE3_RISE_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_FALL      (EIC_CONFIG_SENSE3_FALL_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_BOTH      (EIC_CONFIG_SENSE3_BOTH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_HIGH      (EIC_CONFIG_SENSE3_HIGH_Val    << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_LOW       (EIC_CONFIG_SENSE3_LOW_Val     << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_FILTEN3_Pos      15           /**< \brief (EIC_CONFIG) Filter Enable 3 */
+#define EIC_CONFIG_FILTEN3          (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_SENSE4_Pos       16           /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */
+#define EIC_CONFIG_SENSE4_Msk       (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4(value)    (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
+#define   EIC_CONFIG_SENSE4_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE4_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE4_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE4_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE4_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE4_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE4_NONE      (EIC_CONFIG_SENSE4_NONE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_RISE      (EIC_CONFIG_SENSE4_RISE_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_FALL      (EIC_CONFIG_SENSE4_FALL_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_BOTH      (EIC_CONFIG_SENSE4_BOTH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_HIGH      (EIC_CONFIG_SENSE4_HIGH_Val    << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_LOW       (EIC_CONFIG_SENSE4_LOW_Val     << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_FILTEN4_Pos      19           /**< \brief (EIC_CONFIG) Filter Enable 4 */
+#define EIC_CONFIG_FILTEN4          (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_SENSE5_Pos       20           /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */
+#define EIC_CONFIG_SENSE5_Msk       (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5(value)    (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
+#define   EIC_CONFIG_SENSE5_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE5_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE5_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE5_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE5_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE5_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE5_NONE      (EIC_CONFIG_SENSE5_NONE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_RISE      (EIC_CONFIG_SENSE5_RISE_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_FALL      (EIC_CONFIG_SENSE5_FALL_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_BOTH      (EIC_CONFIG_SENSE5_BOTH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_HIGH      (EIC_CONFIG_SENSE5_HIGH_Val    << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_LOW       (EIC_CONFIG_SENSE5_LOW_Val     << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_FILTEN5_Pos      23           /**< \brief (EIC_CONFIG) Filter Enable 5 */
+#define EIC_CONFIG_FILTEN5          (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_SENSE6_Pos       24           /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */
+#define EIC_CONFIG_SENSE6_Msk       (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6(value)    (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
+#define   EIC_CONFIG_SENSE6_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE6_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE6_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE6_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE6_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE6_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE6_NONE      (EIC_CONFIG_SENSE6_NONE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_RISE      (EIC_CONFIG_SENSE6_RISE_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_FALL      (EIC_CONFIG_SENSE6_FALL_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_BOTH      (EIC_CONFIG_SENSE6_BOTH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_HIGH      (EIC_CONFIG_SENSE6_HIGH_Val    << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_LOW       (EIC_CONFIG_SENSE6_LOW_Val     << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_FILTEN6_Pos      27           /**< \brief (EIC_CONFIG) Filter Enable 6 */
+#define EIC_CONFIG_FILTEN6          (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_SENSE7_Pos       28           /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */
+#define EIC_CONFIG_SENSE7_Msk       (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7(value)    (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
+#define   EIC_CONFIG_SENSE7_NONE_Val      _U_(0x0)   /**< \brief (EIC_CONFIG) No detection */
+#define   EIC_CONFIG_SENSE7_RISE_Val      _U_(0x1)   /**< \brief (EIC_CONFIG) Rising edge detection */
+#define   EIC_CONFIG_SENSE7_FALL_Val      _U_(0x2)   /**< \brief (EIC_CONFIG) Falling edge detection */
+#define   EIC_CONFIG_SENSE7_BOTH_Val      _U_(0x3)   /**< \brief (EIC_CONFIG) Both edges detection */
+#define   EIC_CONFIG_SENSE7_HIGH_Val      _U_(0x4)   /**< \brief (EIC_CONFIG) High level detection */
+#define   EIC_CONFIG_SENSE7_LOW_Val       _U_(0x5)   /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE7_NONE      (EIC_CONFIG_SENSE7_NONE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_RISE      (EIC_CONFIG_SENSE7_RISE_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_FALL      (EIC_CONFIG_SENSE7_FALL_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_BOTH      (EIC_CONFIG_SENSE7_BOTH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_HIGH      (EIC_CONFIG_SENSE7_HIGH_Val    << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_LOW       (EIC_CONFIG_SENSE7_LOW_Val     << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_FILTEN7_Pos      31           /**< \brief (EIC_CONFIG) Filter Enable 7 */
+#define EIC_CONFIG_FILTEN7          (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK             _U_(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */
+
+/** \brief EIC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO EIC_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control */
+  __IO EIC_NMICTRL_Type          NMICTRL;     /**< \brief Offset: 0x01 (R/W  8) NMI Control */
+  __IO EIC_NMIFLAG_Type          NMIFLAG;     /**< \brief Offset: 0x02 (R/W 16) NMI Interrupt Flag */
+  __I  EIC_SYNCBUSY_Type         SYNCBUSY;    /**< \brief Offset: 0x04 (R/  32) Syncbusy register */
+  __IO EIC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x08 (R/W 32) Event Control */
+  __IO EIC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */
+  __IO EIC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */
+  __IO EIC_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */
+  __IO EIC_ASYNCH_Type           ASYNCH;      /**< \brief Offset: 0x18 (R/W 32) EIC Asynchronous edge Detection Enable */
+  __IO EIC_CONFIG_Type           CONFIG[2];   /**< \brief Offset: 0x1C (R/W 32) Configuration n */
+} Eic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_EIC_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/evsys.h

@@ -0,0 +1,604 @@
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_EVSYS_COMPONENT_
+#define _SAMR34_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAMR34_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2256
+#define REV_EVSYS                   0x101
+
+/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} EVSYS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRLA_OFFSET          0x00         /**< \brief (EVSYS_CTRLA offset) Control */
+#define EVSYS_CTRLA_RESETVALUE      _U_(0x00)    /**< \brief (EVSYS_CTRLA reset_value) Control */
+
+#define EVSYS_CTRLA_SWRST_Pos       0            /**< \brief (EVSYS_CTRLA) Software Reset */
+#define EVSYS_CTRLA_SWRST           (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos)
+#define EVSYS_CTRLA_MASK            _U_(0x01)    /**< \brief (EVSYS_CTRLA) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/  32) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t USRRDY0:1;        /*!< bit:      0  Channel 0 User Ready               */
+    uint32_t USRRDY1:1;        /*!< bit:      1  Channel 1 User Ready               */
+    uint32_t USRRDY2:1;        /*!< bit:      2  Channel 2 User Ready               */
+    uint32_t USRRDY3:1;        /*!< bit:      3  Channel 3 User Ready               */
+    uint32_t USRRDY4:1;        /*!< bit:      4  Channel 4 User Ready               */
+    uint32_t USRRDY5:1;        /*!< bit:      5  Channel 5 User Ready               */
+    uint32_t USRRDY6:1;        /*!< bit:      6  Channel 6 User Ready               */
+    uint32_t USRRDY7:1;        /*!< bit:      7  Channel 7 User Ready               */
+    uint32_t USRRDY8:1;        /*!< bit:      8  Channel 8 User Ready               */
+    uint32_t USRRDY9:1;        /*!< bit:      9  Channel 9 User Ready               */
+    uint32_t USRRDY10:1;       /*!< bit:     10  Channel 10 User Ready              */
+    uint32_t USRRDY11:1;       /*!< bit:     11  Channel 11 User Ready              */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t CHBUSY0:1;        /*!< bit:     16  Channel 0 Busy                     */
+    uint32_t CHBUSY1:1;        /*!< bit:     17  Channel 1 Busy                     */
+    uint32_t CHBUSY2:1;        /*!< bit:     18  Channel 2 Busy                     */
+    uint32_t CHBUSY3:1;        /*!< bit:     19  Channel 3 Busy                     */
+    uint32_t CHBUSY4:1;        /*!< bit:     20  Channel 4 Busy                     */
+    uint32_t CHBUSY5:1;        /*!< bit:     21  Channel 5 Busy                     */
+    uint32_t CHBUSY6:1;        /*!< bit:     22  Channel 6 Busy                     */
+    uint32_t CHBUSY7:1;        /*!< bit:     23  Channel 7 Busy                     */
+    uint32_t CHBUSY8:1;        /*!< bit:     24  Channel 8 Busy                     */
+    uint32_t CHBUSY9:1;        /*!< bit:     25  Channel 9 Busy                     */
+    uint32_t CHBUSY10:1;       /*!< bit:     26  Channel 10 Busy                    */
+    uint32_t CHBUSY11:1;       /*!< bit:     27  Channel 11 Busy                    */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t USRRDY:12;        /*!< bit:  0..11  Channel x User Ready               */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t CHBUSY:12;        /*!< bit: 16..27  Channel x Busy                     */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET       0x0C         /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
+#define EVSYS_CHSTATUS_RESETVALUE   _U_(0x00000000) /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
+
+#define EVSYS_CHSTATUS_USRRDY0_Pos  0            /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
+#define EVSYS_CHSTATUS_USRRDY0      (_U_(1) << EVSYS_CHSTATUS_USRRDY0_Pos)
+#define EVSYS_CHSTATUS_USRRDY1_Pos  1            /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
+#define EVSYS_CHSTATUS_USRRDY1      (_U_(1) << EVSYS_CHSTATUS_USRRDY1_Pos)
+#define EVSYS_CHSTATUS_USRRDY2_Pos  2            /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
+#define EVSYS_CHSTATUS_USRRDY2      (_U_(1) << EVSYS_CHSTATUS_USRRDY2_Pos)
+#define EVSYS_CHSTATUS_USRRDY3_Pos  3            /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
+#define EVSYS_CHSTATUS_USRRDY3      (_U_(1) << EVSYS_CHSTATUS_USRRDY3_Pos)
+#define EVSYS_CHSTATUS_USRRDY4_Pos  4            /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
+#define EVSYS_CHSTATUS_USRRDY4      (_U_(1) << EVSYS_CHSTATUS_USRRDY4_Pos)
+#define EVSYS_CHSTATUS_USRRDY5_Pos  5            /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
+#define EVSYS_CHSTATUS_USRRDY5      (_U_(1) << EVSYS_CHSTATUS_USRRDY5_Pos)
+#define EVSYS_CHSTATUS_USRRDY6_Pos  6            /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
+#define EVSYS_CHSTATUS_USRRDY6      (_U_(1) << EVSYS_CHSTATUS_USRRDY6_Pos)
+#define EVSYS_CHSTATUS_USRRDY7_Pos  7            /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
+#define EVSYS_CHSTATUS_USRRDY7      (_U_(1) << EVSYS_CHSTATUS_USRRDY7_Pos)
+#define EVSYS_CHSTATUS_USRRDY8_Pos  8            /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
+#define EVSYS_CHSTATUS_USRRDY8      (_U_(1) << EVSYS_CHSTATUS_USRRDY8_Pos)
+#define EVSYS_CHSTATUS_USRRDY9_Pos  9            /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
+#define EVSYS_CHSTATUS_USRRDY9      (_U_(1) << EVSYS_CHSTATUS_USRRDY9_Pos)
+#define EVSYS_CHSTATUS_USRRDY10_Pos 10           /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
+#define EVSYS_CHSTATUS_USRRDY10     (_U_(1) << EVSYS_CHSTATUS_USRRDY10_Pos)
+#define EVSYS_CHSTATUS_USRRDY11_Pos 11           /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
+#define EVSYS_CHSTATUS_USRRDY11     (_U_(1) << EVSYS_CHSTATUS_USRRDY11_Pos)
+#define EVSYS_CHSTATUS_USRRDY_Pos   0            /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
+#define EVSYS_CHSTATUS_USRRDY_Msk   (_U_(0xFFF) << EVSYS_CHSTATUS_USRRDY_Pos)
+#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
+#define EVSYS_CHSTATUS_CHBUSY0_Pos  16           /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
+#define EVSYS_CHSTATUS_CHBUSY0      (_U_(1) << EVSYS_CHSTATUS_CHBUSY0_Pos)
+#define EVSYS_CHSTATUS_CHBUSY1_Pos  17           /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
+#define EVSYS_CHSTATUS_CHBUSY1      (_U_(1) << EVSYS_CHSTATUS_CHBUSY1_Pos)
+#define EVSYS_CHSTATUS_CHBUSY2_Pos  18           /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
+#define EVSYS_CHSTATUS_CHBUSY2      (_U_(1) << EVSYS_CHSTATUS_CHBUSY2_Pos)
+#define EVSYS_CHSTATUS_CHBUSY3_Pos  19           /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
+#define EVSYS_CHSTATUS_CHBUSY3      (_U_(1) << EVSYS_CHSTATUS_CHBUSY3_Pos)
+#define EVSYS_CHSTATUS_CHBUSY4_Pos  20           /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
+#define EVSYS_CHSTATUS_CHBUSY4      (_U_(1) << EVSYS_CHSTATUS_CHBUSY4_Pos)
+#define EVSYS_CHSTATUS_CHBUSY5_Pos  21           /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
+#define EVSYS_CHSTATUS_CHBUSY5      (_U_(1) << EVSYS_CHSTATUS_CHBUSY5_Pos)
+#define EVSYS_CHSTATUS_CHBUSY6_Pos  22           /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
+#define EVSYS_CHSTATUS_CHBUSY6      (_U_(1) << EVSYS_CHSTATUS_CHBUSY6_Pos)
+#define EVSYS_CHSTATUS_CHBUSY7_Pos  23           /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
+#define EVSYS_CHSTATUS_CHBUSY7      (_U_(1) << EVSYS_CHSTATUS_CHBUSY7_Pos)
+#define EVSYS_CHSTATUS_CHBUSY8_Pos  24           /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
+#define EVSYS_CHSTATUS_CHBUSY8      (_U_(1) << EVSYS_CHSTATUS_CHBUSY8_Pos)
+#define EVSYS_CHSTATUS_CHBUSY9_Pos  25           /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
+#define EVSYS_CHSTATUS_CHBUSY9      (_U_(1) << EVSYS_CHSTATUS_CHBUSY9_Pos)
+#define EVSYS_CHSTATUS_CHBUSY10_Pos 26           /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
+#define EVSYS_CHSTATUS_CHBUSY10     (_U_(1) << EVSYS_CHSTATUS_CHBUSY10_Pos)
+#define EVSYS_CHSTATUS_CHBUSY11_Pos 27           /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
+#define EVSYS_CHSTATUS_CHBUSY11     (_U_(1) << EVSYS_CHSTATUS_CHBUSY11_Pos)
+#define EVSYS_CHSTATUS_CHBUSY_Pos   16           /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
+#define EVSYS_CHSTATUS_CHBUSY_Msk   (_U_(0xFFF) << EVSYS_CHSTATUS_CHBUSY_Pos)
+#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
+#define EVSYS_CHSTATUS_MASK         _U_(0x0FFF0FFF) /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t OVR8:1;           /*!< bit:      8  Channel 8 Overrun Interrupt Enable */
+    uint32_t OVR9:1;           /*!< bit:      9  Channel 9 Overrun Interrupt Enable */
+    uint32_t OVR10:1;          /*!< bit:     10  Channel 10 Overrun Interrupt Enable */
+    uint32_t OVR11:1;          /*!< bit:     11  Channel 11 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t EVD0:1;           /*!< bit:     16  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:     17  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     18  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     19  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     20  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     21  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     22  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     23  Channel 7 Event Detection Interrupt Enable */
+    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
+    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
+    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
+    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:12;           /*!< bit:  0..11  Channel x Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t EVD:12;           /*!< bit: 16..27  Channel x Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENCLR_OFFSET       0x10         /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
+#define EVSYS_INTENCLR_RESETVALUE   _U_(0x00000000) /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EVSYS_INTENCLR_OVR0_Pos     0            /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR0         (_U_(1) << EVSYS_INTENCLR_OVR0_Pos)
+#define EVSYS_INTENCLR_OVR1_Pos     1            /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR1         (_U_(1) << EVSYS_INTENCLR_OVR1_Pos)
+#define EVSYS_INTENCLR_OVR2_Pos     2            /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR2         (_U_(1) << EVSYS_INTENCLR_OVR2_Pos)
+#define EVSYS_INTENCLR_OVR3_Pos     3            /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR3         (_U_(1) << EVSYS_INTENCLR_OVR3_Pos)
+#define EVSYS_INTENCLR_OVR4_Pos     4            /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR4         (_U_(1) << EVSYS_INTENCLR_OVR4_Pos)
+#define EVSYS_INTENCLR_OVR5_Pos     5            /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR5         (_U_(1) << EVSYS_INTENCLR_OVR5_Pos)
+#define EVSYS_INTENCLR_OVR6_Pos     6            /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR6         (_U_(1) << EVSYS_INTENCLR_OVR6_Pos)
+#define EVSYS_INTENCLR_OVR7_Pos     7            /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR7         (_U_(1) << EVSYS_INTENCLR_OVR7_Pos)
+#define EVSYS_INTENCLR_OVR8_Pos     8            /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR8         (_U_(1) << EVSYS_INTENCLR_OVR8_Pos)
+#define EVSYS_INTENCLR_OVR9_Pos     9            /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR9         (_U_(1) << EVSYS_INTENCLR_OVR9_Pos)
+#define EVSYS_INTENCLR_OVR10_Pos    10           /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR10        (_U_(1) << EVSYS_INTENCLR_OVR10_Pos)
+#define EVSYS_INTENCLR_OVR11_Pos    11           /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR11        (_U_(1) << EVSYS_INTENCLR_OVR11_Pos)
+#define EVSYS_INTENCLR_OVR_Pos      0            /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR_Msk      (_U_(0xFFF) << EVSYS_INTENCLR_OVR_Pos)
+#define EVSYS_INTENCLR_OVR(value)   (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
+#define EVSYS_INTENCLR_EVD0_Pos     16           /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD0         (_U_(1) << EVSYS_INTENCLR_EVD0_Pos)
+#define EVSYS_INTENCLR_EVD1_Pos     17           /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD1         (_U_(1) << EVSYS_INTENCLR_EVD1_Pos)
+#define EVSYS_INTENCLR_EVD2_Pos     18           /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD2         (_U_(1) << EVSYS_INTENCLR_EVD2_Pos)
+#define EVSYS_INTENCLR_EVD3_Pos     19           /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD3         (_U_(1) << EVSYS_INTENCLR_EVD3_Pos)
+#define EVSYS_INTENCLR_EVD4_Pos     20           /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD4         (_U_(1) << EVSYS_INTENCLR_EVD4_Pos)
+#define EVSYS_INTENCLR_EVD5_Pos     21           /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD5         (_U_(1) << EVSYS_INTENCLR_EVD5_Pos)
+#define EVSYS_INTENCLR_EVD6_Pos     22           /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD6         (_U_(1) << EVSYS_INTENCLR_EVD6_Pos)
+#define EVSYS_INTENCLR_EVD7_Pos     23           /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD7         (_U_(1) << EVSYS_INTENCLR_EVD7_Pos)
+#define EVSYS_INTENCLR_EVD8_Pos     24           /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD8         (_U_(1) << EVSYS_INTENCLR_EVD8_Pos)
+#define EVSYS_INTENCLR_EVD9_Pos     25           /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD9         (_U_(1) << EVSYS_INTENCLR_EVD9_Pos)
+#define EVSYS_INTENCLR_EVD10_Pos    26           /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD10        (_U_(1) << EVSYS_INTENCLR_EVD10_Pos)
+#define EVSYS_INTENCLR_EVD11_Pos    27           /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD11        (_U_(1) << EVSYS_INTENCLR_EVD11_Pos)
+#define EVSYS_INTENCLR_EVD_Pos      16           /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD_Msk      (_U_(0xFFF) << EVSYS_INTENCLR_EVD_Pos)
+#define EVSYS_INTENCLR_EVD(value)   (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
+#define EVSYS_INTENCLR_MASK         _U_(0x0FFF0FFF) /**< \brief (EVSYS_INTENCLR) MASK Register */
+
+/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun Interrupt Enable */
+    uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun Interrupt Enable */
+    uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun Interrupt Enable */
+    uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun Interrupt Enable */
+    uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun Interrupt Enable */
+    uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun Interrupt Enable */
+    uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun Interrupt Enable */
+    uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun Interrupt Enable */
+    uint32_t OVR8:1;           /*!< bit:      8  Channel 8 Overrun Interrupt Enable */
+    uint32_t OVR9:1;           /*!< bit:      9  Channel 9 Overrun Interrupt Enable */
+    uint32_t OVR10:1;          /*!< bit:     10  Channel 10 Overrun Interrupt Enable */
+    uint32_t OVR11:1;          /*!< bit:     11  Channel 11 Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t EVD0:1;           /*!< bit:     16  Channel 0 Event Detection Interrupt Enable */
+    uint32_t EVD1:1;           /*!< bit:     17  Channel 1 Event Detection Interrupt Enable */
+    uint32_t EVD2:1;           /*!< bit:     18  Channel 2 Event Detection Interrupt Enable */
+    uint32_t EVD3:1;           /*!< bit:     19  Channel 3 Event Detection Interrupt Enable */
+    uint32_t EVD4:1;           /*!< bit:     20  Channel 4 Event Detection Interrupt Enable */
+    uint32_t EVD5:1;           /*!< bit:     21  Channel 5 Event Detection Interrupt Enable */
+    uint32_t EVD6:1;           /*!< bit:     22  Channel 6 Event Detection Interrupt Enable */
+    uint32_t EVD7:1;           /*!< bit:     23  Channel 7 Event Detection Interrupt Enable */
+    uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection Interrupt Enable */
+    uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection Interrupt Enable */
+    uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection Interrupt Enable */
+    uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t OVR:12;           /*!< bit:  0..11  Channel x Overrun Interrupt Enable */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t EVD:12;           /*!< bit: 16..27  Channel x Event Detection Interrupt Enable */
+    uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENSET_OFFSET       0x14         /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
+#define EVSYS_INTENSET_RESETVALUE   _U_(0x00000000) /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
+
+#define EVSYS_INTENSET_OVR0_Pos     0            /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR0         (_U_(1) << EVSYS_INTENSET_OVR0_Pos)
+#define EVSYS_INTENSET_OVR1_Pos     1            /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR1         (_U_(1) << EVSYS_INTENSET_OVR1_Pos)
+#define EVSYS_INTENSET_OVR2_Pos     2            /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR2         (_U_(1) << EVSYS_INTENSET_OVR2_Pos)
+#define EVSYS_INTENSET_OVR3_Pos     3            /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR3         (_U_(1) << EVSYS_INTENSET_OVR3_Pos)
+#define EVSYS_INTENSET_OVR4_Pos     4            /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR4         (_U_(1) << EVSYS_INTENSET_OVR4_Pos)
+#define EVSYS_INTENSET_OVR5_Pos     5            /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR5         (_U_(1) << EVSYS_INTENSET_OVR5_Pos)
+#define EVSYS_INTENSET_OVR6_Pos     6            /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR6         (_U_(1) << EVSYS_INTENSET_OVR6_Pos)
+#define EVSYS_INTENSET_OVR7_Pos     7            /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR7         (_U_(1) << EVSYS_INTENSET_OVR7_Pos)
+#define EVSYS_INTENSET_OVR8_Pos     8            /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR8         (_U_(1) << EVSYS_INTENSET_OVR8_Pos)
+#define EVSYS_INTENSET_OVR9_Pos     9            /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR9         (_U_(1) << EVSYS_INTENSET_OVR9_Pos)
+#define EVSYS_INTENSET_OVR10_Pos    10           /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR10        (_U_(1) << EVSYS_INTENSET_OVR10_Pos)
+#define EVSYS_INTENSET_OVR11_Pos    11           /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR11        (_U_(1) << EVSYS_INTENSET_OVR11_Pos)
+#define EVSYS_INTENSET_OVR_Pos      0            /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR_Msk      (_U_(0xFFF) << EVSYS_INTENSET_OVR_Pos)
+#define EVSYS_INTENSET_OVR(value)   (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
+#define EVSYS_INTENSET_EVD0_Pos     16           /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD0         (_U_(1) << EVSYS_INTENSET_EVD0_Pos)
+#define EVSYS_INTENSET_EVD1_Pos     17           /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD1         (_U_(1) << EVSYS_INTENSET_EVD1_Pos)
+#define EVSYS_INTENSET_EVD2_Pos     18           /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD2         (_U_(1) << EVSYS_INTENSET_EVD2_Pos)
+#define EVSYS_INTENSET_EVD3_Pos     19           /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD3         (_U_(1) << EVSYS_INTENSET_EVD3_Pos)
+#define EVSYS_INTENSET_EVD4_Pos     20           /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD4         (_U_(1) << EVSYS_INTENSET_EVD4_Pos)
+#define EVSYS_INTENSET_EVD5_Pos     21           /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD5         (_U_(1) << EVSYS_INTENSET_EVD5_Pos)
+#define EVSYS_INTENSET_EVD6_Pos     22           /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD6         (_U_(1) << EVSYS_INTENSET_EVD6_Pos)
+#define EVSYS_INTENSET_EVD7_Pos     23           /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD7         (_U_(1) << EVSYS_INTENSET_EVD7_Pos)
+#define EVSYS_INTENSET_EVD8_Pos     24           /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD8         (_U_(1) << EVSYS_INTENSET_EVD8_Pos)
+#define EVSYS_INTENSET_EVD9_Pos     25           /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD9         (_U_(1) << EVSYS_INTENSET_EVD9_Pos)
+#define EVSYS_INTENSET_EVD10_Pos    26           /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD10        (_U_(1) << EVSYS_INTENSET_EVD10_Pos)
+#define EVSYS_INTENSET_EVD11_Pos    27           /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD11        (_U_(1) << EVSYS_INTENSET_EVD11_Pos)
+#define EVSYS_INTENSET_EVD_Pos      16           /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD_Msk      (_U_(0xFFF) << EVSYS_INTENSET_EVD_Pos)
+#define EVSYS_INTENSET_EVD(value)   (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
+#define EVSYS_INTENSET_MASK         _U_(0x0FFF0FFF) /**< \brief (EVSYS_INTENSET) MASK Register */
+
+/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun                  */
+    __I uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun                  */
+    __I uint32_t OVR2:1;           /*!< bit:      2  Channel 2 Overrun                  */
+    __I uint32_t OVR3:1;           /*!< bit:      3  Channel 3 Overrun                  */
+    __I uint32_t OVR4:1;           /*!< bit:      4  Channel 4 Overrun                  */
+    __I uint32_t OVR5:1;           /*!< bit:      5  Channel 5 Overrun                  */
+    __I uint32_t OVR6:1;           /*!< bit:      6  Channel 6 Overrun                  */
+    __I uint32_t OVR7:1;           /*!< bit:      7  Channel 7 Overrun                  */
+    __I uint32_t OVR8:1;           /*!< bit:      8  Channel 8 Overrun                  */
+    __I uint32_t OVR9:1;           /*!< bit:      9  Channel 9 Overrun                  */
+    __I uint32_t OVR10:1;          /*!< bit:     10  Channel 10 Overrun                 */
+    __I uint32_t OVR11:1;          /*!< bit:     11  Channel 11 Overrun                 */
+    __I uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    __I uint32_t EVD0:1;           /*!< bit:     16  Channel 0 Event Detection          */
+    __I uint32_t EVD1:1;           /*!< bit:     17  Channel 1 Event Detection          */
+    __I uint32_t EVD2:1;           /*!< bit:     18  Channel 2 Event Detection          */
+    __I uint32_t EVD3:1;           /*!< bit:     19  Channel 3 Event Detection          */
+    __I uint32_t EVD4:1;           /*!< bit:     20  Channel 4 Event Detection          */
+    __I uint32_t EVD5:1;           /*!< bit:     21  Channel 5 Event Detection          */
+    __I uint32_t EVD6:1;           /*!< bit:     22  Channel 6 Event Detection          */
+    __I uint32_t EVD7:1;           /*!< bit:     23  Channel 7 Event Detection          */
+    __I uint32_t EVD8:1;           /*!< bit:     24  Channel 8 Event Detection          */
+    __I uint32_t EVD9:1;           /*!< bit:     25  Channel 9 Event Detection          */
+    __I uint32_t EVD10:1;          /*!< bit:     26  Channel 10 Event Detection         */
+    __I uint32_t EVD11:1;          /*!< bit:     27  Channel 11 Event Detection         */
+    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    __I uint32_t OVR:12;           /*!< bit:  0..11  Channel x Overrun                  */
+    __I uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    __I uint32_t EVD:12;           /*!< bit: 16..27  Channel x Event Detection          */
+    __I uint32_t :4;               /*!< bit: 28..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTFLAG_OFFSET        0x18         /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EVSYS_INTFLAG_RESETVALUE    _U_(0x00000000) /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EVSYS_INTFLAG_OVR0_Pos      0            /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
+#define EVSYS_INTFLAG_OVR0          (_U_(1) << EVSYS_INTFLAG_OVR0_Pos)
+#define EVSYS_INTFLAG_OVR1_Pos      1            /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
+#define EVSYS_INTFLAG_OVR1          (_U_(1) << EVSYS_INTFLAG_OVR1_Pos)
+#define EVSYS_INTFLAG_OVR2_Pos      2            /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
+#define EVSYS_INTFLAG_OVR2          (_U_(1) << EVSYS_INTFLAG_OVR2_Pos)
+#define EVSYS_INTFLAG_OVR3_Pos      3            /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
+#define EVSYS_INTFLAG_OVR3          (_U_(1) << EVSYS_INTFLAG_OVR3_Pos)
+#define EVSYS_INTFLAG_OVR4_Pos      4            /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
+#define EVSYS_INTFLAG_OVR4          (_U_(1) << EVSYS_INTFLAG_OVR4_Pos)
+#define EVSYS_INTFLAG_OVR5_Pos      5            /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
+#define EVSYS_INTFLAG_OVR5          (_U_(1) << EVSYS_INTFLAG_OVR5_Pos)
+#define EVSYS_INTFLAG_OVR6_Pos      6            /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
+#define EVSYS_INTFLAG_OVR6          (_U_(1) << EVSYS_INTFLAG_OVR6_Pos)
+#define EVSYS_INTFLAG_OVR7_Pos      7            /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
+#define EVSYS_INTFLAG_OVR7          (_U_(1) << EVSYS_INTFLAG_OVR7_Pos)
+#define EVSYS_INTFLAG_OVR8_Pos      8            /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
+#define EVSYS_INTFLAG_OVR8          (_U_(1) << EVSYS_INTFLAG_OVR8_Pos)
+#define EVSYS_INTFLAG_OVR9_Pos      9            /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
+#define EVSYS_INTFLAG_OVR9          (_U_(1) << EVSYS_INTFLAG_OVR9_Pos)
+#define EVSYS_INTFLAG_OVR10_Pos     10           /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
+#define EVSYS_INTFLAG_OVR10         (_U_(1) << EVSYS_INTFLAG_OVR10_Pos)
+#define EVSYS_INTFLAG_OVR11_Pos     11           /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
+#define EVSYS_INTFLAG_OVR11         (_U_(1) << EVSYS_INTFLAG_OVR11_Pos)
+#define EVSYS_INTFLAG_OVR_Pos       0            /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
+#define EVSYS_INTFLAG_OVR_Msk       (_U_(0xFFF) << EVSYS_INTFLAG_OVR_Pos)
+#define EVSYS_INTFLAG_OVR(value)    (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
+#define EVSYS_INTFLAG_EVD0_Pos      16           /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
+#define EVSYS_INTFLAG_EVD0          (_U_(1) << EVSYS_INTFLAG_EVD0_Pos)
+#define EVSYS_INTFLAG_EVD1_Pos      17           /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
+#define EVSYS_INTFLAG_EVD1          (_U_(1) << EVSYS_INTFLAG_EVD1_Pos)
+#define EVSYS_INTFLAG_EVD2_Pos      18           /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
+#define EVSYS_INTFLAG_EVD2          (_U_(1) << EVSYS_INTFLAG_EVD2_Pos)
+#define EVSYS_INTFLAG_EVD3_Pos      19           /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
+#define EVSYS_INTFLAG_EVD3          (_U_(1) << EVSYS_INTFLAG_EVD3_Pos)
+#define EVSYS_INTFLAG_EVD4_Pos      20           /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
+#define EVSYS_INTFLAG_EVD4          (_U_(1) << EVSYS_INTFLAG_EVD4_Pos)
+#define EVSYS_INTFLAG_EVD5_Pos      21           /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
+#define EVSYS_INTFLAG_EVD5          (_U_(1) << EVSYS_INTFLAG_EVD5_Pos)
+#define EVSYS_INTFLAG_EVD6_Pos      22           /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
+#define EVSYS_INTFLAG_EVD6          (_U_(1) << EVSYS_INTFLAG_EVD6_Pos)
+#define EVSYS_INTFLAG_EVD7_Pos      23           /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
+#define EVSYS_INTFLAG_EVD7          (_U_(1) << EVSYS_INTFLAG_EVD7_Pos)
+#define EVSYS_INTFLAG_EVD8_Pos      24           /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
+#define EVSYS_INTFLAG_EVD8          (_U_(1) << EVSYS_INTFLAG_EVD8_Pos)
+#define EVSYS_INTFLAG_EVD9_Pos      25           /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
+#define EVSYS_INTFLAG_EVD9          (_U_(1) << EVSYS_INTFLAG_EVD9_Pos)
+#define EVSYS_INTFLAG_EVD10_Pos     26           /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
+#define EVSYS_INTFLAG_EVD10         (_U_(1) << EVSYS_INTFLAG_EVD10_Pos)
+#define EVSYS_INTFLAG_EVD11_Pos     27           /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
+#define EVSYS_INTFLAG_EVD11         (_U_(1) << EVSYS_INTFLAG_EVD11_Pos)
+#define EVSYS_INTFLAG_EVD_Pos       16           /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
+#define EVSYS_INTFLAG_EVD_Msk       (_U_(0xFFF) << EVSYS_INTFLAG_EVD_Pos)
+#define EVSYS_INTFLAG_EVD(value)    (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
+#define EVSYS_INTFLAG_MASK          _U_(0x0FFF0FFF) /**< \brief (EVSYS_INTFLAG) MASK Register */
+
+/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x1C) ( /W 32) Software Event -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHANNEL0:1;       /*!< bit:      0  Channel 0 Software Selection       */
+    uint32_t CHANNEL1:1;       /*!< bit:      1  Channel 1 Software Selection       */
+    uint32_t CHANNEL2:1;       /*!< bit:      2  Channel 2 Software Selection       */
+    uint32_t CHANNEL3:1;       /*!< bit:      3  Channel 3 Software Selection       */
+    uint32_t CHANNEL4:1;       /*!< bit:      4  Channel 4 Software Selection       */
+    uint32_t CHANNEL5:1;       /*!< bit:      5  Channel 5 Software Selection       */
+    uint32_t CHANNEL6:1;       /*!< bit:      6  Channel 6 Software Selection       */
+    uint32_t CHANNEL7:1;       /*!< bit:      7  Channel 7 Software Selection       */
+    uint32_t CHANNEL8:1;       /*!< bit:      8  Channel 8 Software Selection       */
+    uint32_t CHANNEL9:1;       /*!< bit:      9  Channel 9 Software Selection       */
+    uint32_t CHANNEL10:1;      /*!< bit:     10  Channel 10 Software Selection      */
+    uint32_t CHANNEL11:1;      /*!< bit:     11  Channel 11 Software Selection      */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t CHANNEL:12;       /*!< bit:  0..11  Channel x Software Selection       */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_SWEVT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_SWEVT_OFFSET          0x1C         /**< \brief (EVSYS_SWEVT offset) Software Event */
+#define EVSYS_SWEVT_RESETVALUE      _U_(0x00000000) /**< \brief (EVSYS_SWEVT reset_value) Software Event */
+
+#define EVSYS_SWEVT_CHANNEL0_Pos    0            /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */
+#define EVSYS_SWEVT_CHANNEL0        (_U_(1) << EVSYS_SWEVT_CHANNEL0_Pos)
+#define EVSYS_SWEVT_CHANNEL1_Pos    1            /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */
+#define EVSYS_SWEVT_CHANNEL1        (_U_(1) << EVSYS_SWEVT_CHANNEL1_Pos)
+#define EVSYS_SWEVT_CHANNEL2_Pos    2            /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */
+#define EVSYS_SWEVT_CHANNEL2        (_U_(1) << EVSYS_SWEVT_CHANNEL2_Pos)
+#define EVSYS_SWEVT_CHANNEL3_Pos    3            /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */
+#define EVSYS_SWEVT_CHANNEL3        (_U_(1) << EVSYS_SWEVT_CHANNEL3_Pos)
+#define EVSYS_SWEVT_CHANNEL4_Pos    4            /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */
+#define EVSYS_SWEVT_CHANNEL4        (_U_(1) << EVSYS_SWEVT_CHANNEL4_Pos)
+#define EVSYS_SWEVT_CHANNEL5_Pos    5            /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */
+#define EVSYS_SWEVT_CHANNEL5        (_U_(1) << EVSYS_SWEVT_CHANNEL5_Pos)
+#define EVSYS_SWEVT_CHANNEL6_Pos    6            /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */
+#define EVSYS_SWEVT_CHANNEL6        (_U_(1) << EVSYS_SWEVT_CHANNEL6_Pos)
+#define EVSYS_SWEVT_CHANNEL7_Pos    7            /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */
+#define EVSYS_SWEVT_CHANNEL7        (_U_(1) << EVSYS_SWEVT_CHANNEL7_Pos)
+#define EVSYS_SWEVT_CHANNEL8_Pos    8            /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */
+#define EVSYS_SWEVT_CHANNEL8        (_U_(1) << EVSYS_SWEVT_CHANNEL8_Pos)
+#define EVSYS_SWEVT_CHANNEL9_Pos    9            /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */
+#define EVSYS_SWEVT_CHANNEL9        (_U_(1) << EVSYS_SWEVT_CHANNEL9_Pos)
+#define EVSYS_SWEVT_CHANNEL10_Pos   10           /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */
+#define EVSYS_SWEVT_CHANNEL10       (_U_(1) << EVSYS_SWEVT_CHANNEL10_Pos)
+#define EVSYS_SWEVT_CHANNEL11_Pos   11           /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */
+#define EVSYS_SWEVT_CHANNEL11       (_U_(1) << EVSYS_SWEVT_CHANNEL11_Pos)
+#define EVSYS_SWEVT_CHANNEL_Pos     0            /**< \brief (EVSYS_SWEVT) Channel x Software Selection */
+#define EVSYS_SWEVT_CHANNEL_Msk     (_U_(0xFFF) << EVSYS_SWEVT_CHANNEL_Pos)
+#define EVSYS_SWEVT_CHANNEL(value)  (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
+#define EVSYS_SWEVT_MASK            _U_(0x00000FFF) /**< \brief (EVSYS_SWEVT) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x20) (R/W 32) Channel n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVGEN:7;          /*!< bit:  0.. 6  Event Generator Selection          */
+    uint32_t :1;               /*!< bit:      7  Reserved                           */
+    uint32_t PATH:2;           /*!< bit:  8.. 9  Path Selection                     */
+    uint32_t EDGSEL:2;         /*!< bit: 10..11  Edge Detection Selection           */
+    uint32_t :2;               /*!< bit: 12..13  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:     14  Run in standby                     */
+    uint32_t ONDEMAND:1;       /*!< bit:     15  Generic Clock On Demand            */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET        0x20         /**< \brief (EVSYS_CHANNEL offset) Channel n */
+#define EVSYS_CHANNEL_RESETVALUE    _U_(0x00008000) /**< \brief (EVSYS_CHANNEL reset_value) Channel n */
+
+#define EVSYS_CHANNEL_EVGEN_Pos     0            /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk     (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value)  (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
+#define EVSYS_CHANNEL_PATH_Pos      8            /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk      (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value)   (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
+#define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0)   /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1)   /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2)   /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos    10           /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk    (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
+#define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0)   /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1)   /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2)   /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3)   /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_RUNSTDBY_Pos  14           /**< \brief (EVSYS_CHANNEL) Run in standby */
+#define EVSYS_CHANNEL_RUNSTDBY      (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)
+#define EVSYS_CHANNEL_ONDEMAND_Pos  15           /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */
+#define EVSYS_CHANNEL_ONDEMAND      (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)
+#define EVSYS_CHANNEL_MASK          _U_(0x0000CF7F) /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x80) (R/W 32) User Multiplexer n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t CHANNEL:5;        /*!< bit:  0.. 4  Channel Event Selection            */
+    uint32_t :27;              /*!< bit:  5..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET           0x80         /**< \brief (EVSYS_USER offset) User Multiplexer n */
+#define EVSYS_USER_RESETVALUE       _U_(0x00000000) /**< \brief (EVSYS_USER reset_value) User Multiplexer n */
+
+#define EVSYS_USER_CHANNEL_Pos      0            /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk      (_U_(0x1F) << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value)   (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
+#define EVSYS_USER_MASK             _U_(0x0000001F) /**< \brief (EVSYS_USER) MASK Register */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO EVSYS_CTRLA_Type          CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control */
+       RoReg8                    Reserved1[0xB];
+  __I  EVSYS_CHSTATUS_Type       CHSTATUS;    /**< \brief Offset: 0x0C (R/  32) Channel Status */
+  __IO EVSYS_INTENCLR_Type       INTENCLR;    /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+  __IO EVSYS_INTENSET_Type       INTENSET;    /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+  __IO EVSYS_INTFLAG_Type        INTFLAG;     /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+  __O  EVSYS_SWEVT_Type          SWEVT;       /**< \brief Offset: 0x1C ( /W 32) Software Event */
+  __IO EVSYS_CHANNEL_Type        CHANNEL[12]; /**< \brief Offset: 0x20 (R/W 32) Channel n */
+       RoReg8                    Reserved2[0x30];
+  __IO EVSYS_USER_Type           USER[45];    /**< \brief Offset: 0x80 (R/W 32) User Multiplexer n */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_EVSYS_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/gclk.h

@@ -0,0 +1,251 @@
+/**
+ * \file
+ *
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_GCLK_COMPONENT_
+#define _SAMR34_GCLK_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR GCLK */
+/* ========================================================================== */
+/** \addtogroup SAMR34_GCLK Generic Clock Generator */
+/*@{*/
+
+#define GCLK_U2122
+#define REV_GCLK                    0x111
+
+/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W  8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SWRST:1;          /*!< bit:      0  Software Reset                     */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} GCLK_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CTRLA_OFFSET           0x00         /**< \brief (GCLK_CTRLA offset) Control */
+#define GCLK_CTRLA_RESETVALUE       _U_(0x00)    /**< \brief (GCLK_CTRLA reset_value) Control */
+
+#define GCLK_CTRLA_SWRST_Pos        0            /**< \brief (GCLK_CTRLA) Software Reset */
+#define GCLK_CTRLA_SWRST            (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
+#define GCLK_CTRLA_MASK             _U_(0x01)    /**< \brief (GCLK_CTRLA) MASK Register */
+
+/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/  32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SWRST:1;          /*!< bit:      0  Software Reset Synchroniation Busy bit */
+    uint32_t :1;               /*!< bit:      1  Reserved                           */
+    uint32_t GENCTRL0:1;       /*!< bit:      2  Generic Clock Generator Control 0 Synchronization Busy bits */
+    uint32_t GENCTRL1:1;       /*!< bit:      3  Generic Clock Generator Control 1 Synchronization Busy bits */
+    uint32_t GENCTRL2:1;       /*!< bit:      4  Generic Clock Generator Control 2 Synchronization Busy bits */
+    uint32_t GENCTRL3:1;       /*!< bit:      5  Generic Clock Generator Control 3 Synchronization Busy bits */
+    uint32_t GENCTRL4:1;       /*!< bit:      6  Generic Clock Generator Control 4 Synchronization Busy bits */
+    uint32_t GENCTRL5:1;       /*!< bit:      7  Generic Clock Generator Control 5 Synchronization Busy bits */
+    uint32_t GENCTRL6:1;       /*!< bit:      8  Generic Clock Generator Control 6 Synchronization Busy bits */
+    uint32_t GENCTRL7:1;       /*!< bit:      9  Generic Clock Generator Control 7 Synchronization Busy bits */
+    uint32_t GENCTRL8:1;       /*!< bit:     10  Generic Clock Generator Control 8 Synchronization Busy bits */
+    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t GENCTRL:9;        /*!< bit:  2..10  Generic Clock Generator Control x Synchronization Busy bits */
+    uint32_t :21;              /*!< bit: 11..31  Reserved                           */
+  } vec;                       /*!< Structure used for vec  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_SYNCBUSY_OFFSET        0x04         /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */
+#define GCLK_SYNCBUSY_RESETVALUE    _U_(0x00000000) /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */
+
+#define GCLK_SYNCBUSY_SWRST_Pos     0            /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */
+#define GCLK_SYNCBUSY_SWRST         (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)
+#define GCLK_SYNCBUSY_GENCTRL0_Pos  2            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL0      (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)
+#define GCLK_SYNCBUSY_GENCTRL1_Pos  3            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL1      (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)
+#define GCLK_SYNCBUSY_GENCTRL2_Pos  4            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL2      (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)
+#define GCLK_SYNCBUSY_GENCTRL3_Pos  5            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL3      (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)
+#define GCLK_SYNCBUSY_GENCTRL4_Pos  6            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL4      (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)
+#define GCLK_SYNCBUSY_GENCTRL5_Pos  7            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL5      (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
+#define GCLK_SYNCBUSY_GENCTRL6_Pos  8            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL6      (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)
+#define GCLK_SYNCBUSY_GENCTRL7_Pos  9            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL7      (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)
+#define GCLK_SYNCBUSY_GENCTRL8_Pos  10           /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL8      (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_Pos   2            /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits */
+#define GCLK_SYNCBUSY_GENCTRL_Msk   (_U_(0x1FF) << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100)   /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
+#define GCLK_SYNCBUSY_MASK          _U_(0x000007FD) /**< \brief (GCLK_SYNCBUSY) MASK Register */
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SRC:4;            /*!< bit:  0.. 3  Source Select                      */
+    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
+    uint32_t GENEN:1;          /*!< bit:      8  Generic Clock Generator Enable     */
+    uint32_t IDC:1;            /*!< bit:      9  Improve Duty Cycle                 */
+    uint32_t OOV:1;            /*!< bit:     10  Output Off Value                   */
+    uint32_t OE:1;             /*!< bit:     11  Output Enable                      */
+    uint32_t DIVSEL:1;         /*!< bit:     12  Divide Selection                   */
+    uint32_t RUNSTDBY:1;       /*!< bit:     13  Run in Standby                     */
+    uint32_t :2;               /*!< bit: 14..15  Reserved                           */
+    uint32_t DIV:16;           /*!< bit: 16..31  Division Factor                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_GENCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENCTRL_OFFSET         0x20         /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE     _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+
+#define GCLK_GENCTRL_SRC_Pos        0            /**< \brief (GCLK_GENCTRL) Source Select */
+#define GCLK_GENCTRL_SRC_Msk        (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC(value)     (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
+#define   GCLK_GENCTRL_SRC_XOSC_Val       _U_(0x0)   /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
+#define   GCLK_GENCTRL_SRC_GCLKIN_Val     _U_(0x1)   /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define   GCLK_GENCTRL_SRC_GCLKGEN1_Val   _U_(0x2)   /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define   GCLK_GENCTRL_SRC_OSCULP32K_Val  _U_(0x3)   /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC32K_Val     _U_(0x4)   /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_XOSC32K_Val    _U_(0x5)   /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define   GCLK_GENCTRL_SRC_OSC16M_Val     _U_(0x6)   /**< \brief (GCLK_GENCTRL) OSC16M oscillator output */
+#define   GCLK_GENCTRL_SRC_DFLL48M_Val    _U_(0x7)   /**< \brief (GCLK_GENCTRL) DFLL48M output */
+#define   GCLK_GENCTRL_SRC_DPLL96M_Val    _U_(0x8)   /**< \brief (GCLK_GENCTRL) DPLL96M output */
+#define GCLK_GENCTRL_SRC_XOSC       (GCLK_GENCTRL_SRC_XOSC_Val     << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKIN     (GCLK_GENCTRL_SRC_GCLKIN_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKGEN1   (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSCULP32K  (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC32K     (GCLK_GENCTRL_SRC_OSC32K_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC32K    (GCLK_GENCTRL_SRC_XOSC32K_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC16M     (GCLK_GENCTRL_SRC_OSC16M_Val   << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DFLL48M    (GCLK_GENCTRL_SRC_DFLL48M_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DPLL96M    (GCLK_GENCTRL_SRC_DPLL96M_Val  << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_GENEN_Pos      8            /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
+#define GCLK_GENCTRL_GENEN          (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_IDC_Pos        9            /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
+#define GCLK_GENCTRL_IDC            (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_OOV_Pos        10           /**< \brief (GCLK_GENCTRL) Output Off Value */
+#define GCLK_GENCTRL_OOV            (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OE_Pos         11           /**< \brief (GCLK_GENCTRL) Output Enable */
+#define GCLK_GENCTRL_OE             (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_DIVSEL_Pos     12           /**< \brief (GCLK_GENCTRL) Divide Selection */
+#define GCLK_GENCTRL_DIVSEL         (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_RUNSTDBY_Pos   13           /**< \brief (GCLK_GENCTRL) Run in Standby */
+#define GCLK_GENCTRL_RUNSTDBY       (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_DIV_Pos        16           /**< \brief (GCLK_GENCTRL) Division Factor */
+#define GCLK_GENCTRL_DIV_Msk        (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)
+#define GCLK_GENCTRL_DIV(value)     (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
+#define GCLK_GENCTRL_MASK           _U_(0xFFFF3F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
+
+/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t GEN:4;            /*!< bit:  0.. 3  Generic Clock Generator            */
+    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint32_t CHEN:1;           /*!< bit:      6  Channel Enable                     */
+    uint32_t WRTLOCK:1;        /*!< bit:      7  Write Lock                         */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} GCLK_PCHCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_PCHCTRL_OFFSET         0x80         /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */
+#define GCLK_PCHCTRL_RESETVALUE     _U_(0x00000000) /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */
+
+#define GCLK_PCHCTRL_GEN_Pos        0            /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */
+#define GCLK_PCHCTRL_GEN_Msk        (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN(value)     (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
+#define   GCLK_PCHCTRL_GEN_GCLK0_Val      _U_(0x0)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */
+#define   GCLK_PCHCTRL_GEN_GCLK1_Val      _U_(0x1)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */
+#define   GCLK_PCHCTRL_GEN_GCLK2_Val      _U_(0x2)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */
+#define   GCLK_PCHCTRL_GEN_GCLK3_Val      _U_(0x3)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */
+#define   GCLK_PCHCTRL_GEN_GCLK4_Val      _U_(0x4)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */
+#define   GCLK_PCHCTRL_GEN_GCLK5_Val      _U_(0x5)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */
+#define   GCLK_PCHCTRL_GEN_GCLK6_Val      _U_(0x6)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */
+#define   GCLK_PCHCTRL_GEN_GCLK7_Val      _U_(0x7)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */
+#define   GCLK_PCHCTRL_GEN_GCLK8_Val      _U_(0x8)   /**< \brief (GCLK_PCHCTRL) Generic clock generator 8 */
+#define GCLK_PCHCTRL_GEN_GCLK0      (GCLK_PCHCTRL_GEN_GCLK0_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK1      (GCLK_PCHCTRL_GEN_GCLK1_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK2      (GCLK_PCHCTRL_GEN_GCLK2_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK3      (GCLK_PCHCTRL_GEN_GCLK3_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK4      (GCLK_PCHCTRL_GEN_GCLK4_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK5      (GCLK_PCHCTRL_GEN_GCLK5_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK6      (GCLK_PCHCTRL_GEN_GCLK6_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK7      (GCLK_PCHCTRL_GEN_GCLK7_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_GEN_GCLK8      (GCLK_PCHCTRL_GEN_GCLK8_Val    << GCLK_PCHCTRL_GEN_Pos)
+#define GCLK_PCHCTRL_CHEN_Pos       6            /**< \brief (GCLK_PCHCTRL) Channel Enable */
+#define GCLK_PCHCTRL_CHEN           (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)
+#define GCLK_PCHCTRL_WRTLOCK_Pos    7            /**< \brief (GCLK_PCHCTRL) Write Lock */
+#define GCLK_PCHCTRL_WRTLOCK        (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)
+#define GCLK_PCHCTRL_MASK           _U_(0x000000CF) /**< \brief (GCLK_PCHCTRL) MASK Register */
+
+/** \brief GCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO GCLK_CTRLA_Type           CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control */
+       RoReg8                    Reserved1[0x3];
+  __I  GCLK_SYNCBUSY_Type        SYNCBUSY;    /**< \brief Offset: 0x04 (R/  32) Synchronization Busy */
+       RoReg8                    Reserved2[0x18];
+  __IO GCLK_GENCTRL_Type         GENCTRL[9];  /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */
+       RoReg8                    Reserved3[0x3C];
+  __IO GCLK_PCHCTRL_Type         PCHCTRL[36]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */
+} Gclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_GCLK_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/mclk.h

@@ -0,0 +1,489 @@
+/**
+ * \file
+ *
+ * \brief Component description for MCLK
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_MCLK_COMPONENT_
+#define _SAMR34_MCLK_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR MCLK */
+/* ========================================================================== */
+/** \addtogroup SAMR34_MCLK Main Clock */
+/*@{*/
+
+#define MCLK_U2234
+#define REV_MCLK                    0x101
+
+/* -------- MCLK_CTRLA : (MCLK Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_CTRLA_OFFSET           0x00         /**< \brief (MCLK_CTRLA offset) Control A */
+#define MCLK_CTRLA_RESETVALUE       _U_(0x00)    /**< \brief (MCLK_CTRLA reset_value) Control A */
+#define MCLK_CTRLA_MASK             _U_(0x00)    /**< \brief (MCLK_CTRLA) MASK Register */
+
+/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTENCLR_OFFSET        0x01         /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */
+#define MCLK_INTENCLR_RESETVALUE    _U_(0x00)    /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define MCLK_INTENCLR_CKRDY_Pos     0            /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */
+#define MCLK_INTENCLR_CKRDY         (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)
+#define MCLK_INTENCLR_MASK          _U_(0x01)    /**< \brief (MCLK_INTENCLR) MASK Register */
+
+/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready Interrupt Enable       */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTENSET_OFFSET        0x02         /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */
+#define MCLK_INTENSET_RESETVALUE    _U_(0x00)    /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */
+
+#define MCLK_INTENSET_CKRDY_Pos     0            /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */
+#define MCLK_INTENSET_CKRDY         (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)
+#define MCLK_INTENSET_MASK          _U_(0x01)    /**< \brief (MCLK_INTENSET) MASK Register */
+
+/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready                        */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_INTFLAG_OFFSET         0x03         /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */
+#define MCLK_INTFLAG_RESETVALUE     _U_(0x01)    /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define MCLK_INTFLAG_CKRDY_Pos      0            /**< \brief (MCLK_INTFLAG) Clock Ready */
+#define MCLK_INTFLAG_CKRDY          (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)
+#define MCLK_INTFLAG_MASK           _U_(0x01)    /**< \brief (MCLK_INTFLAG) MASK Register */
+
+/* -------- MCLK_CPUDIV : (MCLK Offset: 0x04) (R/W  8) CPU Clock Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  CPUDIV:8;         /*!< bit:  0.. 7  CPU Clock Division Factor          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_CPUDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_CPUDIV_OFFSET          0x04         /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */
+#define MCLK_CPUDIV_RESETVALUE      _U_(0x01)    /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */
+
+#define MCLK_CPUDIV_CPUDIV_Pos      0            /**< \brief (MCLK_CPUDIV) CPU Clock Division Factor */
+#define MCLK_CPUDIV_CPUDIV_Msk      (_U_(0xFF) << MCLK_CPUDIV_CPUDIV_Pos)
+#define MCLK_CPUDIV_CPUDIV(value)   (MCLK_CPUDIV_CPUDIV_Msk & ((value) << MCLK_CPUDIV_CPUDIV_Pos))
+#define   MCLK_CPUDIV_CPUDIV_DIV1_Val     _U_(0x1)   /**< \brief (MCLK_CPUDIV) Divide by 1 */
+#define   MCLK_CPUDIV_CPUDIV_DIV2_Val     _U_(0x2)   /**< \brief (MCLK_CPUDIV) Divide by 2 */
+#define   MCLK_CPUDIV_CPUDIV_DIV4_Val     _U_(0x4)   /**< \brief (MCLK_CPUDIV) Divide by 4 */
+#define   MCLK_CPUDIV_CPUDIV_DIV8_Val     _U_(0x8)   /**< \brief (MCLK_CPUDIV) Divide by 8 */
+#define   MCLK_CPUDIV_CPUDIV_DIV16_Val    _U_(0x10)   /**< \brief (MCLK_CPUDIV) Divide by 16 */
+#define   MCLK_CPUDIV_CPUDIV_DIV32_Val    _U_(0x20)   /**< \brief (MCLK_CPUDIV) Divide by 32 */
+#define   MCLK_CPUDIV_CPUDIV_DIV64_Val    _U_(0x40)   /**< \brief (MCLK_CPUDIV) Divide by 64 */
+#define   MCLK_CPUDIV_CPUDIV_DIV128_Val   _U_(0x80)   /**< \brief (MCLK_CPUDIV) Divide by 128 */
+#define MCLK_CPUDIV_CPUDIV_DIV1     (MCLK_CPUDIV_CPUDIV_DIV1_Val   << MCLK_CPUDIV_CPUDIV_Pos)
+#define MCLK_CPUDIV_CPUDIV_DIV2     (MCLK_CPUDIV_CPUDIV_DIV2_Val   << MCLK_CPUDIV_CPUDIV_Pos)
+#define MCLK_CPUDIV_CPUDIV_DIV4     (MCLK_CPUDIV_CPUDIV_DIV4_Val   << MCLK_CPUDIV_CPUDIV_Pos)
+#define MCLK_CPUDIV_CPUDIV_DIV8     (MCLK_CPUDIV_CPUDIV_DIV8_Val   << MCLK_CPUDIV_CPUDIV_Pos)
+#define MCLK_CPUDIV_CPUDIV_DIV16    (MCLK_CPUDIV_CPUDIV_DIV16_Val  << MCLK_CPUDIV_CPUDIV_Pos)
+#define MCLK_CPUDIV_CPUDIV_DIV32    (MCLK_CPUDIV_CPUDIV_DIV32_Val  << MCLK_CPUDIV_CPUDIV_Pos)
+#define MCLK_CPUDIV_CPUDIV_DIV64    (MCLK_CPUDIV_CPUDIV_DIV64_Val  << MCLK_CPUDIV_CPUDIV_Pos)
+#define MCLK_CPUDIV_CPUDIV_DIV128   (MCLK_CPUDIV_CPUDIV_DIV128_Val << MCLK_CPUDIV_CPUDIV_Pos)
+#define MCLK_CPUDIV_MASK            _U_(0xFF)    /**< \brief (MCLK_CPUDIV) MASK Register */
+
+/* -------- MCLK_LPDIV : (MCLK Offset: 0x05) (R/W  8) Low-Power Clock Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  LPDIV:8;          /*!< bit:  0.. 7  Low-Power Clock Division Factor    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_LPDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_LPDIV_OFFSET           0x05         /**< \brief (MCLK_LPDIV offset) Low-Power Clock Division */
+#define MCLK_LPDIV_RESETVALUE       _U_(0x01)    /**< \brief (MCLK_LPDIV reset_value) Low-Power Clock Division */
+
+#define MCLK_LPDIV_LPDIV_Pos        0            /**< \brief (MCLK_LPDIV) Low-Power Clock Division Factor */
+#define MCLK_LPDIV_LPDIV_Msk        (_U_(0xFF) << MCLK_LPDIV_LPDIV_Pos)
+#define MCLK_LPDIV_LPDIV(value)     (MCLK_LPDIV_LPDIV_Msk & ((value) << MCLK_LPDIV_LPDIV_Pos))
+#define   MCLK_LPDIV_LPDIV_DIV1_Val       _U_(0x1)   /**< \brief (MCLK_LPDIV) Divide by 1 */
+#define   MCLK_LPDIV_LPDIV_DIV2_Val       _U_(0x2)   /**< \brief (MCLK_LPDIV) Divide by 2 */
+#define   MCLK_LPDIV_LPDIV_DIV4_Val       _U_(0x4)   /**< \brief (MCLK_LPDIV) Divide by 4 */
+#define   MCLK_LPDIV_LPDIV_DIV8_Val       _U_(0x8)   /**< \brief (MCLK_LPDIV) Divide by 8 */
+#define   MCLK_LPDIV_LPDIV_DIV16_Val      _U_(0x10)   /**< \brief (MCLK_LPDIV) Divide by 16 */
+#define   MCLK_LPDIV_LPDIV_DIV32_Val      _U_(0x20)   /**< \brief (MCLK_LPDIV) Divide by 32 */
+#define   MCLK_LPDIV_LPDIV_DIV64_Val      _U_(0x40)   /**< \brief (MCLK_LPDIV) Divide by 64 */
+#define   MCLK_LPDIV_LPDIV_DIV128_Val     _U_(0x80)   /**< \brief (MCLK_LPDIV) Divide by 128 */
+#define MCLK_LPDIV_LPDIV_DIV1       (MCLK_LPDIV_LPDIV_DIV1_Val     << MCLK_LPDIV_LPDIV_Pos)
+#define MCLK_LPDIV_LPDIV_DIV2       (MCLK_LPDIV_LPDIV_DIV2_Val     << MCLK_LPDIV_LPDIV_Pos)
+#define MCLK_LPDIV_LPDIV_DIV4       (MCLK_LPDIV_LPDIV_DIV4_Val     << MCLK_LPDIV_LPDIV_Pos)
+#define MCLK_LPDIV_LPDIV_DIV8       (MCLK_LPDIV_LPDIV_DIV8_Val     << MCLK_LPDIV_LPDIV_Pos)
+#define MCLK_LPDIV_LPDIV_DIV16      (MCLK_LPDIV_LPDIV_DIV16_Val    << MCLK_LPDIV_LPDIV_Pos)
+#define MCLK_LPDIV_LPDIV_DIV32      (MCLK_LPDIV_LPDIV_DIV32_Val    << MCLK_LPDIV_LPDIV_Pos)
+#define MCLK_LPDIV_LPDIV_DIV64      (MCLK_LPDIV_LPDIV_DIV64_Val    << MCLK_LPDIV_LPDIV_Pos)
+#define MCLK_LPDIV_LPDIV_DIV128     (MCLK_LPDIV_LPDIV_DIV128_Val   << MCLK_LPDIV_LPDIV_Pos)
+#define MCLK_LPDIV_MASK             _U_(0xFF)    /**< \brief (MCLK_LPDIV) MASK Register */
+
+/* -------- MCLK_BUPDIV : (MCLK Offset: 0x06) (R/W  8) Backup Clock Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  BUPDIV:8;         /*!< bit:  0.. 7  Backup Clock Division Factor       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} MCLK_BUPDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_BUPDIV_OFFSET          0x06         /**< \brief (MCLK_BUPDIV offset) Backup Clock Division */
+#define MCLK_BUPDIV_RESETVALUE      _U_(0x01)    /**< \brief (MCLK_BUPDIV reset_value) Backup Clock Division */
+
+#define MCLK_BUPDIV_BUPDIV_Pos      0            /**< \brief (MCLK_BUPDIV) Backup Clock Division Factor */
+#define MCLK_BUPDIV_BUPDIV_Msk      (_U_(0xFF) << MCLK_BUPDIV_BUPDIV_Pos)
+#define MCLK_BUPDIV_BUPDIV(value)   (MCLK_BUPDIV_BUPDIV_Msk & ((value) << MCLK_BUPDIV_BUPDIV_Pos))
+#define   MCLK_BUPDIV_BUPDIV_DIV1_Val     _U_(0x1)   /**< \brief (MCLK_BUPDIV) Divide by 1 */
+#define   MCLK_BUPDIV_BUPDIV_DIV2_Val     _U_(0x2)   /**< \brief (MCLK_BUPDIV) Divide by 2 */
+#define   MCLK_BUPDIV_BUPDIV_DIV4_Val     _U_(0x4)   /**< \brief (MCLK_BUPDIV) Divide by 4 */
+#define   MCLK_BUPDIV_BUPDIV_DIV8_Val     _U_(0x8)   /**< \brief (MCLK_BUPDIV) Divide by 8 */
+#define   MCLK_BUPDIV_BUPDIV_DIV16_Val    _U_(0x10)   /**< \brief (MCLK_BUPDIV) Divide by 16 */
+#define   MCLK_BUPDIV_BUPDIV_DIV32_Val    _U_(0x20)   /**< \brief (MCLK_BUPDIV) Divide by 32 */
+#define   MCLK_BUPDIV_BUPDIV_DIV64_Val    _U_(0x40)   /**< \brief (MCLK_BUPDIV) Divide by 64 */
+#define   MCLK_BUPDIV_BUPDIV_DIV128_Val   _U_(0x80)   /**< \brief (MCLK_BUPDIV) Divide by 128 */
+#define MCLK_BUPDIV_BUPDIV_DIV1     (MCLK_BUPDIV_BUPDIV_DIV1_Val   << MCLK_BUPDIV_BUPDIV_Pos)
+#define MCLK_BUPDIV_BUPDIV_DIV2     (MCLK_BUPDIV_BUPDIV_DIV2_Val   << MCLK_BUPDIV_BUPDIV_Pos)
+#define MCLK_BUPDIV_BUPDIV_DIV4     (MCLK_BUPDIV_BUPDIV_DIV4_Val   << MCLK_BUPDIV_BUPDIV_Pos)
+#define MCLK_BUPDIV_BUPDIV_DIV8     (MCLK_BUPDIV_BUPDIV_DIV8_Val   << MCLK_BUPDIV_BUPDIV_Pos)
+#define MCLK_BUPDIV_BUPDIV_DIV16    (MCLK_BUPDIV_BUPDIV_DIV16_Val  << MCLK_BUPDIV_BUPDIV_Pos)
+#define MCLK_BUPDIV_BUPDIV_DIV32    (MCLK_BUPDIV_BUPDIV_DIV32_Val  << MCLK_BUPDIV_BUPDIV_Pos)
+#define MCLK_BUPDIV_BUPDIV_DIV64    (MCLK_BUPDIV_BUPDIV_DIV64_Val  << MCLK_BUPDIV_BUPDIV_Pos)
+#define MCLK_BUPDIV_BUPDIV_DIV128   (MCLK_BUPDIV_BUPDIV_DIV128_Val << MCLK_BUPDIV_BUPDIV_Pos)
+#define MCLK_BUPDIV_MASK            _U_(0xFF)    /**< \brief (MCLK_BUPDIV) MASK Register */
+
+/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t HPB0_:1;          /*!< bit:      0  HPB0 AHB Clock Mask                */
+    uint32_t HPB1_:1;          /*!< bit:      1  HPB1 AHB Clock Mask                */
+    uint32_t HPB2_:1;          /*!< bit:      2  HPB2 AHB Clock Mask                */
+    uint32_t HPB3_:1;          /*!< bit:      3  HPB3 AHB Clock Mask                */
+    uint32_t HPB4_:1;          /*!< bit:      4  HPB4 AHB Clock Mask                */
+    uint32_t DSU_:1;           /*!< bit:      5  DSU AHB Clock Mask                 */
+    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint32_t NVMCTRL_:1;       /*!< bit:      8  NVMCTRL AHB Clock Mask             */
+    uint32_t HSRAM_:1;         /*!< bit:      9  HSRAM AHB Clock Mask               */
+    uint32_t LPRAM_:1;         /*!< bit:     10  LPRAM AHB Clock Mask               */
+    uint32_t DMAC_:1;          /*!< bit:     11  DMAC AHB Clock Mask                */
+    uint32_t USB_:1;           /*!< bit:     12  USB AHB Clock Mask                 */
+    uint32_t :1;               /*!< bit:     13  Reserved                           */
+    uint32_t PAC_:1;           /*!< bit:     14  PAC AHB Clock Mask                 */
+    uint32_t NVMCTRL_PICACHU_:1; /*!< bit:     15  NVMCTRL_PICACHU AHB Clock Mask     */
+    uint32_t L2HBRIDGES_H_:1;  /*!< bit:     16  L2HBRIDGES_H AHB Clock Mask        */
+    uint32_t H2LBRIDGES_H_:1;  /*!< bit:     17  H2LBRIDGES_H AHB Clock Mask        */
+    uint32_t HSRAM_AHBSETUPKEEPER_:1; /*!< bit:     18  HSRAM_AHBSETUPKEEPER AHB Clock Mask */
+    uint32_t HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_:1; /*!< bit:     19  HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE AHB Clock Mask */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MCLK_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_AHBMASK_OFFSET         0x10         /**< \brief (MCLK_AHBMASK offset) AHB Mask */
+#define MCLK_AHBMASK_RESETVALUE     _U_(0x000FFFFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */
+
+#define MCLK_AHBMASK_HPB0_Pos       0            /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB0           (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)
+#define MCLK_AHBMASK_HPB1_Pos       1            /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB1           (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)
+#define MCLK_AHBMASK_HPB2_Pos       2            /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB2           (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)
+#define MCLK_AHBMASK_HPB3_Pos       3            /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB3           (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)
+#define MCLK_AHBMASK_HPB4_Pos       4            /**< \brief (MCLK_AHBMASK) HPB4 AHB Clock Mask */
+#define MCLK_AHBMASK_HPB4           (_U_(0x1) << MCLK_AHBMASK_HPB4_Pos)
+#define MCLK_AHBMASK_DSU_Pos        5            /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */
+#define MCLK_AHBMASK_DSU            (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)
+#define MCLK_AHBMASK_NVMCTRL_Pos    8            /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */
+#define MCLK_AHBMASK_NVMCTRL        (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)
+#define MCLK_AHBMASK_HSRAM_Pos      9            /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */
+#define MCLK_AHBMASK_HSRAM          (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)
+#define MCLK_AHBMASK_LPRAM_Pos      10           /**< \brief (MCLK_AHBMASK) LPRAM AHB Clock Mask */
+#define MCLK_AHBMASK_LPRAM          (_U_(0x1) << MCLK_AHBMASK_LPRAM_Pos)
+#define MCLK_AHBMASK_DMAC_Pos       11           /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */
+#define MCLK_AHBMASK_DMAC           (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)
+#define MCLK_AHBMASK_USB_Pos        12           /**< \brief (MCLK_AHBMASK) USB AHB Clock Mask */
+#define MCLK_AHBMASK_USB            (_U_(0x1) << MCLK_AHBMASK_USB_Pos)
+#define MCLK_AHBMASK_PAC_Pos        14           /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */
+#define MCLK_AHBMASK_PAC            (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
+#define MCLK_AHBMASK_NVMCTRL_PICACHU_Pos 15           /**< \brief (MCLK_AHBMASK) NVMCTRL_PICACHU AHB Clock Mask */
+#define MCLK_AHBMASK_NVMCTRL_PICACHU (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos)
+#define MCLK_AHBMASK_L2HBRIDGES_H_Pos 16           /**< \brief (MCLK_AHBMASK) L2HBRIDGES_H AHB Clock Mask */
+#define MCLK_AHBMASK_L2HBRIDGES_H   (_U_(0x1) << MCLK_AHBMASK_L2HBRIDGES_H_Pos)
+#define MCLK_AHBMASK_H2LBRIDGES_H_Pos 17           /**< \brief (MCLK_AHBMASK) H2LBRIDGES_H AHB Clock Mask */
+#define MCLK_AHBMASK_H2LBRIDGES_H   (_U_(0x1) << MCLK_AHBMASK_H2LBRIDGES_H_Pos)
+#define MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER_Pos 18           /**< \brief (MCLK_AHBMASK) HSRAM_AHBSETUPKEEPER AHB Clock Mask */
+#define MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER (_U_(0x1) << MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER_Pos)
+#define MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_Pos 19           /**< \brief (MCLK_AHBMASK) HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE AHB Clock Mask */
+#define MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE (_U_(0x1) << MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_Pos)
+#define MCLK_AHBMASK_MASK           _U_(0x000FDF3F) /**< \brief (MCLK_AHBMASK) MASK Register */
+
+/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PM_:1;            /*!< bit:      0  PM APB Clock Enable                */
+    uint32_t MCLK_:1;          /*!< bit:      1  MCLK APB Clock Enable              */
+    uint32_t RSTC_:1;          /*!< bit:      2  RSTC APB Clock Enable              */
+    uint32_t OSCCTRL_:1;       /*!< bit:      3  OSCCTRL APB Clock Enable           */
+    uint32_t OSC32KCTRL_:1;    /*!< bit:      4  OSC32KCTRL APB Clock Enable        */
+    uint32_t SUPC_:1;          /*!< bit:      5  SUPC APB Clock Enable              */
+    uint32_t GCLK_:1;          /*!< bit:      6  GCLK APB Clock Enable              */
+    uint32_t WDT_:1;           /*!< bit:      7  WDT APB Clock Enable               */
+    uint32_t RTC_:1;           /*!< bit:      8  RTC APB Clock Enable               */
+    uint32_t EIC_:1;           /*!< bit:      9  EIC APB Clock Enable               */
+    uint32_t PORT_:1;          /*!< bit:     10  PORT APB Clock Enable              */
+    uint32_t TAL_:1;           /*!< bit:     11  TAL APB Clock Enable               */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MCLK_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBAMASK_OFFSET        0x14         /**< \brief (MCLK_APBAMASK offset) APBA Mask */
+#define MCLK_APBAMASK_RESETVALUE    _U_(0x00001FFF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */
+
+#define MCLK_APBAMASK_PM_Pos        0            /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */
+#define MCLK_APBAMASK_PM            (_U_(0x1) << MCLK_APBAMASK_PM_Pos)
+#define MCLK_APBAMASK_MCLK_Pos      1            /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */
+#define MCLK_APBAMASK_MCLK          (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)
+#define MCLK_APBAMASK_RSTC_Pos      2            /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */
+#define MCLK_APBAMASK_RSTC          (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)
+#define MCLK_APBAMASK_OSCCTRL_Pos   3            /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */
+#define MCLK_APBAMASK_OSCCTRL       (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)
+#define MCLK_APBAMASK_OSC32KCTRL_Pos 4            /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */
+#define MCLK_APBAMASK_OSC32KCTRL    (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)
+#define MCLK_APBAMASK_SUPC_Pos      5            /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */
+#define MCLK_APBAMASK_SUPC          (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)
+#define MCLK_APBAMASK_GCLK_Pos      6            /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */
+#define MCLK_APBAMASK_GCLK          (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)
+#define MCLK_APBAMASK_WDT_Pos       7            /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */
+#define MCLK_APBAMASK_WDT           (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)
+#define MCLK_APBAMASK_RTC_Pos       8            /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */
+#define MCLK_APBAMASK_RTC           (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)
+#define MCLK_APBAMASK_EIC_Pos       9            /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */
+#define MCLK_APBAMASK_EIC           (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)
+#define MCLK_APBAMASK_PORT_Pos      10           /**< \brief (MCLK_APBAMASK) PORT APB Clock Enable */
+#define MCLK_APBAMASK_PORT          (_U_(0x1) << MCLK_APBAMASK_PORT_Pos)
+#define MCLK_APBAMASK_TAL_Pos       11           /**< \brief (MCLK_APBAMASK) TAL APB Clock Enable */
+#define MCLK_APBAMASK_TAL           (_U_(0x1) << MCLK_APBAMASK_TAL_Pos)
+#define MCLK_APBAMASK_MASK          _U_(0x00000FFF) /**< \brief (MCLK_APBAMASK) MASK Register */
+
+/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t USB_:1;           /*!< bit:      0  USB APB Clock Enable               */
+    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Clock Enable               */
+    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Clock Enable           */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MCLK_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBBMASK_OFFSET        0x18         /**< \brief (MCLK_APBBMASK offset) APBB Mask */
+#define MCLK_APBBMASK_RESETVALUE    _U_(0x00000017) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */
+
+#define MCLK_APBBMASK_USB_Pos       0            /**< \brief (MCLK_APBBMASK) USB APB Clock Enable */
+#define MCLK_APBBMASK_USB           (_U_(0x1) << MCLK_APBBMASK_USB_Pos)
+#define MCLK_APBBMASK_DSU_Pos       1            /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */
+#define MCLK_APBBMASK_DSU           (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)
+#define MCLK_APBBMASK_NVMCTRL_Pos   2            /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */
+#define MCLK_APBBMASK_NVMCTRL       (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)
+#define MCLK_APBBMASK_MASK          _U_(0x00000007) /**< \brief (MCLK_APBBMASK) MASK Register */
+
+/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SERCOM0_:1;       /*!< bit:      0  SERCOM0 APB Clock Enable           */
+    uint32_t SERCOM1_:1;       /*!< bit:      1  SERCOM1 APB Clock Enable           */
+    uint32_t SERCOM2_:1;       /*!< bit:      2  SERCOM2 APB Clock Enable           */
+    uint32_t SERCOM3_:1;       /*!< bit:      3  SERCOM3 APB Clock Enable           */
+    uint32_t SERCOM4_:1;       /*!< bit:      4  SERCOM4 APB Clock Enable           */
+    uint32_t TCC0_:1;          /*!< bit:      5  TCC0 APB Clock Enable              */
+    uint32_t TCC1_:1;          /*!< bit:      6  TCC1 APB Clock Enable              */
+    uint32_t TCC2_:1;          /*!< bit:      7  TCC2 APB Clock Enable              */
+    uint32_t TC0_:1;           /*!< bit:      8  TC0 APB Clock Enable               */
+    uint32_t TC1_:1;           /*!< bit:      9  TC1 APB Clock Enable               */
+    uint32_t TC2_:1;           /*!< bit:     10  TC2 APB Clock Enable               */
+    uint32_t TC3_:1;           /*!< bit:     11  TC3 APB Clock Enable               */
+    uint32_t DAC_:1;           /*!< bit:     12  DAC APB Clock Enable               */
+    uint32_t AES_:1;           /*!< bit:     13  AES APB Clock Enable               */
+    uint32_t TRNG_:1;          /*!< bit:     14  TRNG APB Clock Enable              */
+    uint32_t :17;              /*!< bit: 15..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MCLK_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBCMASK_OFFSET        0x1C         /**< \brief (MCLK_APBCMASK offset) APBC Mask */
+#define MCLK_APBCMASK_RESETVALUE    _U_(0x00007FFF) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */
+
+#define MCLK_APBCMASK_SERCOM0_Pos   0            /**< \brief (MCLK_APBCMASK) SERCOM0 APB Clock Enable */
+#define MCLK_APBCMASK_SERCOM0       (_U_(0x1) << MCLK_APBCMASK_SERCOM0_Pos)
+#define MCLK_APBCMASK_SERCOM1_Pos   1            /**< \brief (MCLK_APBCMASK) SERCOM1 APB Clock Enable */
+#define MCLK_APBCMASK_SERCOM1       (_U_(0x1) << MCLK_APBCMASK_SERCOM1_Pos)
+#define MCLK_APBCMASK_SERCOM2_Pos   2            /**< \brief (MCLK_APBCMASK) SERCOM2 APB Clock Enable */
+#define MCLK_APBCMASK_SERCOM2       (_U_(0x1) << MCLK_APBCMASK_SERCOM2_Pos)
+#define MCLK_APBCMASK_SERCOM3_Pos   3            /**< \brief (MCLK_APBCMASK) SERCOM3 APB Clock Enable */
+#define MCLK_APBCMASK_SERCOM3       (_U_(0x1) << MCLK_APBCMASK_SERCOM3_Pos)
+#define MCLK_APBCMASK_SERCOM4_Pos   4            /**< \brief (MCLK_APBCMASK) SERCOM4 APB Clock Enable */
+#define MCLK_APBCMASK_SERCOM4       (_U_(0x1) << MCLK_APBCMASK_SERCOM4_Pos)
+#define MCLK_APBCMASK_TCC0_Pos      5            /**< \brief (MCLK_APBCMASK) TCC0 APB Clock Enable */
+#define MCLK_APBCMASK_TCC0          (_U_(0x1) << MCLK_APBCMASK_TCC0_Pos)
+#define MCLK_APBCMASK_TCC1_Pos      6            /**< \brief (MCLK_APBCMASK) TCC1 APB Clock Enable */
+#define MCLK_APBCMASK_TCC1          (_U_(0x1) << MCLK_APBCMASK_TCC1_Pos)
+#define MCLK_APBCMASK_TCC2_Pos      7            /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */
+#define MCLK_APBCMASK_TCC2          (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
+#define MCLK_APBCMASK_TC0_Pos       8            /**< \brief (MCLK_APBCMASK) TC0 APB Clock Enable */
+#define MCLK_APBCMASK_TC0           (_U_(0x1) << MCLK_APBCMASK_TC0_Pos)
+#define MCLK_APBCMASK_TC1_Pos       9            /**< \brief (MCLK_APBCMASK) TC1 APB Clock Enable */
+#define MCLK_APBCMASK_TC1           (_U_(0x1) << MCLK_APBCMASK_TC1_Pos)
+#define MCLK_APBCMASK_TC2_Pos       10           /**< \brief (MCLK_APBCMASK) TC2 APB Clock Enable */
+#define MCLK_APBCMASK_TC2           (_U_(0x1) << MCLK_APBCMASK_TC2_Pos)
+#define MCLK_APBCMASK_TC3_Pos       11           /**< \brief (MCLK_APBCMASK) TC3 APB Clock Enable */
+#define MCLK_APBCMASK_TC3           (_U_(0x1) << MCLK_APBCMASK_TC3_Pos)
+#define MCLK_APBCMASK_DAC_Pos       12           /**< \brief (MCLK_APBCMASK) DAC APB Clock Enable */
+#define MCLK_APBCMASK_DAC           (_U_(0x1) << MCLK_APBCMASK_DAC_Pos)
+#define MCLK_APBCMASK_AES_Pos       13           /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */
+#define MCLK_APBCMASK_AES           (_U_(0x1) << MCLK_APBCMASK_AES_Pos)
+#define MCLK_APBCMASK_TRNG_Pos      14           /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */
+#define MCLK_APBCMASK_TRNG          (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)
+#define MCLK_APBCMASK_MASK          _U_(0x00007FFF) /**< \brief (MCLK_APBCMASK) MASK Register */
+
+/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVSYS_:1;         /*!< bit:      0  EVSYS APB Clock Enable             */
+    uint32_t SERCOM5_:1;       /*!< bit:      1  SERCOM5 APB Clock Enable           */
+    uint32_t TC4_:1;           /*!< bit:      2  TC4 APB Clock Enable               */
+    uint32_t ADC_:1;           /*!< bit:      3  ADC APB Clock Enable               */
+    uint32_t AC_:1;            /*!< bit:      4  AC APB Clock Enable                */
+    uint32_t PTC_:1;           /*!< bit:      5  PTC APB Clock Enable               */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CCL_:1;           /*!< bit:      7  CCL APB Clock Enable               */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MCLK_APBDMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBDMASK_OFFSET        0x20         /**< \brief (MCLK_APBDMASK offset) APBD Mask */
+#define MCLK_APBDMASK_RESETVALUE    _U_(0x000000FF) /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */
+
+#define MCLK_APBDMASK_EVSYS_Pos     0            /**< \brief (MCLK_APBDMASK) EVSYS APB Clock Enable */
+#define MCLK_APBDMASK_EVSYS         (_U_(0x1) << MCLK_APBDMASK_EVSYS_Pos)
+#define MCLK_APBDMASK_SERCOM5_Pos   1            /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM5       (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)
+#define MCLK_APBDMASK_TC4_Pos       2            /**< \brief (MCLK_APBDMASK) TC4 APB Clock Enable */
+#define MCLK_APBDMASK_TC4           (_U_(0x1) << MCLK_APBDMASK_TC4_Pos)
+#define MCLK_APBDMASK_ADC_Pos       3            /**< \brief (MCLK_APBDMASK) ADC APB Clock Enable */
+#define MCLK_APBDMASK_ADC           (_U_(0x1) << MCLK_APBDMASK_ADC_Pos)
+#define MCLK_APBDMASK_AC_Pos        4            /**< \brief (MCLK_APBDMASK) AC APB Clock Enable */
+#define MCLK_APBDMASK_AC            (_U_(0x1) << MCLK_APBDMASK_AC_Pos)
+#define MCLK_APBDMASK_PTC_Pos       5            /**< \brief (MCLK_APBDMASK) PTC APB Clock Enable */
+#define MCLK_APBDMASK_PTC           (_U_(0x1) << MCLK_APBDMASK_PTC_Pos)
+#define MCLK_APBDMASK_CCL_Pos       7            /**< \brief (MCLK_APBDMASK) CCL APB Clock Enable */
+#define MCLK_APBDMASK_CCL           (_U_(0x1) << MCLK_APBDMASK_CCL_Pos)
+#define MCLK_APBDMASK_MASK          _U_(0x000000BF) /**< \brief (MCLK_APBDMASK) MASK Register */
+
+/* -------- MCLK_APBEMASK : (MCLK Offset: 0x24) (R/W 32) APBE Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC_:1;           /*!< bit:      0  PAC APB Clock Enable               */
+    uint32_t :31;              /*!< bit:  1..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MCLK_APBEMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MCLK_APBEMASK_OFFSET        0x24         /**< \brief (MCLK_APBEMASK offset) APBE Mask */
+#define MCLK_APBEMASK_RESETVALUE    _U_(0x0000000D) /**< \brief (MCLK_APBEMASK reset_value) APBE Mask */
+
+#define MCLK_APBEMASK_PAC_Pos       0            /**< \brief (MCLK_APBEMASK) PAC APB Clock Enable */
+#define MCLK_APBEMASK_PAC           (_U_(0x1) << MCLK_APBEMASK_PAC_Pos)
+#define MCLK_APBEMASK_MASK          _U_(0x00000001) /**< \brief (MCLK_APBEMASK) MASK Register */
+
+/** \brief MCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO MCLK_CTRLA_Type           CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __IO MCLK_INTENCLR_Type        INTENCLR;    /**< \brief Offset: 0x01 (R/W  8) Interrupt Enable Clear */
+  __IO MCLK_INTENSET_Type        INTENSET;    /**< \brief Offset: 0x02 (R/W  8) Interrupt Enable Set */
+  __IO MCLK_INTFLAG_Type         INTFLAG;     /**< \brief Offset: 0x03 (R/W  8) Interrupt Flag Status and Clear */
+  __IO MCLK_CPUDIV_Type          CPUDIV;      /**< \brief Offset: 0x04 (R/W  8) CPU Clock Division */
+  __IO MCLK_LPDIV_Type           LPDIV;       /**< \brief Offset: 0x05 (R/W  8) Low-Power Clock Division */
+  __IO MCLK_BUPDIV_Type          BUPDIV;      /**< \brief Offset: 0x06 (R/W  8) Backup Clock Division */
+       RoReg8                    Reserved1[0x9];
+  __IO MCLK_AHBMASK_Type         AHBMASK;     /**< \brief Offset: 0x10 (R/W 32) AHB Mask */
+  __IO MCLK_APBAMASK_Type        APBAMASK;    /**< \brief Offset: 0x14 (R/W 32) APBA Mask */
+  __IO MCLK_APBBMASK_Type        APBBMASK;    /**< \brief Offset: 0x18 (R/W 32) APBB Mask */
+  __IO MCLK_APBCMASK_Type        APBCMASK;    /**< \brief Offset: 0x1C (R/W 32) APBC Mask */
+  __IO MCLK_APBDMASK_Type        APBDMASK;    /**< \brief Offset: 0x20 (R/W 32) APBD Mask */
+  __IO MCLK_APBEMASK_Type        APBEMASK;    /**< \brief Offset: 0x24 (R/W 32) APBE Mask */
+} Mclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_MCLK_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/mtb.h

@@ -0,0 +1,382 @@
+/**
+ * \file
+ *
+ * \brief Component description for MTB
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_MTB_COMPONENT_
+#define _SAMR34_MTB_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR MTB */
+/* ========================================================================== */
+/** \addtogroup SAMR34_MTB Cortex-M0+ Micro-Trace Buffer */
+/*@{*/
+
+#define MTB_U2002
+#define REV_MTB                     0x100
+
+/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint32_t WRAP:1;           /*!< bit:      2  Pointer Value Wraps                */
+    uint32_t POINTER:29;       /*!< bit:  3..31  Trace Packet Location Pointer      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_POSITION_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_POSITION_OFFSET         0x000        /**< \brief (MTB_POSITION offset) MTB Position */
+
+#define MTB_POSITION_WRAP_Pos       2            /**< \brief (MTB_POSITION) Pointer Value Wraps */
+#define MTB_POSITION_WRAP           (_U_(0x1) << MTB_POSITION_WRAP_Pos)
+#define MTB_POSITION_POINTER_Pos    3            /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
+#define MTB_POSITION_POINTER_Msk    (_U_(0x1FFFFFFF) << MTB_POSITION_POINTER_Pos)
+#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
+#define MTB_POSITION_MASK           _U_(0xFFFFFFFC) /**< \brief (MTB_POSITION) MASK Register */
+
+/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MASK:5;           /*!< bit:  0.. 4  Maximum Value of the Trace Buffer in SRAM */
+    uint32_t TSTARTEN:1;       /*!< bit:      5  Trace Start Input Enable           */
+    uint32_t TSTOPEN:1;        /*!< bit:      6  Trace Stop Input Enable            */
+    uint32_t SFRWPRIV:1;       /*!< bit:      7  Special Function Register Write Privilege */
+    uint32_t RAMPRIV:1;        /*!< bit:      8  SRAM Privilege                     */
+    uint32_t HALTREQ:1;        /*!< bit:      9  Halt Request                       */
+    uint32_t :21;              /*!< bit: 10..30  Reserved                           */
+    uint32_t EN:1;             /*!< bit:     31  Main Trace Enable                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_MASTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_MASTER_OFFSET           0x004        /**< \brief (MTB_MASTER offset) MTB Master */
+#define MTB_MASTER_RESETVALUE       _U_(0x00000000) /**< \brief (MTB_MASTER reset_value) MTB Master */
+
+#define MTB_MASTER_MASK_Pos         0            /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
+#define MTB_MASTER_MASK_Msk         (_U_(0x1F) << MTB_MASTER_MASK_Pos)
+#define MTB_MASTER_MASK(value)      (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
+#define MTB_MASTER_TSTARTEN_Pos     5            /**< \brief (MTB_MASTER) Trace Start Input Enable */
+#define MTB_MASTER_TSTARTEN         (_U_(0x1) << MTB_MASTER_TSTARTEN_Pos)
+#define MTB_MASTER_TSTOPEN_Pos      6            /**< \brief (MTB_MASTER) Trace Stop Input Enable */
+#define MTB_MASTER_TSTOPEN          (_U_(0x1) << MTB_MASTER_TSTOPEN_Pos)
+#define MTB_MASTER_SFRWPRIV_Pos     7            /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
+#define MTB_MASTER_SFRWPRIV         (_U_(0x1) << MTB_MASTER_SFRWPRIV_Pos)
+#define MTB_MASTER_RAMPRIV_Pos      8            /**< \brief (MTB_MASTER) SRAM Privilege */
+#define MTB_MASTER_RAMPRIV          (_U_(0x1) << MTB_MASTER_RAMPRIV_Pos)
+#define MTB_MASTER_HALTREQ_Pos      9            /**< \brief (MTB_MASTER) Halt Request */
+#define MTB_MASTER_HALTREQ          (_U_(0x1) << MTB_MASTER_HALTREQ_Pos)
+#define MTB_MASTER_EN_Pos           31           /**< \brief (MTB_MASTER) Main Trace Enable */
+#define MTB_MASTER_EN               (_U_(0x1) << MTB_MASTER_EN_Pos)
+#define MTB_MASTER_MASK_            _U_(0x800003FF) /**< \brief (MTB_MASTER) MASK Register */
+
+/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t AUTOSTOP:1;       /*!< bit:      0  Auto Stop Tracing                  */
+    uint32_t AUTOHALT:1;       /*!< bit:      1  Auto Halt Request                  */
+    uint32_t :1;               /*!< bit:      2  Reserved                           */
+    uint32_t WATERMARK:29;     /*!< bit:  3..31  Watermark value                    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_FLOW_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_FLOW_OFFSET             0x008        /**< \brief (MTB_FLOW offset) MTB Flow */
+#define MTB_FLOW_RESETVALUE         _U_(0x00000000) /**< \brief (MTB_FLOW reset_value) MTB Flow */
+
+#define MTB_FLOW_AUTOSTOP_Pos       0            /**< \brief (MTB_FLOW) Auto Stop Tracing */
+#define MTB_FLOW_AUTOSTOP           (_U_(0x1) << MTB_FLOW_AUTOSTOP_Pos)
+#define MTB_FLOW_AUTOHALT_Pos       1            /**< \brief (MTB_FLOW) Auto Halt Request */
+#define MTB_FLOW_AUTOHALT           (_U_(0x1) << MTB_FLOW_AUTOHALT_Pos)
+#define MTB_FLOW_WATERMARK_Pos      3            /**< \brief (MTB_FLOW) Watermark value */
+#define MTB_FLOW_WATERMARK_Msk      (_U_(0x1FFFFFFF) << MTB_FLOW_WATERMARK_Pos)
+#define MTB_FLOW_WATERMARK(value)   (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
+#define MTB_FLOW_MASK               _U_(0xFFFFFFFB) /**< \brief (MTB_FLOW) MASK Register */
+
+/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/  32) MTB Base -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_BASE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_BASE_OFFSET             0x00C        /**< \brief (MTB_BASE offset) MTB Base */
+#define MTB_BASE_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_BASE) MASK Register */
+
+/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_ITCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_ITCTRL_OFFSET           0xF00        /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
+#define MTB_ITCTRL_MASK             _U_(0xFFFFFFFF) /**< \brief (MTB_ITCTRL) MASK Register */
+
+/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CLAIMSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMSET_OFFSET         0xFA0        /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
+#define MTB_CLAIMSET_MASK           _U_(0xFFFFFFFF) /**< \brief (MTB_CLAIMSET) MASK Register */
+
+/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CLAIMCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMCLR_OFFSET         0xFA4        /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
+#define MTB_CLAIMCLR_MASK           _U_(0xFFFFFFFF) /**< \brief (MTB_CLAIMCLR) MASK Register */
+
+/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_LOCKACCESS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKACCESS_OFFSET       0xFB0        /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
+#define MTB_LOCKACCESS_MASK         _U_(0xFFFFFFFF) /**< \brief (MTB_LOCKACCESS) MASK Register */
+
+/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/  32) MTB Lock Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_LOCKSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKSTATUS_OFFSET       0xFB4        /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
+#define MTB_LOCKSTATUS_MASK         _U_(0xFFFFFFFF) /**< \brief (MTB_LOCKSTATUS) MASK Register */
+
+/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/  32) MTB Authentication Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_AUTHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_AUTHSTATUS_OFFSET       0xFB8        /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
+#define MTB_AUTHSTATUS_MASK         _U_(0xFFFFFFFF) /**< \brief (MTB_AUTHSTATUS) MASK Register */
+
+/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/  32) MTB Device Architecture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVARCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVARCH_OFFSET          0xFBC        /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
+#define MTB_DEVARCH_MASK            _U_(0xFFFFFFFF) /**< \brief (MTB_DEVARCH) MASK Register */
+
+/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/  32) MTB Device Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVID_OFFSET            0xFC8        /**< \brief (MTB_DEVID offset) MTB Device Configuration */
+#define MTB_DEVID_MASK              _U_(0xFFFFFFFF) /**< \brief (MTB_DEVID) MASK Register */
+
+/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/  32) MTB Device Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_DEVTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVTYPE_OFFSET          0xFCC        /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
+#define MTB_DEVTYPE_MASK            _U_(0xFFFFFFFF) /**< \brief (MTB_DEVTYPE) MASK Register */
+
+/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/  32) Peripheral Identification 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID4_OFFSET             0xFD0        /**< \brief (MTB_PID4 offset) Peripheral Identification 4 */
+#define MTB_PID4_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_PID4) MASK Register */
+
+/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/  32) Peripheral Identification 5 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID5_OFFSET             0xFD4        /**< \brief (MTB_PID5 offset) Peripheral Identification 5 */
+#define MTB_PID5_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_PID5) MASK Register */
+
+/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/  32) Peripheral Identification 6 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID6_OFFSET             0xFD8        /**< \brief (MTB_PID6 offset) Peripheral Identification 6 */
+#define MTB_PID6_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_PID6) MASK Register */
+
+/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/  32) Peripheral Identification 7 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID7_OFFSET             0xFDC        /**< \brief (MTB_PID7 offset) Peripheral Identification 7 */
+#define MTB_PID7_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_PID7) MASK Register */
+
+/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/  32) Peripheral Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID0_OFFSET             0xFE0        /**< \brief (MTB_PID0 offset) Peripheral Identification 0 */
+#define MTB_PID0_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_PID0) MASK Register */
+
+/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/  32) Peripheral Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID1_OFFSET             0xFE4        /**< \brief (MTB_PID1 offset) Peripheral Identification 1 */
+#define MTB_PID1_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_PID1) MASK Register */
+
+/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/  32) Peripheral Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID2_OFFSET             0xFE8        /**< \brief (MTB_PID2 offset) Peripheral Identification 2 */
+#define MTB_PID2_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_PID2) MASK Register */
+
+/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/  32) Peripheral Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID3_OFFSET             0xFEC        /**< \brief (MTB_PID3 offset) Peripheral Identification 3 */
+#define MTB_PID3_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_PID3) MASK Register */
+
+/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/  32) Component Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID0_OFFSET             0xFF0        /**< \brief (MTB_CID0 offset) Component Identification 0 */
+#define MTB_CID0_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_CID0) MASK Register */
+
+/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/  32) Component Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID1_OFFSET             0xFF4        /**< \brief (MTB_CID1 offset) Component Identification 1 */
+#define MTB_CID1_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_CID1) MASK Register */
+
+/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/  32) Component Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID2_OFFSET             0xFF8        /**< \brief (MTB_CID2 offset) Component Identification 2 */
+#define MTB_CID2_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_CID2) MASK Register */
+
+/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/  32) Component Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  uint32_t reg;                /*!< Type      used for register access              */
+} MTB_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID3_OFFSET             0xFFC        /**< \brief (MTB_CID3 offset) Component Identification 3 */
+#define MTB_CID3_MASK               _U_(0xFFFFFFFF) /**< \brief (MTB_CID3) MASK Register */
+
+/** \brief MTB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO MTB_POSITION_Type         POSITION;    /**< \brief Offset: 0x000 (R/W 32) MTB Position */
+  __IO MTB_MASTER_Type           MASTER;      /**< \brief Offset: 0x004 (R/W 32) MTB Master */
+  __IO MTB_FLOW_Type             FLOW;        /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
+  __I  MTB_BASE_Type             BASE;        /**< \brief Offset: 0x00C (R/  32) MTB Base */
+       RoReg8                    Reserved1[0xEF0];
+  __IO MTB_ITCTRL_Type           ITCTRL;      /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
+       RoReg8                    Reserved2[0x9C];
+  __IO MTB_CLAIMSET_Type         CLAIMSET;    /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
+  __IO MTB_CLAIMCLR_Type         CLAIMCLR;    /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
+       RoReg8                    Reserved3[0x8];
+  __IO MTB_LOCKACCESS_Type       LOCKACCESS;  /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
+  __I  MTB_LOCKSTATUS_Type       LOCKSTATUS;  /**< \brief Offset: 0xFB4 (R/  32) MTB Lock Status */
+  __I  MTB_AUTHSTATUS_Type       AUTHSTATUS;  /**< \brief Offset: 0xFB8 (R/  32) MTB Authentication Status */
+  __I  MTB_DEVARCH_Type          DEVARCH;     /**< \brief Offset: 0xFBC (R/  32) MTB Device Architecture */
+       RoReg8                    Reserved4[0x8];
+  __I  MTB_DEVID_Type            DEVID;       /**< \brief Offset: 0xFC8 (R/  32) MTB Device Configuration */
+  __I  MTB_DEVTYPE_Type          DEVTYPE;     /**< \brief Offset: 0xFCC (R/  32) MTB Device Type */
+  __I  MTB_PID4_Type             PID4;        /**< \brief Offset: 0xFD0 (R/  32) Peripheral Identification 4 */
+  __I  MTB_PID5_Type             PID5;        /**< \brief Offset: 0xFD4 (R/  32) Peripheral Identification 5 */
+  __I  MTB_PID6_Type             PID6;        /**< \brief Offset: 0xFD8 (R/  32) Peripheral Identification 6 */
+  __I  MTB_PID7_Type             PID7;        /**< \brief Offset: 0xFDC (R/  32) Peripheral Identification 7 */
+  __I  MTB_PID0_Type             PID0;        /**< \brief Offset: 0xFE0 (R/  32) Peripheral Identification 0 */
+  __I  MTB_PID1_Type             PID1;        /**< \brief Offset: 0xFE4 (R/  32) Peripheral Identification 1 */
+  __I  MTB_PID2_Type             PID2;        /**< \brief Offset: 0xFE8 (R/  32) Peripheral Identification 2 */
+  __I  MTB_PID3_Type             PID3;        /**< \brief Offset: 0xFEC (R/  32) Peripheral Identification 3 */
+  __I  MTB_CID0_Type             CID0;        /**< \brief Offset: 0xFF0 (R/  32) Component Identification 0 */
+  __I  MTB_CID1_Type             CID1;        /**< \brief Offset: 0xFF4 (R/  32) Component Identification 1 */
+  __I  MTB_CID2_Type             CID2;        /**< \brief Offset: 0xFF8 (R/  32) Component Identification 2 */
+  __I  MTB_CID3_Type             CID3;        /**< \brief Offset: 0xFFC (R/  32) Component Identification 3 */
+} Mtb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_MTB_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/nvmctrl.h

@@ -0,0 +1,549 @@
+/**
+ * \file
+ *
+ * \brief Component description for NVMCTRL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_NVMCTRL_COMPONENT_
+#define _SAMR34_NVMCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR NVMCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMR34_NVMCTRL Non-Volatile Memory Controller */
+/*@{*/
+
+#define NVMCTRL_U2207
+#define REV_NVMCTRL                 0x302
+
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t CMD:7;            /*!< bit:  0.. 6  Command                            */
+    uint16_t :1;               /*!< bit:      7  Reserved                           */
+    uint16_t CMDEX:8;          /*!< bit:  8..15  Command Execution                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLA_OFFSET        0x00         /**< \brief (NVMCTRL_CTRLA offset) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE    _U_(0x0000)  /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+
+#define NVMCTRL_CTRLA_CMD_Pos       0            /**< \brief (NVMCTRL_CTRLA) Command */
+#define NVMCTRL_CTRLA_CMD_Msk       (_U_(0x7F) << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD(value)    (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
+#define   NVMCTRL_CTRLA_CMD_ER_Val        _U_(0x2)   /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_WP_Val        _U_(0x4)   /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_EAR_Val       _U_(0x5)   /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_WAP_Val       _U_(0x6)   /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define   NVMCTRL_CTRLA_CMD_SF_Val        _U_(0xA)   /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
+#define   NVMCTRL_CTRLA_CMD_WL_Val        _U_(0xF)   /**< \brief (NVMCTRL_CTRLA) Write lockbits */
+#define   NVMCTRL_CTRLA_CMD_RWWEEER_Val   _U_(0x1A)   /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_RWWEEWP_Val   _U_(0x1C)   /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_LR_Val        _U_(0x40)   /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_UR_Val        _U_(0x41)   /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define   NVMCTRL_CTRLA_CMD_SPRM_Val      _U_(0x42)   /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_CPRM_Val      _U_(0x43)   /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
+#define   NVMCTRL_CTRLA_CMD_PBC_Val       _U_(0x44)   /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
+#define   NVMCTRL_CTRLA_CMD_SSB_Val       _U_(0x45)   /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
+#define   NVMCTRL_CTRLA_CMD_INVALL_Val    _U_(0x46)   /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */
+#define NVMCTRL_CTRLA_CMD_ER        (NVMCTRL_CTRLA_CMD_ER_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WP        (NVMCTRL_CTRLA_CMD_WP_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_EAR       (NVMCTRL_CTRLA_CMD_EAR_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WAP       (NVMCTRL_CTRLA_CMD_WAP_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SF        (NVMCTRL_CTRLA_CMD_SF_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WL        (NVMCTRL_CTRLA_CMD_WL_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_RWWEEER   (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_RWWEEWP   (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_LR        (NVMCTRL_CTRLA_CMD_LR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_UR        (NVMCTRL_CTRLA_CMD_UR_Val      << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SPRM      (NVMCTRL_CTRLA_CMD_SPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_CPRM      (NVMCTRL_CTRLA_CMD_CPRM_Val    << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_PBC       (NVMCTRL_CTRLA_CMD_PBC_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SSB       (NVMCTRL_CTRLA_CMD_SSB_Val     << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_INVALL    (NVMCTRL_CTRLA_CMD_INVALL_Val  << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMDEX_Pos     8            /**< \brief (NVMCTRL_CTRLA) Command Execution */
+#define NVMCTRL_CTRLA_CMDEX_Msk     (_U_(0xFF) << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_CMDEX(value)  (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
+#define   NVMCTRL_CTRLA_CMDEX_KEY_Val     _U_(0xA5)   /**< \brief (NVMCTRL_CTRLA) Execution Key */
+#define NVMCTRL_CTRLA_CMDEX_KEY     (NVMCTRL_CTRLA_CMDEX_KEY_Val   << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_MASK          _U_(0xFF7F)  /**< \brief (NVMCTRL_CTRLA) MASK Register */
+
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t RWS:4;            /*!< bit:  1.. 4  NVM Read Wait States               */
+    uint32_t :2;               /*!< bit:  5.. 6  Reserved                           */
+    uint32_t MANW:1;           /*!< bit:      7  Manual Write                       */
+    uint32_t SLEEPPRM:2;       /*!< bit:  8.. 9  Power Reduction Mode during Sleep  */
+    uint32_t :1;               /*!< bit:     10  Reserved                           */
+    uint32_t FWUP:1;           /*!< bit:     11  fast wake-up                       */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t READMODE:2;       /*!< bit: 16..17  NVMCTRL Read Mode                  */
+    uint32_t CACHEDIS:1;       /*!< bit:     18  Cache Disable                      */
+    uint32_t :13;              /*!< bit: 19..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLB_OFFSET        0x04         /**< \brief (NVMCTRL_CTRLB offset) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE    _U_(0x00000080) /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+
+#define NVMCTRL_CTRLB_RWS_Pos       1            /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
+#define NVMCTRL_CTRLB_RWS_Msk       (_U_(0xF) << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS(value)    (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
+#define   NVMCTRL_CTRLB_RWS_SINGLE_Val    _U_(0x0)   /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_HALF_Val      _U_(0x1)   /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
+#define   NVMCTRL_CTRLB_RWS_DUAL_Val      _U_(0x2)   /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_SINGLE    (NVMCTRL_CTRLB_RWS_SINGLE_Val  << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_HALF      (NVMCTRL_CTRLB_RWS_HALF_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_DUAL      (NVMCTRL_CTRLB_RWS_DUAL_Val    << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_MANW_Pos      7            /**< \brief (NVMCTRL_CTRLB) Manual Write */
+#define NVMCTRL_CTRLB_MANW          (_U_(0x1) << NVMCTRL_CTRLB_MANW_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_Pos  8            /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLB_SLEEPPRM_Msk  (_U_(0x3) << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val _U_(0x0)   /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val _U_(0x1)   /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
+#define   NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val _U_(0x3)   /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_FWUP_Pos      11           /**< \brief (NVMCTRL_CTRLB) fast wake-up */
+#define NVMCTRL_CTRLB_FWUP          (_U_(0x1) << NVMCTRL_CTRLB_FWUP_Pos)
+#define NVMCTRL_CTRLB_READMODE_Pos  16           /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
+#define NVMCTRL_CTRLB_READMODE_Msk  (_U_(0x3) << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
+#define   NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val _U_(0x0)   /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
+#define   NVMCTRL_CTRLB_READMODE_LOW_POWER_Val _U_(0x1)   /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
+#define   NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val _U_(0x2)   /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_CACHEDIS_Pos  18           /**< \brief (NVMCTRL_CTRLB) Cache Disable */
+#define NVMCTRL_CTRLB_CACHEDIS      (_U_(0x1) << NVMCTRL_CTRLB_CACHEDIS_Pos)
+#define NVMCTRL_CTRLB_MASK          _U_(0x00070B9E) /**< \brief (NVMCTRL_CTRLB) MASK Register */
+
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t NVMP:16;          /*!< bit:  0..15  NVM Pages                          */
+    uint32_t PSZ:3;            /*!< bit: 16..18  Page Size                          */
+    uint32_t :1;               /*!< bit:     19  Reserved                           */
+    uint32_t RWWEEP:12;        /*!< bit: 20..31  RWW EEPROM Pages                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_PARAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PARAM_OFFSET        0x08         /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE    _U_(0x00000000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+
+#define NVMCTRL_PARAM_NVMP_Pos      0            /**< \brief (NVMCTRL_PARAM) NVM Pages */
+#define NVMCTRL_PARAM_NVMP_Msk      (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP(value)   (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
+#define NVMCTRL_PARAM_PSZ_Pos       16           /**< \brief (NVMCTRL_PARAM) Page Size */
+#define NVMCTRL_PARAM_PSZ_Msk       (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ(value)    (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
+#define   NVMCTRL_PARAM_PSZ_8_Val         _U_(0x0)   /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define   NVMCTRL_PARAM_PSZ_16_Val        _U_(0x1)   /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define   NVMCTRL_PARAM_PSZ_32_Val        _U_(0x2)   /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define   NVMCTRL_PARAM_PSZ_64_Val        _U_(0x3)   /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define   NVMCTRL_PARAM_PSZ_128_Val       _U_(0x4)   /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define   NVMCTRL_PARAM_PSZ_256_Val       _U_(0x5)   /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define   NVMCTRL_PARAM_PSZ_512_Val       _U_(0x6)   /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define   NVMCTRL_PARAM_PSZ_1024_Val      _U_(0x7)   /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define NVMCTRL_PARAM_PSZ_8         (NVMCTRL_PARAM_PSZ_8_Val       << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_16        (NVMCTRL_PARAM_PSZ_16_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_32        (NVMCTRL_PARAM_PSZ_32_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_64        (NVMCTRL_PARAM_PSZ_64_Val      << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_128       (NVMCTRL_PARAM_PSZ_128_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_256       (NVMCTRL_PARAM_PSZ_256_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_512       (NVMCTRL_PARAM_PSZ_512_Val     << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_1024      (NVMCTRL_PARAM_PSZ_1024_Val    << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_RWWEEP_Pos    20           /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */
+#define NVMCTRL_PARAM_RWWEEP_Msk    (_U_(0xFFF) << NVMCTRL_PARAM_RWWEEP_Pos)
+#define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))
+#define NVMCTRL_PARAM_MASK          _U_(0xFFF7FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */
+
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENCLR_OFFSET     0x0C         /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE _U_(0x00)    /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define NVMCTRL_INTENCLR_READY_Pos  0            /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENCLR_READY      (_U_(0x1) << NVMCTRL_INTENCLR_READY_Pos)
+#define NVMCTRL_INTENCLR_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
+#define NVMCTRL_INTENCLR_ERROR      (_U_(0x1) << NVMCTRL_INTENCLR_ERROR_Pos)
+#define NVMCTRL_INTENCLR_MASK       _U_(0x03)    /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  READY:1;          /*!< bit:      0  NVM Ready Interrupt Enable         */
+    uint8_t  ERROR:1;          /*!< bit:      1  Error Interrupt Enable             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENSET_OFFSET     0x10         /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE _U_(0x00)    /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define NVMCTRL_INTENSET_READY_Pos  0            /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENSET_READY      (_U_(0x1) << NVMCTRL_INTENSET_READY_Pos)
+#define NVMCTRL_INTENSET_ERROR_Pos  1            /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ERROR      (_U_(0x1) << NVMCTRL_INTENSET_ERROR_Pos)
+#define NVMCTRL_INTENSET_MASK       _U_(0x03)    /**< \brief (NVMCTRL_INTENSET) MASK Register */
+
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  READY:1;          /*!< bit:      0  NVM Ready                          */
+    __I uint8_t  ERROR:1;          /*!< bit:      1  Error                              */
+    __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} NVMCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTFLAG_OFFSET      0x14         /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE  _U_(0x00)    /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define NVMCTRL_INTFLAG_READY_Pos   0            /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
+#define NVMCTRL_INTFLAG_READY       (_U_(0x1) << NVMCTRL_INTFLAG_READY_Pos)
+#define NVMCTRL_INTFLAG_ERROR_Pos   1            /**< \brief (NVMCTRL_INTFLAG) Error */
+#define NVMCTRL_INTFLAG_ERROR       (_U_(0x1) << NVMCTRL_INTFLAG_ERROR_Pos)
+#define NVMCTRL_INTFLAG_MASK        _U_(0x03)    /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PRM:1;            /*!< bit:      0  Power Reduction Mode               */
+    uint16_t LOAD:1;           /*!< bit:      1  NVM Page Buffer Active Loading     */
+    uint16_t PROGE:1;          /*!< bit:      2  Programming Error Status           */
+    uint16_t LOCKE:1;          /*!< bit:      3  Lock Error Status                  */
+    uint16_t NVME:1;           /*!< bit:      4  NVM Error                          */
+    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint16_t SB:1;             /*!< bit:      8  Security Bit Status                */
+    uint16_t :7;               /*!< bit:  9..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_STATUS_OFFSET       0x18         /**< \brief (NVMCTRL_STATUS offset) Status */
+#define NVMCTRL_STATUS_RESETVALUE   _U_(0x0000)  /**< \brief (NVMCTRL_STATUS reset_value) Status */
+
+#define NVMCTRL_STATUS_PRM_Pos      0            /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
+#define NVMCTRL_STATUS_PRM          (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_LOAD_Pos     1            /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_LOAD         (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_PROGE_Pos    2            /**< \brief (NVMCTRL_STATUS) Programming Error Status */
+#define NVMCTRL_STATUS_PROGE        (_U_(0x1) << NVMCTRL_STATUS_PROGE_Pos)
+#define NVMCTRL_STATUS_LOCKE_Pos    3            /**< \brief (NVMCTRL_STATUS) Lock Error Status */
+#define NVMCTRL_STATUS_LOCKE        (_U_(0x1) << NVMCTRL_STATUS_LOCKE_Pos)
+#define NVMCTRL_STATUS_NVME_Pos     4            /**< \brief (NVMCTRL_STATUS) NVM Error */
+#define NVMCTRL_STATUS_NVME         (_U_(0x1) << NVMCTRL_STATUS_NVME_Pos)
+#define NVMCTRL_STATUS_SB_Pos       8            /**< \brief (NVMCTRL_STATUS) Security Bit Status */
+#define NVMCTRL_STATUS_SB           (_U_(0x1) << NVMCTRL_STATUS_SB_Pos)
+#define NVMCTRL_STATUS_MASK         _U_(0x011F)  /**< \brief (NVMCTRL_STATUS) MASK Register */
+
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t ADDR:22;          /*!< bit:  0..21  NVM Address                        */
+    uint32_t :10;              /*!< bit: 22..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ADDR_OFFSET         0x1C         /**< \brief (NVMCTRL_ADDR offset) Address */
+#define NVMCTRL_ADDR_RESETVALUE     _U_(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */
+
+#define NVMCTRL_ADDR_ADDR_Pos       0            /**< \brief (NVMCTRL_ADDR) NVM Address */
+#define NVMCTRL_ADDR_ADDR_Msk       (_U_(0x3FFFFF) << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR(value)    (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
+#define NVMCTRL_ADDR_MASK           _U_(0x003FFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */
+
+/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t LOCK:16;          /*!< bit:  0..15  Region Lock Bits                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} NVMCTRL_LOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_LOCK_OFFSET         0x20         /**< \brief (NVMCTRL_LOCK offset) Lock Section */
+
+#define NVMCTRL_LOCK_LOCK_Pos       0            /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
+#define NVMCTRL_LOCK_LOCK_Msk       (_U_(0xFFFF) << NVMCTRL_LOCK_LOCK_Pos)
+#define NVMCTRL_LOCK_LOCK(value)    (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
+#define NVMCTRL_LOCK_MASK           _U_(0xFFFF)  /**< \brief (NVMCTRL_LOCK) MASK Register */
+
+/** \brief NVMCTRL APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO NVMCTRL_CTRLA_Type        CTRLA;       /**< \brief Offset: 0x00 (R/W 16) Control A */
+       RoReg8                    Reserved1[0x2];
+  __IO NVMCTRL_CTRLB_Type        CTRLB;       /**< \brief Offset: 0x04 (R/W 32) Control B */
+  __IO NVMCTRL_PARAM_Type        PARAM;       /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+  __IO NVMCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x0C (R/W  8) Interrupt Enable Clear */
+       RoReg8                    Reserved2[0x3];
+  __IO NVMCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x10 (R/W  8) Interrupt Enable Set */
+       RoReg8                    Reserved3[0x3];
+  __IO NVMCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x14 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved4[0x3];
+  __IO NVMCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x18 (R/W 16) Status */
+       RoReg8                    Reserved5[0x2];
+  __IO NVMCTRL_ADDR_Type         ADDR;        /**< \brief Offset: 0x1C (R/W 32) Address */
+  __IO NVMCTRL_LOCK_Type         LOCK;        /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+} Nvmctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#ifdef __GNUC__
+ #define SECTION_NVMCTRL_CAL          __attribute__ ((section(".flash")))
+#elif defined(__ICCARM__)
+ #define SECTION_NVMCTRL_CAL          @".flash"
+#endif
+
+#ifdef __GNUC__
+ #define SECTION_NVMCTRL_LOCKBIT      __attribute__ ((section(".flash")))
+#elif defined(__ICCARM__)
+ #define SECTION_NVMCTRL_LOCKBIT      @".flash"
+#endif
+
+#ifdef __GNUC__
+ #define SECTION_NVMCTRL_OTP1         __attribute__ ((section(".flash")))
+#elif defined(__ICCARM__)
+ #define SECTION_NVMCTRL_OTP1         @".flash"
+#endif
+
+#ifdef __GNUC__
+ #define SECTION_NVMCTRL_OTP2         __attribute__ ((section(".flash")))
+#elif defined(__ICCARM__)
+ #define SECTION_NVMCTRL_OTP2         @".flash"
+#endif
+
+#ifdef __GNUC__
+ #define SECTION_NVMCTRL_OTP3         __attribute__ ((section(".flash")))
+#elif defined(__ICCARM__)
+ #define SECTION_NVMCTRL_OTP3         @".flash"
+#endif
+
+#ifdef __GNUC__
+ #define SECTION_NVMCTRL_OTP4         __attribute__ ((section(".flash")))
+#elif defined(__ICCARM__)
+ #define SECTION_NVMCTRL_OTP4         @".flash"
+#endif
+
+#ifdef __GNUC__
+ #define SECTION_NVMCTRL_OTP5         __attribute__ ((section(".flash")))
+#elif defined(__ICCARM__)
+ #define SECTION_NVMCTRL_OTP5         @".flash"
+#endif
+
+#ifdef __GNUC__
+ #define SECTION_NVMCTRL_TEMP_LOG     __attribute__ ((section(".flash")))
+#elif defined(__ICCARM__)
+ #define SECTION_NVMCTRL_TEMP_LOG     @".flash"
+#endif
+
+#ifdef __GNUC__
+ #define SECTION_NVMCTRL_USER         __attribute__ ((section(".flash")))
+#elif defined(__ICCARM__)
+ #define SECTION_NVMCTRL_USER         @".flash"
+#endif
+
+/*@}*/
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
+/* ************************************************************************** */
+/** \addtogroup fuses_api Peripheral Software API */
+/*@{*/
+
+
+#define ADC_FUSES_BIASCOMP_ADDR     NVMCTRL_OTP5
+#define ADC_FUSES_BIASCOMP_Pos      3            /**< \brief (NVMCTRL_OTP5) ADC Comparator Scaling */
+#define ADC_FUSES_BIASCOMP_Msk      (_U_(0x7) << ADC_FUSES_BIASCOMP_Pos)
+#define ADC_FUSES_BIASCOMP(value)   (ADC_FUSES_BIASCOMP_Msk & ((value) << ADC_FUSES_BIASCOMP_Pos))
+
+#define ADC_FUSES_BIASREFBUF_ADDR   NVMCTRL_OTP5
+#define ADC_FUSES_BIASREFBUF_Pos    0            /**< \brief (NVMCTRL_OTP5) ADC Bias Reference Buffer Scaling */
+#define ADC_FUSES_BIASREFBUF_Msk    (_U_(0x7) << ADC_FUSES_BIASREFBUF_Pos)
+#define ADC_FUSES_BIASREFBUF(value) (ADC_FUSES_BIASREFBUF_Msk & ((value) << ADC_FUSES_BIASREFBUF_Pos))
+
+#define FUSES_BOD12_DIS_ADDR        NVMCTRL_USER
+#define FUSES_BOD12_DIS_Pos         23           /**< \brief (NVMCTRL_USER) BOD12 Disable */
+#define FUSES_BOD12_DIS_Msk         (_U_(0x1) << FUSES_BOD12_DIS_Pos)
+
+#define FUSES_BOD12_HYST_ADDR       (NVMCTRL_USER + 4)
+#define FUSES_BOD12_HYST_Pos        10           /**< \brief (NVMCTRL_USER) BOD12 Hysteresis */
+#define FUSES_BOD12_HYST_Msk        (_U_(0x1) << FUSES_BOD12_HYST_Pos)
+
+#define FUSES_BOD33USERLEVEL_ADDR   NVMCTRL_USER
+#define FUSES_BOD33USERLEVEL_Pos    8            /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define FUSES_BOD33USERLEVEL_Msk    (_U_(0x3F) << FUSES_BOD33USERLEVEL_Pos)
+#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
+
+#define FUSES_BOD33_ACTION_ADDR     NVMCTRL_USER
+#define FUSES_BOD33_ACTION_Pos      15           /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define FUSES_BOD33_ACTION_Msk      (_U_(0x3) << FUSES_BOD33_ACTION_Pos)
+#define FUSES_BOD33_ACTION(value)   (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
+
+#define FUSES_BOD33_DIS_ADDR        NVMCTRL_USER
+#define FUSES_BOD33_DIS_Pos         14           /**< \brief (NVMCTRL_USER) BOD33 Disable */
+#define FUSES_BOD33_DIS_Msk         (_U_(0x1) << FUSES_BOD33_DIS_Pos)
+
+#define FUSES_BOD33_HYST_ADDR       (NVMCTRL_USER + 4)
+#define FUSES_BOD33_HYST_Pos        9            /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define FUSES_BOD33_HYST_Msk        (_U_(0x1) << FUSES_BOD33_HYST_Pos)
+
+#define FUSES_HOT_ADC_VAL_ADDR      (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_ADC_VAL_Pos       20           /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define FUSES_HOT_ADC_VAL_Msk       (_U_(0xFFF) << FUSES_HOT_ADC_VAL_Pos)
+#define FUSES_HOT_ADC_VAL(value)    (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
+
+#define FUSES_HOT_INT1V_VAL_ADDR    (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_INT1V_VAL_Pos     0            /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define FUSES_HOT_INT1V_VAL_Msk     (_U_(0xFF) << FUSES_HOT_INT1V_VAL_Pos)
+#define FUSES_HOT_INT1V_VAL(value)  (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
+
+#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_DEC_Pos  20           /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define FUSES_HOT_TEMP_VAL_DEC_Msk  (_U_(0xF) << FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
+
+#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_INT_Pos  12           /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define FUSES_HOT_TEMP_VAL_INT_Msk  (_U_(0xFF) << FUSES_HOT_TEMP_VAL_INT_Pos)
+#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
+
+#define FUSES_ROOM_ADC_VAL_ADDR     (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_ROOM_ADC_VAL_Pos      8            /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define FUSES_ROOM_ADC_VAL_Msk      (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_Pos)
+#define FUSES_ROOM_ADC_VAL(value)   (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
+
+#define FUSES_ROOM_INT1V_VAL_ADDR   NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_INT1V_VAL_Pos    24           /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define FUSES_ROOM_INT1V_VAL_Msk    (_U_(0xFF) << FUSES_ROOM_INT1V_VAL_Pos)
+#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8            /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define FUSES_ROOM_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_INT_Pos 0            /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define FUSES_ROOM_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
+
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_BOOTPROT_Pos  0            /**< \brief (NVMCTRL_USER) Bootloader Size */
+#define NVMCTRL_FUSES_BOOTPROT_Msk  (_U_(0x7) << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
+
+#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4            /**< \brief (NVMCTRL_USER) EEPROM Size */
+#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (_U_(0x7) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
+#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
+
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16           /**< \brief (NVMCTRL_USER) NVM Region Locks */
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U_(0xFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
+
+#define USB_FUSES_TRANSN_ADDR       NVMCTRL_OTP5
+#define USB_FUSES_TRANSN_Pos        13           /**< \brief (NVMCTRL_OTP5) USB pad Transn calibration */
+#define USB_FUSES_TRANSN_Msk        (_U_(0x1F) << USB_FUSES_TRANSN_Pos)
+#define USB_FUSES_TRANSN(value)     (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
+
+#define USB_FUSES_TRANSP_ADDR       NVMCTRL_OTP5
+#define USB_FUSES_TRANSP_Pos        18           /**< \brief (NVMCTRL_OTP5) USB pad Transp calibration */
+#define USB_FUSES_TRANSP_Msk        (_U_(0x1F) << USB_FUSES_TRANSP_Pos)
+#define USB_FUSES_TRANSP(value)     (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
+
+#define USB_FUSES_TRIM_ADDR         NVMCTRL_OTP5
+#define USB_FUSES_TRIM_Pos          23           /**< \brief (NVMCTRL_OTP5) USB pad Trim calibration */
+#define USB_FUSES_TRIM_Msk          (_U_(0x7) << USB_FUSES_TRIM_Pos)
+#define USB_FUSES_TRIM(value)       (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
+
+#define WDT_FUSES_ALWAYSON_ADDR     NVMCTRL_USER
+#define WDT_FUSES_ALWAYSON_Pos      27           /**< \brief (NVMCTRL_USER) WDT Always On */
+#define WDT_FUSES_ALWAYSON_Msk      (_U_(0x1) << WDT_FUSES_ALWAYSON_Pos)
+
+#define WDT_FUSES_ENABLE_ADDR       NVMCTRL_USER
+#define WDT_FUSES_ENABLE_Pos        26           /**< \brief (NVMCTRL_USER) WDT Enable */
+#define WDT_FUSES_ENABLE_Msk        (_U_(0x1) << WDT_FUSES_ENABLE_Pos)
+
+#define WDT_FUSES_EWOFFSET_ADDR     (NVMCTRL_USER + 4)
+#define WDT_FUSES_EWOFFSET_Pos      4            /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
+#define WDT_FUSES_EWOFFSET_Msk      (_U_(0xF) << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET(value)   (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
+
+#define WDT_FUSES_PER_ADDR          NVMCTRL_USER
+#define WDT_FUSES_PER_Pos           28           /**< \brief (NVMCTRL_USER) WDT Period */
+#define WDT_FUSES_PER_Msk           (_U_(0xF) << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER(value)        (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
+
+#define WDT_FUSES_WEN_ADDR          (NVMCTRL_USER + 4)
+#define WDT_FUSES_WEN_Pos           8            /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
+#define WDT_FUSES_WEN_Msk           (_U_(0x1) << WDT_FUSES_WEN_Pos)
+
+#define WDT_FUSES_WINDOW_ADDR       (NVMCTRL_USER + 4)
+#define WDT_FUSES_WINDOW_Pos        0            /**< \brief (NVMCTRL_USER) WDT Window */
+#define WDT_FUSES_WINDOW_Msk        (_U_(0xF) << WDT_FUSES_WINDOW_Pos)
+#define WDT_FUSES_WINDOW(value)     (WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos))
+
+/*@}*/
+
+#endif /* _SAMR34_NVMCTRL_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/osc32kctrl.h

@@ -0,0 +1,284 @@
+/**
+ * \file
+ *
+ * \brief Component description for OSC32KCTRL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_OSC32KCTRL_COMPONENT_
+#define _SAMR34_OSC32KCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR OSC32KCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMR34_OSC32KCTRL 32k Oscillators Control */
+/*@{*/
+
+#define OSC32KCTRL_U2246
+#define REV_OSC32KCTRL              0x110
+
+/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready Interrupt Enable     */
+    uint32_t OSC32KRDY:1;      /*!< bit:      1  OSC32K Ready Interrupt Enable      */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTENCLR_OFFSET  0x00         /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTENCLR_OSC32KRDY_Pos 1            /**< \brief (OSC32KCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
+#define OSC32KCTRL_INTENCLR_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_OSC32KRDY_Pos)
+#define OSC32KCTRL_INTENCLR_MASK    _U_(0x00000003) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */
+
+/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready Interrupt Enable     */
+    uint32_t OSC32KRDY:1;      /*!< bit:      1  OSC32K Ready Interrupt Enable      */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTENSET_OFFSET  0x04         /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */
+#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
+#define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTENSET_OSC32KRDY_Pos 1            /**< \brief (OSC32KCTRL_INTENSET) OSC32K Ready Interrupt Enable */
+#define OSC32KCTRL_INTENSET_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_OSC32KRDY_Pos)
+#define OSC32KCTRL_INTENSET_MASK    _U_(0x00000003) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */
+
+/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready                      */
+    __I uint32_t OSC32KRDY:1;      /*!< bit:      1  OSC32K Ready                       */
+    __I uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_INTFLAG_OFFSET   0x08         /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)
+#define OSC32KCTRL_INTFLAG_OSC32KRDY_Pos 1            /**< \brief (OSC32KCTRL_INTFLAG) OSC32K Ready */
+#define OSC32KCTRL_INTFLAG_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_OSC32KRDY_Pos)
+#define OSC32KCTRL_INTFLAG_MASK     _U_(0x00000003) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */
+
+/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/  32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSC32KRDY:1;     /*!< bit:      0  XOSC32K Ready                      */
+    uint32_t OSC32KRDY:1;      /*!< bit:      1  OSC32K Ready                       */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_STATUS_OFFSET    0x0C         /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */
+#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */
+
+#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0            /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */
+#define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)
+#define OSC32KCTRL_STATUS_OSC32KRDY_Pos 1            /**< \brief (OSC32KCTRL_STATUS) OSC32K Ready */
+#define OSC32KCTRL_STATUS_OSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_OSC32KRDY_Pos)
+#define OSC32KCTRL_STATUS_MASK      _U_(0x00000003) /**< \brief (OSC32KCTRL_STATUS) MASK Register */
+
+/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 32) Clock selection -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t RTCSEL:3;         /*!< bit:  0.. 2  RTC Clock Selection                */
+    uint32_t :29;              /*!< bit:  3..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_RTCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_RTCCTRL_OFFSET   0x10         /**< \brief (OSC32KCTRL_RTCCTRL offset) Clock selection */
+#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_RTCCTRL reset_value) Clock selection */
+
+#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0            /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0)   /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1)   /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val _U_(0x2)   /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val _U_(0x3)   /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz internal oscillator */
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4)   /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5)   /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
+#define OSC32KCTRL_RTCCTRL_MASK     _U_(0x00000007) /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */
+
+/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint32_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint32_t EN32K:1;          /*!< bit:      3  32kHz Output Enable                */
+    uint32_t EN1K:1;           /*!< bit:      4  1kHz Output Enable                 */
+    uint32_t :1;               /*!< bit:      5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint32_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
+    uint32_t :19;              /*!< bit: 13..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_XOSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_XOSC32K_OFFSET   0x14         /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x00000080) /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
+
+#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1            /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */
+#define OSC32KCTRL_XOSC32K_ENABLE   (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)
+#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2            /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */
+#define OSC32KCTRL_XOSC32K_XTALEN   (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)
+#define OSC32KCTRL_XOSC32K_EN32K_Pos 3            /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */
+#define OSC32KCTRL_XOSC32K_EN32K    (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)
+#define OSC32KCTRL_XOSC32K_EN1K_Pos 4            /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */
+#define OSC32KCTRL_XOSC32K_EN1K     (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)
+#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6            /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */
+#define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
+#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7            /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */
+#define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
+#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8            /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */
+#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)
+#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
+#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12           /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */
+#define OSC32KCTRL_XOSC32K_WRTLOCK  (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)
+#define OSC32KCTRL_XOSC32K_MASK     _U_(0x000017DE) /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */
+
+/* -------- OSC32KCTRL_OSC32K : (OSC32KCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :1;               /*!< bit:      0  Reserved                           */
+    uint32_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint32_t EN32K:1;          /*!< bit:      2  32kHz Output Enable                */
+    uint32_t EN1K:1;           /*!< bit:      3  1kHz Output Enable                 */
+    uint32_t :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint32_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint32_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint32_t STARTUP:3;        /*!< bit:  8..10  Oscillator Start-Up Time           */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t WRTLOCK:1;        /*!< bit:     12  Write Lock                         */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t CALIB:7;          /*!< bit: 16..22  Oscillator Calibration             */
+    uint32_t :9;               /*!< bit: 23..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_OSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_OSC32K_OFFSET    0x18         /**< \brief (OSC32KCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
+#define OSC32KCTRL_OSC32K_RESETVALUE _U_(0x003F0080) /**< \brief (OSC32KCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
+
+#define OSC32KCTRL_OSC32K_ENABLE_Pos 1            /**< \brief (OSC32KCTRL_OSC32K) Oscillator Enable */
+#define OSC32KCTRL_OSC32K_ENABLE    (_U_(0x1) << OSC32KCTRL_OSC32K_ENABLE_Pos)
+#define OSC32KCTRL_OSC32K_EN32K_Pos 2            /**< \brief (OSC32KCTRL_OSC32K) 32kHz Output Enable */
+#define OSC32KCTRL_OSC32K_EN32K     (_U_(0x1) << OSC32KCTRL_OSC32K_EN32K_Pos)
+#define OSC32KCTRL_OSC32K_EN1K_Pos  3            /**< \brief (OSC32KCTRL_OSC32K) 1kHz Output Enable */
+#define OSC32KCTRL_OSC32K_EN1K      (_U_(0x1) << OSC32KCTRL_OSC32K_EN1K_Pos)
+#define OSC32KCTRL_OSC32K_RUNSTDBY_Pos 6            /**< \brief (OSC32KCTRL_OSC32K) Run in Standby */
+#define OSC32KCTRL_OSC32K_RUNSTDBY  (_U_(0x1) << OSC32KCTRL_OSC32K_RUNSTDBY_Pos)
+#define OSC32KCTRL_OSC32K_ONDEMAND_Pos 7            /**< \brief (OSC32KCTRL_OSC32K) On Demand Control */
+#define OSC32KCTRL_OSC32K_ONDEMAND  (_U_(0x1) << OSC32KCTRL_OSC32K_ONDEMAND_Pos)
+#define OSC32KCTRL_OSC32K_STARTUP_Pos 8            /**< \brief (OSC32KCTRL_OSC32K) Oscillator Start-Up Time */
+#define OSC32KCTRL_OSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_OSC32K_STARTUP_Pos)
+#define OSC32KCTRL_OSC32K_STARTUP(value) (OSC32KCTRL_OSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_OSC32K_STARTUP_Pos))
+#define OSC32KCTRL_OSC32K_WRTLOCK_Pos 12           /**< \brief (OSC32KCTRL_OSC32K) Write Lock */
+#define OSC32KCTRL_OSC32K_WRTLOCK   (_U_(0x1) << OSC32KCTRL_OSC32K_WRTLOCK_Pos)
+#define OSC32KCTRL_OSC32K_CALIB_Pos 16           /**< \brief (OSC32KCTRL_OSC32K) Oscillator Calibration */
+#define OSC32KCTRL_OSC32K_CALIB_Msk (_U_(0x7F) << OSC32KCTRL_OSC32K_CALIB_Pos)
+#define OSC32KCTRL_OSC32K_CALIB(value) (OSC32KCTRL_OSC32K_CALIB_Msk & ((value) << OSC32KCTRL_OSC32K_CALIB_Pos))
+#define OSC32KCTRL_OSC32K_MASK      _U_(0x007F17CE) /**< \brief (OSC32KCTRL_OSC32K) MASK Register */
+
+/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t :8;               /*!< bit:  0.. 7  Reserved                           */
+    uint32_t CALIB:5;          /*!< bit:  8..12  Oscillator Calibration             */
+    uint32_t :2;               /*!< bit: 13..14  Reserved                           */
+    uint32_t WRTLOCK:1;        /*!< bit:     15  Write Lock                         */
+    uint32_t :16;              /*!< bit: 16..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSC32KCTRL_OSCULP32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C         /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+
+#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8            /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */
+#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x1F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)
+#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
+#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15           /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */
+#define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)
+#define OSC32KCTRL_OSCULP32K_MASK   _U_(0x00009F00) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */
+
+/** \brief OSC32KCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO OSC32KCTRL_INTENCLR_Type  INTENCLR;    /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+  __IO OSC32KCTRL_INTENSET_Type  INTENSET;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+  __IO OSC32KCTRL_INTFLAG_Type   INTFLAG;     /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+  __I  OSC32KCTRL_STATUS_Type    STATUS;      /**< \brief Offset: 0x0C (R/  32) Power and Clocks Status */
+  __IO OSC32KCTRL_RTCCTRL_Type   RTCCTRL;     /**< \brief Offset: 0x10 (R/W 32) Clock selection */
+  __IO OSC32KCTRL_XOSC32K_Type   XOSC32K;     /**< \brief Offset: 0x14 (R/W 32) 32kHz External Crystal Oscillator (XOSC32K) Control */
+  __IO OSC32KCTRL_OSC32K_Type    OSC32K;      /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
+  __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K;   /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+} Osc32kctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_OSC32KCTRL_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/oscctrl.h

@@ -0,0 +1,635 @@
+/**
+ * \file
+ *
+ * \brief Component description for OSCCTRL
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_OSCCTRL_COMPONENT_
+#define _SAMR34_OSCCTRL_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR OSCCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMR34_OSCCTRL Oscillators Control */
+/*@{*/
+
+#define OSCCTRL_U2119
+#define REV_OSCCTRL                 0x110
+
+/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready Interrupt Enable        */
+    uint32_t :3;               /*!< bit:  1.. 3  Reserved                           */
+    uint32_t OSC16MRDY:1;      /*!< bit:      4  OSC16M Ready Interrupt Enable      */
+    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready Interrupt Enable        */
+    uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds Interrupt Enable */
+    uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine Interrupt Enable    */
+    uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse Interrupt Enable  */
+    uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped Interrupt Enable */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     16  DPLL Lock Rise Interrupt Enable    */
+    uint32_t DPLLLCKF:1;       /*!< bit:     17  DPLL Lock Fall Interrupt Enable    */
+    uint32_t DPLLLTO:1;        /*!< bit:     18  DPLL Time Out Interrupt Enable     */
+    uint32_t DPLLLDRTO:1;      /*!< bit:     19  DPLL Ratio Ready Interrupt Enable  */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTENCLR_OFFSET     0x00         /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define OSCCTRL_INTENCLR_XOSCRDY_Pos 0            /**< \brief (OSCCTRL_INTENCLR) XOSC Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCRDY    (_U_(0x1) << OSCCTRL_INTENCLR_XOSCRDY_Pos)
+#define OSCCTRL_INTENCLR_OSC16MRDY_Pos 4            /**< \brief (OSCCTRL_INTENCLR) OSC16M Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_OSC16MRDY  (_U_(0x1) << OSCCTRL_INTENCLR_OSC16MRDY_Pos)
+#define OSCCTRL_INTENCLR_DFLLRDY_Pos 8            /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLRDY    (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos)
+#define OSCCTRL_INTENCLR_DFLLOOB_Pos 9            /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLOOB    (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos)
+#define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLLCKF   (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos)
+#define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLLCKC   (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos)
+#define OSCCTRL_INTENCLR_DFLLRCS_Pos 12           /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
+#define OSCCTRL_INTENCLR_DFLLRCS    (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos)
+#define OSCCTRL_INTENCLR_DPLLLCKR_Pos 16           /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLLLCKR   (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLCKR_Pos)
+#define OSCCTRL_INTENCLR_DPLLLCKF_Pos 17           /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLLLCKF   (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLCKF_Pos)
+#define OSCCTRL_INTENCLR_DPLLLTO_Pos 18           /**< \brief (OSCCTRL_INTENCLR) DPLL Time Out Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLLLTO    (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLTO_Pos)
+#define OSCCTRL_INTENCLR_DPLLLDRTO_Pos 19           /**< \brief (OSCCTRL_INTENCLR) DPLL Ratio Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_DPLLLDRTO  (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLDRTO_Pos)
+#define OSCCTRL_INTENCLR_MASK       _U_(0x000F1F11) /**< \brief (OSCCTRL_INTENCLR) MASK Register */
+
+/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready Interrupt Enable        */
+    uint32_t :3;               /*!< bit:  1.. 3  Reserved                           */
+    uint32_t OSC16MRDY:1;      /*!< bit:      4  OSC16M Ready Interrupt Enable      */
+    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready Interrupt Enable        */
+    uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds Interrupt Enable */
+    uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine Interrupt Enable    */
+    uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse Interrupt Enable  */
+    uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped Interrupt Enable */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     16  DPLL Lock Rise Interrupt Enable    */
+    uint32_t DPLLLCKF:1;       /*!< bit:     17  DPLL Lock Fall Interrupt Enable    */
+    uint32_t DPLLLTO:1;        /*!< bit:     18  DPLL Time Out Interrupt Enable     */
+    uint32_t DPLLLDRTO:1;      /*!< bit:     19  DPLL Ratio Ready Interrupt Enable  */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTENSET_OFFSET     0x04         /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */
+#define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define OSCCTRL_INTENSET_XOSCRDY_Pos 0            /**< \brief (OSCCTRL_INTENSET) XOSC Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCRDY    (_U_(0x1) << OSCCTRL_INTENSET_XOSCRDY_Pos)
+#define OSCCTRL_INTENSET_OSC16MRDY_Pos 4            /**< \brief (OSCCTRL_INTENSET) OSC16M Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_OSC16MRDY  (_U_(0x1) << OSCCTRL_INTENSET_OSC16MRDY_Pos)
+#define OSCCTRL_INTENSET_DFLLRDY_Pos 8            /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLRDY    (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos)
+#define OSCCTRL_INTENSET_DFLLOOB_Pos 9            /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLOOB    (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos)
+#define OSCCTRL_INTENSET_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLLCKF   (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos)
+#define OSCCTRL_INTENSET_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLLCKC   (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos)
+#define OSCCTRL_INTENSET_DFLLRCS_Pos 12           /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
+#define OSCCTRL_INTENSET_DFLLRCS    (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos)
+#define OSCCTRL_INTENSET_DPLLLCKR_Pos 16           /**< \brief (OSCCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLLLCKR   (_U_(0x1) << OSCCTRL_INTENSET_DPLLLCKR_Pos)
+#define OSCCTRL_INTENSET_DPLLLCKF_Pos 17           /**< \brief (OSCCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLLLCKF   (_U_(0x1) << OSCCTRL_INTENSET_DPLLLCKF_Pos)
+#define OSCCTRL_INTENSET_DPLLLTO_Pos 18           /**< \brief (OSCCTRL_INTENSET) DPLL Time Out Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLLLTO    (_U_(0x1) << OSCCTRL_INTENSET_DPLLLTO_Pos)
+#define OSCCTRL_INTENSET_DPLLLDRTO_Pos 19           /**< \brief (OSCCTRL_INTENSET) DPLL Ratio Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_DPLLLDRTO  (_U_(0x1) << OSCCTRL_INTENSET_DPLLLDRTO_Pos)
+#define OSCCTRL_INTENSET_MASK       _U_(0x000F1F11) /**< \brief (OSCCTRL_INTENSET) MASK Register */
+
+/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    __I uint32_t :3;               /*!< bit:  1.. 3  Reserved                           */
+    __I uint32_t OSC16MRDY:1;      /*!< bit:      4  OSC16M Ready                       */
+    __I uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    __I uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready                         */
+    __I uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds                 */
+    __I uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine                     */
+    __I uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse                   */
+    __I uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped       */
+    __I uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    __I uint32_t DPLLLCKR:1;       /*!< bit:     16  DPLL Lock Rise                     */
+    __I uint32_t DPLLLCKF:1;       /*!< bit:     17  DPLL Lock Fall                     */
+    __I uint32_t DPLLLTO:1;        /*!< bit:     18  DPLL Timeout                       */
+    __I uint32_t DPLLLDRTO:1;      /*!< bit:     19  DPLL Ratio Ready                   */
+    __I uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_INTFLAG_OFFSET      0x08         /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define OSCCTRL_INTFLAG_RESETVALUE  _U_(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define OSCCTRL_INTFLAG_XOSCRDY_Pos 0            /**< \brief (OSCCTRL_INTFLAG) XOSC Ready */
+#define OSCCTRL_INTFLAG_XOSCRDY     (_U_(0x1) << OSCCTRL_INTFLAG_XOSCRDY_Pos)
+#define OSCCTRL_INTFLAG_OSC16MRDY_Pos 4            /**< \brief (OSCCTRL_INTFLAG) OSC16M Ready */
+#define OSCCTRL_INTFLAG_OSC16MRDY   (_U_(0x1) << OSCCTRL_INTFLAG_OSC16MRDY_Pos)
+#define OSCCTRL_INTFLAG_DFLLRDY_Pos 8            /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */
+#define OSCCTRL_INTFLAG_DFLLRDY     (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos)
+#define OSCCTRL_INTFLAG_DFLLOOB_Pos 9            /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */
+#define OSCCTRL_INTFLAG_DFLLOOB     (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos)
+#define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */
+#define OSCCTRL_INTFLAG_DFLLLCKF    (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos)
+#define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */
+#define OSCCTRL_INTFLAG_DFLLLCKC    (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos)
+#define OSCCTRL_INTFLAG_DFLLRCS_Pos 12           /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */
+#define OSCCTRL_INTFLAG_DFLLRCS     (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos)
+#define OSCCTRL_INTFLAG_DPLLLCKR_Pos 16           /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Rise */
+#define OSCCTRL_INTFLAG_DPLLLCKR    (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLCKR_Pos)
+#define OSCCTRL_INTFLAG_DPLLLCKF_Pos 17           /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Fall */
+#define OSCCTRL_INTFLAG_DPLLLCKF    (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLCKF_Pos)
+#define OSCCTRL_INTFLAG_DPLLLTO_Pos 18           /**< \brief (OSCCTRL_INTFLAG) DPLL Timeout */
+#define OSCCTRL_INTFLAG_DPLLLTO     (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLTO_Pos)
+#define OSCCTRL_INTFLAG_DPLLLDRTO_Pos 19           /**< \brief (OSCCTRL_INTFLAG) DPLL Ratio Ready */
+#define OSCCTRL_INTFLAG_DPLLLDRTO   (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLDRTO_Pos)
+#define OSCCTRL_INTFLAG_MASK        _U_(0x000F1F11) /**< \brief (OSCCTRL_INTFLAG) MASK Register */
+
+/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x0C) (R/  32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
+    uint32_t :3;               /*!< bit:  1.. 3  Reserved                           */
+    uint32_t OSC16MRDY:1;      /*!< bit:      4  OSC16M Ready                       */
+    uint32_t :3;               /*!< bit:  5.. 7  Reserved                           */
+    uint32_t DFLLRDY:1;        /*!< bit:      8  DFLL Ready                         */
+    uint32_t DFLLOOB:1;        /*!< bit:      9  DFLL Out Of Bounds                 */
+    uint32_t DFLLLCKF:1;       /*!< bit:     10  DFLL Lock Fine                     */
+    uint32_t DFLLLCKC:1;       /*!< bit:     11  DFLL Lock Coarse                   */
+    uint32_t DFLLRCS:1;        /*!< bit:     12  DFLL Reference Clock Stopped       */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t DPLLLCKR:1;       /*!< bit:     16  DPLL Lock Rise                     */
+    uint32_t DPLLLCKF:1;       /*!< bit:     17  DPLL Lock Fall                     */
+    uint32_t DPLLTO:1;         /*!< bit:     18  DPLL Timeout                       */
+    uint32_t DPLLLDRTO:1;      /*!< bit:     19  DPLL Ratio Ready                   */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_STATUS_OFFSET       0x0C         /**< \brief (OSCCTRL_STATUS offset) Power and Clocks Status */
+#define OSCCTRL_STATUS_RESETVALUE   _U_(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Power and Clocks Status */
+
+#define OSCCTRL_STATUS_XOSCRDY_Pos  0            /**< \brief (OSCCTRL_STATUS) XOSC Ready */
+#define OSCCTRL_STATUS_XOSCRDY      (_U_(0x1) << OSCCTRL_STATUS_XOSCRDY_Pos)
+#define OSCCTRL_STATUS_OSC16MRDY_Pos 4            /**< \brief (OSCCTRL_STATUS) OSC16M Ready */
+#define OSCCTRL_STATUS_OSC16MRDY    (_U_(0x1) << OSCCTRL_STATUS_OSC16MRDY_Pos)
+#define OSCCTRL_STATUS_DFLLRDY_Pos  8            /**< \brief (OSCCTRL_STATUS) DFLL Ready */
+#define OSCCTRL_STATUS_DFLLRDY      (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos)
+#define OSCCTRL_STATUS_DFLLOOB_Pos  9            /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */
+#define OSCCTRL_STATUS_DFLLOOB      (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos)
+#define OSCCTRL_STATUS_DFLLLCKF_Pos 10           /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */
+#define OSCCTRL_STATUS_DFLLLCKF     (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos)
+#define OSCCTRL_STATUS_DFLLLCKC_Pos 11           /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */
+#define OSCCTRL_STATUS_DFLLLCKC     (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos)
+#define OSCCTRL_STATUS_DFLLRCS_Pos  12           /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */
+#define OSCCTRL_STATUS_DFLLRCS      (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos)
+#define OSCCTRL_STATUS_DPLLLCKR_Pos 16           /**< \brief (OSCCTRL_STATUS) DPLL Lock Rise */
+#define OSCCTRL_STATUS_DPLLLCKR     (_U_(0x1) << OSCCTRL_STATUS_DPLLLCKR_Pos)
+#define OSCCTRL_STATUS_DPLLLCKF_Pos 17           /**< \brief (OSCCTRL_STATUS) DPLL Lock Fall */
+#define OSCCTRL_STATUS_DPLLLCKF     (_U_(0x1) << OSCCTRL_STATUS_DPLLLCKF_Pos)
+#define OSCCTRL_STATUS_DPLLTO_Pos   18           /**< \brief (OSCCTRL_STATUS) DPLL Timeout */
+#define OSCCTRL_STATUS_DPLLTO       (_U_(0x1) << OSCCTRL_STATUS_DPLLTO_Pos)
+#define OSCCTRL_STATUS_DPLLLDRTO_Pos 19           /**< \brief (OSCCTRL_STATUS) DPLL Ratio Ready */
+#define OSCCTRL_STATUS_DPLLLDRTO    (_U_(0x1) << OSCCTRL_STATUS_DPLLLDRTO_Pos)
+#define OSCCTRL_STATUS_MASK         _U_(0x000F1F11) /**< \brief (OSCCTRL_STATUS) MASK Register */
+
+/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint16_t XTALEN:1;         /*!< bit:      2  Crystal Oscillator Enable          */
+    uint16_t :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t GAIN:3;           /*!< bit:  8..10  Oscillator Gain                    */
+    uint16_t AMPGC:1;          /*!< bit:     11  Automatic Amplitude Gain Control   */
+    uint16_t STARTUP:4;        /*!< bit: 12..15  Start-Up Time                      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_XOSCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_XOSCCTRL_OFFSET     0x10         /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x0080)  /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
+
+#define OSCCTRL_XOSCCTRL_ENABLE_Pos 1            /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */
+#define OSCCTRL_XOSCCTRL_ENABLE     (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos)
+#define OSCCTRL_XOSCCTRL_XTALEN_Pos 2            /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */
+#define OSCCTRL_XOSCCTRL_XTALEN     (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos)
+#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6            /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */
+#define OSCCTRL_XOSCCTRL_RUNSTDBY   (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
+#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7            /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */
+#define OSCCTRL_XOSCCTRL_ONDEMAND   (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)
+#define OSCCTRL_XOSCCTRL_GAIN_Pos   8            /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Gain */
+#define OSCCTRL_XOSCCTRL_GAIN_Msk   (_U_(0x7) << OSCCTRL_XOSCCTRL_GAIN_Pos)
+#define OSCCTRL_XOSCCTRL_GAIN(value) (OSCCTRL_XOSCCTRL_GAIN_Msk & ((value) << OSCCTRL_XOSCCTRL_GAIN_Pos))
+#define OSCCTRL_XOSCCTRL_AMPGC_Pos  11           /**< \brief (OSCCTRL_XOSCCTRL) Automatic Amplitude Gain Control */
+#define OSCCTRL_XOSCCTRL_AMPGC      (_U_(0x1) << OSCCTRL_XOSCCTRL_AMPGC_Pos)
+#define OSCCTRL_XOSCCTRL_STARTUP_Pos 12           /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */
+#define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos)
+#define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
+#define OSCCTRL_XOSCCTRL_MASK       _U_(0xFFC6)  /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */
+
+/* -------- OSCCTRL_OSC16MCTRL : (OSCCTRL Offset: 0x14) (R/W  8) 16MHz Internal Oscillator (OSC16M) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Oscillator Enable                  */
+    uint8_t  FSEL:2;           /*!< bit:  2.. 3  Oscillator Frequency Select        */
+    uint8_t  :2;               /*!< bit:  4.. 5  Reserved                           */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint8_t  ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSCCTRL_OSC16MCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_OSC16MCTRL_OFFSET   0x14         /**< \brief (OSCCTRL_OSC16MCTRL offset) 16MHz Internal Oscillator (OSC16M) Control */
+#define OSCCTRL_OSC16MCTRL_RESETVALUE _U_(0x82)    /**< \brief (OSCCTRL_OSC16MCTRL reset_value) 16MHz Internal Oscillator (OSC16M) Control */
+
+#define OSCCTRL_OSC16MCTRL_ENABLE_Pos 1            /**< \brief (OSCCTRL_OSC16MCTRL) Oscillator Enable */
+#define OSCCTRL_OSC16MCTRL_ENABLE   (_U_(0x1) << OSCCTRL_OSC16MCTRL_ENABLE_Pos)
+#define OSCCTRL_OSC16MCTRL_FSEL_Pos 2            /**< \brief (OSCCTRL_OSC16MCTRL) Oscillator Frequency Select */
+#define OSCCTRL_OSC16MCTRL_FSEL_Msk (_U_(0x3) << OSCCTRL_OSC16MCTRL_FSEL_Pos)
+#define OSCCTRL_OSC16MCTRL_FSEL(value) (OSCCTRL_OSC16MCTRL_FSEL_Msk & ((value) << OSCCTRL_OSC16MCTRL_FSEL_Pos))
+#define   OSCCTRL_OSC16MCTRL_FSEL_4_Val   _U_(0x0)   /**< \brief (OSCCTRL_OSC16MCTRL) 4MHz */
+#define   OSCCTRL_OSC16MCTRL_FSEL_8_Val   _U_(0x1)   /**< \brief (OSCCTRL_OSC16MCTRL) 8MHz */
+#define   OSCCTRL_OSC16MCTRL_FSEL_12_Val  _U_(0x2)   /**< \brief (OSCCTRL_OSC16MCTRL) 12MHz */
+#define   OSCCTRL_OSC16MCTRL_FSEL_16_Val  _U_(0x3)   /**< \brief (OSCCTRL_OSC16MCTRL) 16MHz */
+#define OSCCTRL_OSC16MCTRL_FSEL_4   (OSCCTRL_OSC16MCTRL_FSEL_4_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos)
+#define OSCCTRL_OSC16MCTRL_FSEL_8   (OSCCTRL_OSC16MCTRL_FSEL_8_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos)
+#define OSCCTRL_OSC16MCTRL_FSEL_12  (OSCCTRL_OSC16MCTRL_FSEL_12_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos)
+#define OSCCTRL_OSC16MCTRL_FSEL_16  (OSCCTRL_OSC16MCTRL_FSEL_16_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos)
+#define OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos 6            /**< \brief (OSCCTRL_OSC16MCTRL) Run in Standby */
+#define OSCCTRL_OSC16MCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos)
+#define OSCCTRL_OSC16MCTRL_ONDEMAND_Pos 7            /**< \brief (OSCCTRL_OSC16MCTRL) On Demand Control */
+#define OSCCTRL_OSC16MCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos)
+#define OSCCTRL_OSC16MCTRL_MASK     _U_(0xCE)    /**< \brief (OSCCTRL_OSC16MCTRL) MASK Register */
+
+/* -------- OSCCTRL_DFLLCTRL : (OSCCTRL Offset: 0x18) (R/W 16) DFLL48M Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t :1;               /*!< bit:      0  Reserved                           */
+    uint16_t ENABLE:1;         /*!< bit:      1  DFLL Enable                        */
+    uint16_t MODE:1;           /*!< bit:      2  Operating Mode Selection           */
+    uint16_t STABLE:1;         /*!< bit:      3  Stable DFLL Frequency              */
+    uint16_t LLAW:1;           /*!< bit:      4  Lose Lock After Wake               */
+    uint16_t USBCRM:1;         /*!< bit:      5  USB Clock Recovery Mode            */
+    uint16_t RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint16_t ONDEMAND:1;       /*!< bit:      7  On Demand Control                  */
+    uint16_t CCDIS:1;          /*!< bit:      8  Chill Cycle Disable                */
+    uint16_t QLDIS:1;          /*!< bit:      9  Quick Lock Disable                 */
+    uint16_t BPLCKC:1;         /*!< bit:     10  Bypass Coarse Lock                 */
+    uint16_t WAITLOCK:1;       /*!< bit:     11  Wait Lock                          */
+    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_DFLLCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLCTRL_OFFSET     0x18         /**< \brief (OSCCTRL_DFLLCTRL offset) DFLL48M Control */
+#define OSCCTRL_DFLLCTRL_RESETVALUE _U_(0x0080)  /**< \brief (OSCCTRL_DFLLCTRL reset_value) DFLL48M Control */
+
+#define OSCCTRL_DFLLCTRL_ENABLE_Pos 1            /**< \brief (OSCCTRL_DFLLCTRL) DFLL Enable */
+#define OSCCTRL_DFLLCTRL_ENABLE     (_U_(0x1) << OSCCTRL_DFLLCTRL_ENABLE_Pos)
+#define OSCCTRL_DFLLCTRL_MODE_Pos   2            /**< \brief (OSCCTRL_DFLLCTRL) Operating Mode Selection */
+#define OSCCTRL_DFLLCTRL_MODE       (_U_(0x1) << OSCCTRL_DFLLCTRL_MODE_Pos)
+#define OSCCTRL_DFLLCTRL_STABLE_Pos 3            /**< \brief (OSCCTRL_DFLLCTRL) Stable DFLL Frequency */
+#define OSCCTRL_DFLLCTRL_STABLE     (_U_(0x1) << OSCCTRL_DFLLCTRL_STABLE_Pos)
+#define OSCCTRL_DFLLCTRL_LLAW_Pos   4            /**< \brief (OSCCTRL_DFLLCTRL) Lose Lock After Wake */
+#define OSCCTRL_DFLLCTRL_LLAW       (_U_(0x1) << OSCCTRL_DFLLCTRL_LLAW_Pos)
+#define OSCCTRL_DFLLCTRL_USBCRM_Pos 5            /**< \brief (OSCCTRL_DFLLCTRL) USB Clock Recovery Mode */
+#define OSCCTRL_DFLLCTRL_USBCRM     (_U_(0x1) << OSCCTRL_DFLLCTRL_USBCRM_Pos)
+#define OSCCTRL_DFLLCTRL_RUNSTDBY_Pos 6            /**< \brief (OSCCTRL_DFLLCTRL) Run in Standby */
+#define OSCCTRL_DFLLCTRL_RUNSTDBY   (_U_(0x1) << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos)
+#define OSCCTRL_DFLLCTRL_ONDEMAND_Pos 7            /**< \brief (OSCCTRL_DFLLCTRL) On Demand Control */
+#define OSCCTRL_DFLLCTRL_ONDEMAND   (_U_(0x1) << OSCCTRL_DFLLCTRL_ONDEMAND_Pos)
+#define OSCCTRL_DFLLCTRL_CCDIS_Pos  8            /**< \brief (OSCCTRL_DFLLCTRL) Chill Cycle Disable */
+#define OSCCTRL_DFLLCTRL_CCDIS      (_U_(0x1) << OSCCTRL_DFLLCTRL_CCDIS_Pos)
+#define OSCCTRL_DFLLCTRL_QLDIS_Pos  9            /**< \brief (OSCCTRL_DFLLCTRL) Quick Lock Disable */
+#define OSCCTRL_DFLLCTRL_QLDIS      (_U_(0x1) << OSCCTRL_DFLLCTRL_QLDIS_Pos)
+#define OSCCTRL_DFLLCTRL_BPLCKC_Pos 10           /**< \brief (OSCCTRL_DFLLCTRL) Bypass Coarse Lock */
+#define OSCCTRL_DFLLCTRL_BPLCKC     (_U_(0x1) << OSCCTRL_DFLLCTRL_BPLCKC_Pos)
+#define OSCCTRL_DFLLCTRL_WAITLOCK_Pos 11           /**< \brief (OSCCTRL_DFLLCTRL) Wait Lock */
+#define OSCCTRL_DFLLCTRL_WAITLOCK   (_U_(0x1) << OSCCTRL_DFLLCTRL_WAITLOCK_Pos)
+#define OSCCTRL_DFLLCTRL_MASK       _U_(0x0FFE)  /**< \brief (OSCCTRL_DFLLCTRL) MASK Register */
+
+/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x1C) (R/W 32) DFLL48M Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FINE:10;          /*!< bit:  0.. 9  Fine Value                         */
+    uint32_t COARSE:6;         /*!< bit: 10..15  Coarse Value                       */
+    uint32_t DIFF:16;          /*!< bit: 16..31  Multiplication Ratio Difference    */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_DFLLVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLVAL_OFFSET      0x1C         /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */
+#define OSCCTRL_DFLLVAL_RESETVALUE  _U_(0x00000000) /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */
+
+#define OSCCTRL_DFLLVAL_FINE_Pos    0            /**< \brief (OSCCTRL_DFLLVAL) Fine Value */
+#define OSCCTRL_DFLLVAL_FINE_Msk    (_U_(0x3FF) << OSCCTRL_DFLLVAL_FINE_Pos)
+#define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))
+#define OSCCTRL_DFLLVAL_COARSE_Pos  10           /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */
+#define OSCCTRL_DFLLVAL_COARSE_Msk  (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos)
+#define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))
+#define OSCCTRL_DFLLVAL_DIFF_Pos    16           /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */
+#define OSCCTRL_DFLLVAL_DIFF_Msk    (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos)
+#define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))
+#define OSCCTRL_DFLLVAL_MASK        _U_(0xFFFFFFFF) /**< \brief (OSCCTRL_DFLLVAL) MASK Register */
+
+/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x20) (R/W 32) DFLL48M Multiplier -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t MUL:16;           /*!< bit:  0..15  DFLL Multiply Factor               */
+    uint32_t FSTEP:10;         /*!< bit: 16..25  Fine Maximum Step                  */
+    uint32_t CSTEP:6;          /*!< bit: 26..31  Coarse Maximum Step                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_DFLLMUL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLMUL_OFFSET      0x20         /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */
+#define OSCCTRL_DFLLMUL_RESETVALUE  _U_(0x00000000) /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
+
+#define OSCCTRL_DFLLMUL_MUL_Pos     0            /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */
+#define OSCCTRL_DFLLMUL_MUL_Msk     (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos)
+#define OSCCTRL_DFLLMUL_MUL(value)  (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))
+#define OSCCTRL_DFLLMUL_FSTEP_Pos   16           /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */
+#define OSCCTRL_DFLLMUL_FSTEP_Msk   (_U_(0x3FF) << OSCCTRL_DFLLMUL_FSTEP_Pos)
+#define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))
+#define OSCCTRL_DFLLMUL_CSTEP_Pos   26           /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */
+#define OSCCTRL_DFLLMUL_CSTEP_Msk   (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos)
+#define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))
+#define OSCCTRL_DFLLMUL_MASK        _U_(0xFFFFFFFF) /**< \brief (OSCCTRL_DFLLMUL) MASK Register */
+
+/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x24) (R/W  8) DFLL48M Synchronization -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :7;               /*!< bit:  0.. 6  Reserved                           */
+    uint8_t  READREQ:1;        /*!< bit:      7  Read Request                       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSCCTRL_DFLLSYNC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DFLLSYNC_OFFSET     0x24         /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */
+#define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00)    /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
+
+#define OSCCTRL_DFLLSYNC_READREQ_Pos 7            /**< \brief (OSCCTRL_DFLLSYNC) Read Request */
+#define OSCCTRL_DFLLSYNC_READREQ    (_U_(0x1) << OSCCTRL_DFLLSYNC_READREQ_Pos)
+#define OSCCTRL_DFLLSYNC_MASK       _U_(0x80)    /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */
+
+/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x28) (R/W  8) DPLL Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  Enable                             */
+    uint8_t  :4;               /*!< bit:  2.. 5  Reserved                           */
+    uint8_t  RUNSTDBY:1;       /*!< bit:      6  Run in Standby                     */
+    uint8_t  ONDEMAND:1;       /*!< bit:      7  On Demand                          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSCCTRL_DPLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLCTRLA_OFFSET    0x28         /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control */
+#define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80)    /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control */
+
+#define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1            /**< \brief (OSCCTRL_DPLLCTRLA) Enable */
+#define OSCCTRL_DPLLCTRLA_ENABLE    (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)
+#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6            /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */
+#define OSCCTRL_DPLLCTRLA_RUNSTDBY  (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7            /**< \brief (OSCCTRL_DPLLCTRLA) On Demand */
+#define OSCCTRL_DPLLCTRLA_ONDEMAND  (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)
+#define OSCCTRL_DPLLCTRLA_MASK      _U_(0xC2)    /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */
+
+/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x2C) (R/W 32) DPLL Ratio Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t LDR:12;           /*!< bit:  0..11  Loop Divider Ratio                 */
+    uint32_t :4;               /*!< bit: 12..15  Reserved                           */
+    uint32_t LDRFRAC:4;        /*!< bit: 16..19  Loop Divider Ratio Fractional Part */
+    uint32_t :12;              /*!< bit: 20..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_DPLLRATIO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLRATIO_OFFSET    0x2C         /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */
+#define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
+
+#define OSCCTRL_DPLLRATIO_LDR_Pos   0            /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */
+#define OSCCTRL_DPLLRATIO_LDR_Msk   (_U_(0xFFF) << OSCCTRL_DPLLRATIO_LDR_Pos)
+#define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
+#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16           /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
+#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0xF) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)
+#define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
+#define OSCCTRL_DPLLRATIO_MASK      _U_(0x000F0FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */
+
+/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x30) (R/W 32) Digital Core Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t FILTER:2;         /*!< bit:  0.. 1  Proportional Integral Filter Selection */
+    uint32_t LPEN:1;           /*!< bit:      2  Low-Power Enable                   */
+    uint32_t WUF:1;            /*!< bit:      3  Wake Up Fast                       */
+    uint32_t REFCLK:2;         /*!< bit:  4.. 5  Reference Clock Selection          */
+    uint32_t :2;               /*!< bit:  6.. 7  Reserved                           */
+    uint32_t LTIME:3;          /*!< bit:  8..10  Lock Time                          */
+    uint32_t :1;               /*!< bit:     11  Reserved                           */
+    uint32_t LBYPASS:1;        /*!< bit:     12  Lock Bypass                        */
+    uint32_t :3;               /*!< bit: 13..15  Reserved                           */
+    uint32_t DIV:11;           /*!< bit: 16..26  Clock Divider                      */
+    uint32_t :5;               /*!< bit: 27..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} OSCCTRL_DPLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLCTRLB_OFFSET    0x30         /**< \brief (OSCCTRL_DPLLCTRLB offset) Digital Core Configuration */
+#define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) Digital Core Configuration */
+
+#define OSCCTRL_DPLLCTRLB_FILTER_Pos 0            /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
+#define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0x3) << OSCCTRL_DPLLCTRLB_FILTER_Pos)
+#define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
+#define OSCCTRL_DPLLCTRLB_LPEN_Pos  2            /**< \brief (OSCCTRL_DPLLCTRLB) Low-Power Enable */
+#define OSCCTRL_DPLLCTRLB_LPEN      (_U_(0x1) << OSCCTRL_DPLLCTRLB_LPEN_Pos)
+#define OSCCTRL_DPLLCTRLB_WUF_Pos   3            /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */
+#define OSCCTRL_DPLLCTRLB_WUF       (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK_Pos 4            /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */
+#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x3) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
+#define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
+#define OSCCTRL_DPLLCTRLB_LTIME_Pos 8            /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */
+#define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos)
+#define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
+#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 12           /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */
+#define OSCCTRL_DPLLCTRLB_LBYPASS   (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)
+#define OSCCTRL_DPLLCTRLB_DIV_Pos   16           /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */
+#define OSCCTRL_DPLLCTRLB_DIV_Msk   (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos)
+#define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
+#define OSCCTRL_DPLLCTRLB_MASK      _U_(0x07FF173F) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */
+
+/* -------- OSCCTRL_DPLLPRESC : (OSCCTRL Offset: 0x34) (R/W  8) DPLL Prescaler -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PRESC:2;          /*!< bit:  0.. 1  Output Clock Prescaler             */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSCCTRL_DPLLPRESC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLPRESC_OFFSET    0x34         /**< \brief (OSCCTRL_DPLLPRESC offset) DPLL Prescaler */
+#define OSCCTRL_DPLLPRESC_RESETVALUE _U_(0x00)    /**< \brief (OSCCTRL_DPLLPRESC reset_value) DPLL Prescaler */
+
+#define OSCCTRL_DPLLPRESC_PRESC_Pos 0            /**< \brief (OSCCTRL_DPLLPRESC) Output Clock Prescaler */
+#define OSCCTRL_DPLLPRESC_PRESC_Msk (_U_(0x3) << OSCCTRL_DPLLPRESC_PRESC_Pos)
+#define OSCCTRL_DPLLPRESC_PRESC(value) (OSCCTRL_DPLLPRESC_PRESC_Msk & ((value) << OSCCTRL_DPLLPRESC_PRESC_Pos))
+#define   OSCCTRL_DPLLPRESC_PRESC_DIV1_Val _U_(0x0)   /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 1 */
+#define   OSCCTRL_DPLLPRESC_PRESC_DIV2_Val _U_(0x1)   /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 2 */
+#define   OSCCTRL_DPLLPRESC_PRESC_DIV4_Val _U_(0x2)   /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 4 */
+#define OSCCTRL_DPLLPRESC_PRESC_DIV1 (OSCCTRL_DPLLPRESC_PRESC_DIV1_Val << OSCCTRL_DPLLPRESC_PRESC_Pos)
+#define OSCCTRL_DPLLPRESC_PRESC_DIV2 (OSCCTRL_DPLLPRESC_PRESC_DIV2_Val << OSCCTRL_DPLLPRESC_PRESC_Pos)
+#define OSCCTRL_DPLLPRESC_PRESC_DIV4 (OSCCTRL_DPLLPRESC_PRESC_DIV4_Val << OSCCTRL_DPLLPRESC_PRESC_Pos)
+#define OSCCTRL_DPLLPRESC_MASK      _U_(0x03)    /**< \brief (OSCCTRL_DPLLPRESC) MASK Register */
+
+/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x38) (R/   8) DPLL Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :1;               /*!< bit:      0  Reserved                           */
+    uint8_t  ENABLE:1;         /*!< bit:      1  DPLL Enable Synchronization Status */
+    uint8_t  DPLLRATIO:1;      /*!< bit:      2  DPLL Ratio Synchronization Status  */
+    uint8_t  DPLLPRESC:1;      /*!< bit:      3  DPLL Prescaler Synchronization Status */
+    uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSCCTRL_DPLLSYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x38         /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */
+#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00)    /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */
+
+#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1            /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */
+#define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)
+#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2            /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Ratio Synchronization Status */
+#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)
+#define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos 3            /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Prescaler Synchronization Status */
+#define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos)
+#define OSCCTRL_DPLLSYNCBUSY_MASK   _U_(0x0E)    /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */
+
+/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x3C) (R/   8) DPLL Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  LOCK:1;           /*!< bit:      0  DPLL Lock Status                   */
+    uint8_t  CLKRDY:1;         /*!< bit:      1  DPLL Clock Ready                   */
+    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} OSCCTRL_DPLLSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define OSCCTRL_DPLLSTATUS_OFFSET   0x3C         /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */
+#define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00)    /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */
+
+#define OSCCTRL_DPLLSTATUS_LOCK_Pos 0            /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */
+#define OSCCTRL_DPLLSTATUS_LOCK     (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos)
+#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1            /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */
+#define OSCCTRL_DPLLSTATUS_CLKRDY   (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)
+#define OSCCTRL_DPLLSTATUS_MASK     _U_(0x03)    /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */
+
+/** \brief OSCCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO OSCCTRL_INTENCLR_Type     INTENCLR;    /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+  __IO OSCCTRL_INTENSET_Type     INTENSET;    /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+  __IO OSCCTRL_INTFLAG_Type      INTFLAG;     /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+  __I  OSCCTRL_STATUS_Type       STATUS;      /**< \brief Offset: 0x0C (R/  32) Power and Clocks Status */
+  __IO OSCCTRL_XOSCCTRL_Type     XOSCCTRL;    /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
+       RoReg8                    Reserved1[0x2];
+  __IO OSCCTRL_OSC16MCTRL_Type   OSC16MCTRL;  /**< \brief Offset: 0x14 (R/W  8) 16MHz Internal Oscillator (OSC16M) Control */
+       RoReg8                    Reserved2[0x3];
+  __IO OSCCTRL_DFLLCTRL_Type     DFLLCTRL;    /**< \brief Offset: 0x18 (R/W 16) DFLL48M Control */
+       RoReg8                    Reserved3[0x2];
+  __IO OSCCTRL_DFLLVAL_Type      DFLLVAL;     /**< \brief Offset: 0x1C (R/W 32) DFLL48M Value */
+  __IO OSCCTRL_DFLLMUL_Type      DFLLMUL;     /**< \brief Offset: 0x20 (R/W 32) DFLL48M Multiplier */
+  __IO OSCCTRL_DFLLSYNC_Type     DFLLSYNC;    /**< \brief Offset: 0x24 (R/W  8) DFLL48M Synchronization */
+       RoReg8                    Reserved4[0x3];
+  __IO OSCCTRL_DPLLCTRLA_Type    DPLLCTRLA;   /**< \brief Offset: 0x28 (R/W  8) DPLL Control */
+       RoReg8                    Reserved5[0x3];
+  __IO OSCCTRL_DPLLRATIO_Type    DPLLRATIO;   /**< \brief Offset: 0x2C (R/W 32) DPLL Ratio Control */
+  __IO OSCCTRL_DPLLCTRLB_Type    DPLLCTRLB;   /**< \brief Offset: 0x30 (R/W 32) Digital Core Configuration */
+  __IO OSCCTRL_DPLLPRESC_Type    DPLLPRESC;   /**< \brief Offset: 0x34 (R/W  8) DPLL Prescaler */
+       RoReg8                    Reserved6[0x3];
+  __I  OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x38 (R/   8) DPLL Synchronization Busy */
+       RoReg8                    Reserved7[0x3];
+  __I  OSCCTRL_DPLLSTATUS_Type   DPLLSTATUS;  /**< \brief Offset: 0x3C (R/   8) DPLL Status */
+} Oscctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_OSCCTRL_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/pac.h

@@ -0,0 +1,604 @@
+/**
+ * \file
+ *
+ * \brief Component description for PAC
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_PAC_COMPONENT_
+#define _SAMR34_PAC_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PAC */
+/* ========================================================================== */
+/** \addtogroup SAMR34_PAC Peripheral Access Controller */
+/*@{*/
+
+#define PAC_U2120
+#define REV_PAC                     0x110
+
+/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PERID:16;         /*!< bit:  0..15  Peripheral identifier              */
+    uint32_t KEY:8;            /*!< bit: 16..23  Peripheral access control key      */
+    uint32_t :8;               /*!< bit: 24..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_WRCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WRCTRL_OFFSET           0x00         /**< \brief (PAC_WRCTRL offset) Write control */
+#define PAC_WRCTRL_RESETVALUE       _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */
+
+#define PAC_WRCTRL_PERID_Pos        0            /**< \brief (PAC_WRCTRL) Peripheral identifier */
+#define PAC_WRCTRL_PERID_Msk        (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)
+#define PAC_WRCTRL_PERID(value)     (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
+#define PAC_WRCTRL_KEY_Pos          16           /**< \brief (PAC_WRCTRL) Peripheral access control key */
+#define PAC_WRCTRL_KEY_Msk          (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY(value)       (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
+#define   PAC_WRCTRL_KEY_OFF_Val          _U_(0x0)   /**< \brief (PAC_WRCTRL) No action */
+#define   PAC_WRCTRL_KEY_CLR_Val          _U_(0x1)   /**< \brief (PAC_WRCTRL) Clear protection */
+#define   PAC_WRCTRL_KEY_SET_Val          _U_(0x2)   /**< \brief (PAC_WRCTRL) Set protection */
+#define   PAC_WRCTRL_KEY_SETLCK_Val       _U_(0x3)   /**< \brief (PAC_WRCTRL) Set and lock protection */
+#define PAC_WRCTRL_KEY_OFF          (PAC_WRCTRL_KEY_OFF_Val        << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_CLR          (PAC_WRCTRL_KEY_CLR_Val        << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_SET          (PAC_WRCTRL_KEY_SET_Val        << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_KEY_SETLCK       (PAC_WRCTRL_KEY_SETLCK_Val     << PAC_WRCTRL_KEY_Pos)
+#define PAC_WRCTRL_MASK             _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */
+
+/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W  8) Event control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ERREO:1;          /*!< bit:      0  Peripheral acess error event output */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_EVCTRL_OFFSET           0x04         /**< \brief (PAC_EVCTRL offset) Event control */
+#define PAC_EVCTRL_RESETVALUE       _U_(0x00)    /**< \brief (PAC_EVCTRL reset_value) Event control */
+
+#define PAC_EVCTRL_ERREO_Pos        0            /**< \brief (PAC_EVCTRL) Peripheral acess error event output */
+#define PAC_EVCTRL_ERREO            (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)
+#define PAC_EVCTRL_MASK             _U_(0x01)    /**< \brief (PAC_EVCTRL) MASK Register */
+
+/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W  8) Interrupt enable clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ERR:1;            /*!< bit:      0  Peripheral access error interrupt disable */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTENCLR_OFFSET         0x08         /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */
+#define PAC_INTENCLR_RESETVALUE     _U_(0x00)    /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */
+
+#define PAC_INTENCLR_ERR_Pos        0            /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */
+#define PAC_INTENCLR_ERR            (_U_(0x1) << PAC_INTENCLR_ERR_Pos)
+#define PAC_INTENCLR_MASK           _U_(0x01)    /**< \brief (PAC_INTENCLR) MASK Register */
+
+/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W  8) Interrupt enable set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  ERR:1;            /*!< bit:      0  Peripheral access error interrupt enable */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTENSET_OFFSET         0x09         /**< \brief (PAC_INTENSET offset) Interrupt enable set */
+#define PAC_INTENSET_RESETVALUE     _U_(0x00)    /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */
+
+#define PAC_INTENSET_ERR_Pos        0            /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */
+#define PAC_INTENSET_ERR            (_U_(0x1) << PAC_INTENSET_ERR_Pos)
+#define PAC_INTENSET_MASK           _U_(0x01)    /**< \brief (PAC_INTENSET) MASK Register */
+
+/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t FLASH_:1;         /*!< bit:      0  FLASH                              */
+    __I uint32_t HSRAMCM0P_:1;     /*!< bit:      1  HSRAMCM0P                          */
+    __I uint32_t HSRAMDSU_:1;      /*!< bit:      2  HSRAMDSU                           */
+    __I uint32_t HPB1_:1;          /*!< bit:      3  HPB1                               */
+    __I uint32_t H2LBRIDGES_:1;    /*!< bit:      4  H2LBRIDGES                         */
+    __I uint32_t :11;              /*!< bit:  5..15  Reserved                           */
+    __I uint32_t HPB0_:1;          /*!< bit:     16  HPB0                               */
+    __I uint32_t HPB2_:1;          /*!< bit:     17  HPB2                               */
+    __I uint32_t HPB3_:1;          /*!< bit:     18  HPB3                               */
+    __I uint32_t HPB4_:1;          /*!< bit:     19  HPB4                               */
+    __I uint32_t :1;               /*!< bit:     20  Reserved                           */
+    __I uint32_t LPRAMHS_:1;       /*!< bit:     21  LPRAMHS                            */
+    __I uint32_t LPRAMPICOP_:1;    /*!< bit:     22  LPRAMPICOP                         */
+    __I uint32_t LPRAMDMAC_:1;     /*!< bit:     23  LPRAMDMAC                          */
+    __I uint32_t L2HBRIDGES_:1;    /*!< bit:     24  L2HBRIDGES                         */
+    __I uint32_t HSRAMLP_:1;       /*!< bit:     25  HSRAMLP                            */
+    __I uint32_t :6;               /*!< bit: 26..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_INTFLAGAHB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGAHB_OFFSET       0x10         /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */
+#define PAC_INTFLAGAHB_RESETVALUE   _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */
+
+#define PAC_INTFLAGAHB_FLASH_Pos    0            /**< \brief (PAC_INTFLAGAHB) FLASH */
+#define PAC_INTFLAGAHB_FLASH        (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)
+#define PAC_INTFLAGAHB_HSRAMCM0P_Pos 1            /**< \brief (PAC_INTFLAGAHB) HSRAMCM0P */
+#define PAC_INTFLAGAHB_HSRAMCM0P    (_U_(0x1) << PAC_INTFLAGAHB_HSRAMCM0P_Pos)
+#define PAC_INTFLAGAHB_HSRAMDSU_Pos 2            /**< \brief (PAC_INTFLAGAHB) HSRAMDSU */
+#define PAC_INTFLAGAHB_HSRAMDSU     (_U_(0x1) << PAC_INTFLAGAHB_HSRAMDSU_Pos)
+#define PAC_INTFLAGAHB_HPB1_Pos     3            /**< \brief (PAC_INTFLAGAHB) HPB1 */
+#define PAC_INTFLAGAHB_HPB1         (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)
+#define PAC_INTFLAGAHB_H2LBRIDGES_Pos 4            /**< \brief (PAC_INTFLAGAHB) H2LBRIDGES */
+#define PAC_INTFLAGAHB_H2LBRIDGES   (_U_(0x1) << PAC_INTFLAGAHB_H2LBRIDGES_Pos)
+#define PAC_INTFLAGAHB_HPB0_Pos     16           /**< \brief (PAC_INTFLAGAHB) HPB0 */
+#define PAC_INTFLAGAHB_HPB0         (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)
+#define PAC_INTFLAGAHB_HPB2_Pos     17           /**< \brief (PAC_INTFLAGAHB) HPB2 */
+#define PAC_INTFLAGAHB_HPB2         (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)
+#define PAC_INTFLAGAHB_HPB3_Pos     18           /**< \brief (PAC_INTFLAGAHB) HPB3 */
+#define PAC_INTFLAGAHB_HPB3         (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos)
+#define PAC_INTFLAGAHB_HPB4_Pos     19           /**< \brief (PAC_INTFLAGAHB) HPB4 */
+#define PAC_INTFLAGAHB_HPB4         (_U_(0x1) << PAC_INTFLAGAHB_HPB4_Pos)
+#define PAC_INTFLAGAHB_LPRAMHS_Pos  21           /**< \brief (PAC_INTFLAGAHB) LPRAMHS */
+#define PAC_INTFLAGAHB_LPRAMHS      (_U_(0x1) << PAC_INTFLAGAHB_LPRAMHS_Pos)
+#define PAC_INTFLAGAHB_LPRAMPICOP_Pos 22           /**< \brief (PAC_INTFLAGAHB) LPRAMPICOP */
+#define PAC_INTFLAGAHB_LPRAMPICOP   (_U_(0x1) << PAC_INTFLAGAHB_LPRAMPICOP_Pos)
+#define PAC_INTFLAGAHB_LPRAMDMAC_Pos 23           /**< \brief (PAC_INTFLAGAHB) LPRAMDMAC */
+#define PAC_INTFLAGAHB_LPRAMDMAC    (_U_(0x1) << PAC_INTFLAGAHB_LPRAMDMAC_Pos)
+#define PAC_INTFLAGAHB_L2HBRIDGES_Pos 24           /**< \brief (PAC_INTFLAGAHB) L2HBRIDGES */
+#define PAC_INTFLAGAHB_L2HBRIDGES   (_U_(0x1) << PAC_INTFLAGAHB_L2HBRIDGES_Pos)
+#define PAC_INTFLAGAHB_HSRAMLP_Pos  25           /**< \brief (PAC_INTFLAGAHB) HSRAMLP */
+#define PAC_INTFLAGAHB_HSRAMLP      (_U_(0x1) << PAC_INTFLAGAHB_HSRAMLP_Pos)
+#define PAC_INTFLAGAHB_MASK         _U_(0x03EF001F) /**< \brief (PAC_INTFLAGAHB) MASK Register */
+
+/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t PM_:1;            /*!< bit:      0  PM                                 */
+    __I uint32_t MCLK_:1;          /*!< bit:      1  MCLK                               */
+    __I uint32_t RSTC_:1;          /*!< bit:      2  RSTC                               */
+    __I uint32_t OSCCTRL_:1;       /*!< bit:      3  OSCCTRL                            */
+    __I uint32_t OSC32KCTRL_:1;    /*!< bit:      4  OSC32KCTRL                         */
+    __I uint32_t SUPC_:1;          /*!< bit:      5  SUPC                               */
+    __I uint32_t GCLK_:1;          /*!< bit:      6  GCLK                               */
+    __I uint32_t WDT_:1;           /*!< bit:      7  WDT                                */
+    __I uint32_t RTC_:1;           /*!< bit:      8  RTC                                */
+    __I uint32_t EIC_:1;           /*!< bit:      9  EIC                                */
+    __I uint32_t PORT_:1;          /*!< bit:     10  PORT                               */
+    __I uint32_t TAL_:1;           /*!< bit:     11  TAL                                */
+    __I uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_INTFLAGA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGA_OFFSET         0x14         /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */
+#define PAC_INTFLAGA_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */
+
+#define PAC_INTFLAGA_PM_Pos         0            /**< \brief (PAC_INTFLAGA) PM */
+#define PAC_INTFLAGA_PM             (_U_(0x1) << PAC_INTFLAGA_PM_Pos)
+#define PAC_INTFLAGA_MCLK_Pos       1            /**< \brief (PAC_INTFLAGA) MCLK */
+#define PAC_INTFLAGA_MCLK           (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)
+#define PAC_INTFLAGA_RSTC_Pos       2            /**< \brief (PAC_INTFLAGA) RSTC */
+#define PAC_INTFLAGA_RSTC           (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)
+#define PAC_INTFLAGA_OSCCTRL_Pos    3            /**< \brief (PAC_INTFLAGA) OSCCTRL */
+#define PAC_INTFLAGA_OSCCTRL        (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)
+#define PAC_INTFLAGA_OSC32KCTRL_Pos 4            /**< \brief (PAC_INTFLAGA) OSC32KCTRL */
+#define PAC_INTFLAGA_OSC32KCTRL     (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)
+#define PAC_INTFLAGA_SUPC_Pos       5            /**< \brief (PAC_INTFLAGA) SUPC */
+#define PAC_INTFLAGA_SUPC           (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)
+#define PAC_INTFLAGA_GCLK_Pos       6            /**< \brief (PAC_INTFLAGA) GCLK */
+#define PAC_INTFLAGA_GCLK           (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)
+#define PAC_INTFLAGA_WDT_Pos        7            /**< \brief (PAC_INTFLAGA) WDT */
+#define PAC_INTFLAGA_WDT            (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)
+#define PAC_INTFLAGA_RTC_Pos        8            /**< \brief (PAC_INTFLAGA) RTC */
+#define PAC_INTFLAGA_RTC            (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)
+#define PAC_INTFLAGA_EIC_Pos        9            /**< \brief (PAC_INTFLAGA) EIC */
+#define PAC_INTFLAGA_EIC            (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)
+#define PAC_INTFLAGA_PORT_Pos       10           /**< \brief (PAC_INTFLAGA) PORT */
+#define PAC_INTFLAGA_PORT           (_U_(0x1) << PAC_INTFLAGA_PORT_Pos)
+#define PAC_INTFLAGA_TAL_Pos        11           /**< \brief (PAC_INTFLAGA) TAL */
+#define PAC_INTFLAGA_TAL            (_U_(0x1) << PAC_INTFLAGA_TAL_Pos)
+#define PAC_INTFLAGA_MASK           _U_(0x00000FFF) /**< \brief (PAC_INTFLAGA) MASK Register */
+
+/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t USB_:1;           /*!< bit:      0  USB                                */
+    __I uint32_t DSU_:1;           /*!< bit:      1  DSU                                */
+    __I uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL                            */
+    __I uint32_t MTB_:1;           /*!< bit:      3  MTB                                */
+    __I uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_INTFLAGB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGB_OFFSET         0x18         /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */
+#define PAC_INTFLAGB_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */
+
+#define PAC_INTFLAGB_USB_Pos        0            /**< \brief (PAC_INTFLAGB) USB */
+#define PAC_INTFLAGB_USB            (_U_(0x1) << PAC_INTFLAGB_USB_Pos)
+#define PAC_INTFLAGB_DSU_Pos        1            /**< \brief (PAC_INTFLAGB) DSU */
+#define PAC_INTFLAGB_DSU            (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)
+#define PAC_INTFLAGB_NVMCTRL_Pos    2            /**< \brief (PAC_INTFLAGB) NVMCTRL */
+#define PAC_INTFLAGB_NVMCTRL        (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)
+#define PAC_INTFLAGB_MTB_Pos        3            /**< \brief (PAC_INTFLAGB) MTB */
+#define PAC_INTFLAGB_MTB            (_U_(0x1) << PAC_INTFLAGB_MTB_Pos)
+#define PAC_INTFLAGB_MASK           _U_(0x0000000F) /**< \brief (PAC_INTFLAGB) MASK Register */
+
+/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t SERCOM0_:1;       /*!< bit:      0  SERCOM0                            */
+    __I uint32_t SERCOM1_:1;       /*!< bit:      1  SERCOM1                            */
+    __I uint32_t SERCOM2_:1;       /*!< bit:      2  SERCOM2                            */
+    __I uint32_t SERCOM3_:1;       /*!< bit:      3  SERCOM3                            */
+    __I uint32_t SERCOM4_:1;       /*!< bit:      4  SERCOM4                            */
+    __I uint32_t TCC0_:1;          /*!< bit:      5  TCC0                               */
+    __I uint32_t TCC1_:1;          /*!< bit:      6  TCC1                               */
+    __I uint32_t TCC2_:1;          /*!< bit:      7  TCC2                               */
+    __I uint32_t TC0_:1;           /*!< bit:      8  TC0                                */
+    __I uint32_t TC1_:1;           /*!< bit:      9  TC1                                */
+    __I uint32_t TC2_:1;           /*!< bit:     10  TC2                                */
+    __I uint32_t TC3_:1;           /*!< bit:     11  TC3                                */
+    __I uint32_t DAC_:1;           /*!< bit:     12  DAC                                */
+    __I uint32_t AES_:1;           /*!< bit:     13  AES                                */
+    __I uint32_t TRNG_:1;          /*!< bit:     14  TRNG                               */
+    __I uint32_t :17;              /*!< bit: 15..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_INTFLAGC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGC_OFFSET         0x1C         /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */
+#define PAC_INTFLAGC_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */
+
+#define PAC_INTFLAGC_SERCOM0_Pos    0            /**< \brief (PAC_INTFLAGC) SERCOM0 */
+#define PAC_INTFLAGC_SERCOM0        (_U_(0x1) << PAC_INTFLAGC_SERCOM0_Pos)
+#define PAC_INTFLAGC_SERCOM1_Pos    1            /**< \brief (PAC_INTFLAGC) SERCOM1 */
+#define PAC_INTFLAGC_SERCOM1        (_U_(0x1) << PAC_INTFLAGC_SERCOM1_Pos)
+#define PAC_INTFLAGC_SERCOM2_Pos    2            /**< \brief (PAC_INTFLAGC) SERCOM2 */
+#define PAC_INTFLAGC_SERCOM2        (_U_(0x1) << PAC_INTFLAGC_SERCOM2_Pos)
+#define PAC_INTFLAGC_SERCOM3_Pos    3            /**< \brief (PAC_INTFLAGC) SERCOM3 */
+#define PAC_INTFLAGC_SERCOM3        (_U_(0x1) << PAC_INTFLAGC_SERCOM3_Pos)
+#define PAC_INTFLAGC_SERCOM4_Pos    4            /**< \brief (PAC_INTFLAGC) SERCOM4 */
+#define PAC_INTFLAGC_SERCOM4        (_U_(0x1) << PAC_INTFLAGC_SERCOM4_Pos)
+#define PAC_INTFLAGC_TCC0_Pos       5            /**< \brief (PAC_INTFLAGC) TCC0 */
+#define PAC_INTFLAGC_TCC0           (_U_(0x1) << PAC_INTFLAGC_TCC0_Pos)
+#define PAC_INTFLAGC_TCC1_Pos       6            /**< \brief (PAC_INTFLAGC) TCC1 */
+#define PAC_INTFLAGC_TCC1           (_U_(0x1) << PAC_INTFLAGC_TCC1_Pos)
+#define PAC_INTFLAGC_TCC2_Pos       7            /**< \brief (PAC_INTFLAGC) TCC2 */
+#define PAC_INTFLAGC_TCC2           (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos)
+#define PAC_INTFLAGC_TC0_Pos        8            /**< \brief (PAC_INTFLAGC) TC0 */
+#define PAC_INTFLAGC_TC0            (_U_(0x1) << PAC_INTFLAGC_TC0_Pos)
+#define PAC_INTFLAGC_TC1_Pos        9            /**< \brief (PAC_INTFLAGC) TC1 */
+#define PAC_INTFLAGC_TC1            (_U_(0x1) << PAC_INTFLAGC_TC1_Pos)
+#define PAC_INTFLAGC_TC2_Pos        10           /**< \brief (PAC_INTFLAGC) TC2 */
+#define PAC_INTFLAGC_TC2            (_U_(0x1) << PAC_INTFLAGC_TC2_Pos)
+#define PAC_INTFLAGC_TC3_Pos        11           /**< \brief (PAC_INTFLAGC) TC3 */
+#define PAC_INTFLAGC_TC3            (_U_(0x1) << PAC_INTFLAGC_TC3_Pos)
+#define PAC_INTFLAGC_DAC_Pos        12           /**< \brief (PAC_INTFLAGC) DAC */
+#define PAC_INTFLAGC_DAC            (_U_(0x1) << PAC_INTFLAGC_DAC_Pos)
+#define PAC_INTFLAGC_AES_Pos        13           /**< \brief (PAC_INTFLAGC) AES */
+#define PAC_INTFLAGC_AES            (_U_(0x1) << PAC_INTFLAGC_AES_Pos)
+#define PAC_INTFLAGC_TRNG_Pos       14           /**< \brief (PAC_INTFLAGC) TRNG */
+#define PAC_INTFLAGC_TRNG           (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos)
+#define PAC_INTFLAGC_MASK           _U_(0x00007FFF) /**< \brief (PAC_INTFLAGC) MASK Register */
+
+/* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t EVSYS_:1;         /*!< bit:      0  EVSYS                              */
+    __I uint32_t SERCOM5_:1;       /*!< bit:      1  SERCOM5                            */
+    __I uint32_t TC4_:1;           /*!< bit:      2  TC4                                */
+    __I uint32_t ADC_:1;           /*!< bit:      3  ADC                                */
+    __I uint32_t AC_:1;            /*!< bit:      4  AC                                 */
+    __I uint32_t PTC_:1;           /*!< bit:      5  PTC                                */
+    __I uint32_t :1;               /*!< bit:      6  Reserved                           */
+    __I uint32_t CCL_:1;           /*!< bit:      7  CCL                                */
+    __I uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_INTFLAGD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGD_OFFSET         0x20         /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */
+#define PAC_INTFLAGD_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */
+
+#define PAC_INTFLAGD_EVSYS_Pos      0            /**< \brief (PAC_INTFLAGD) EVSYS */
+#define PAC_INTFLAGD_EVSYS          (_U_(0x1) << PAC_INTFLAGD_EVSYS_Pos)
+#define PAC_INTFLAGD_SERCOM5_Pos    1            /**< \brief (PAC_INTFLAGD) SERCOM5 */
+#define PAC_INTFLAGD_SERCOM5        (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos)
+#define PAC_INTFLAGD_TC4_Pos        2            /**< \brief (PAC_INTFLAGD) TC4 */
+#define PAC_INTFLAGD_TC4            (_U_(0x1) << PAC_INTFLAGD_TC4_Pos)
+#define PAC_INTFLAGD_ADC_Pos        3            /**< \brief (PAC_INTFLAGD) ADC */
+#define PAC_INTFLAGD_ADC            (_U_(0x1) << PAC_INTFLAGD_ADC_Pos)
+#define PAC_INTFLAGD_AC_Pos         4            /**< \brief (PAC_INTFLAGD) AC */
+#define PAC_INTFLAGD_AC             (_U_(0x1) << PAC_INTFLAGD_AC_Pos)
+#define PAC_INTFLAGD_PTC_Pos        5            /**< \brief (PAC_INTFLAGD) PTC */
+#define PAC_INTFLAGD_PTC            (_U_(0x1) << PAC_INTFLAGD_PTC_Pos)
+#define PAC_INTFLAGD_CCL_Pos        7            /**< \brief (PAC_INTFLAGD) CCL */
+#define PAC_INTFLAGD_CCL            (_U_(0x1) << PAC_INTFLAGD_CCL_Pos)
+#define PAC_INTFLAGD_MASK           _U_(0x000000BF) /**< \brief (PAC_INTFLAGD) MASK Register */
+
+/* -------- PAC_INTFLAGE : (PAC Offset: 0x24) (R/W 32) Peripheral interrupt flag status - Bridge E -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint32_t PAC_:1;           /*!< bit:      0  PAC                                */
+    __I uint32_t DMAC_:1;          /*!< bit:      1  DMAC                               */
+    __I uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_INTFLAGE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_INTFLAGE_OFFSET         0x24         /**< \brief (PAC_INTFLAGE offset) Peripheral interrupt flag status - Bridge E */
+#define PAC_INTFLAGE_RESETVALUE     _U_(0x00000000) /**< \brief (PAC_INTFLAGE reset_value) Peripheral interrupt flag status - Bridge E */
+
+#define PAC_INTFLAGE_PAC_Pos        0            /**< \brief (PAC_INTFLAGE) PAC */
+#define PAC_INTFLAGE_PAC            (_U_(0x1) << PAC_INTFLAGE_PAC_Pos)
+#define PAC_INTFLAGE_DMAC_Pos       1            /**< \brief (PAC_INTFLAGE) DMAC */
+#define PAC_INTFLAGE_DMAC           (_U_(0x1) << PAC_INTFLAGE_DMAC_Pos)
+#define PAC_INTFLAGE_MASK           _U_(0x00000003) /**< \brief (PAC_INTFLAGE) MASK Register */
+
+/* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/  32) Peripheral write protection status - Bridge A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PM_:1;            /*!< bit:      0  PM APB Protect Enable              */
+    uint32_t MCLK_:1;          /*!< bit:      1  MCLK APB Protect Enable            */
+    uint32_t RSTC_:1;          /*!< bit:      2  RSTC APB Protect Enable            */
+    uint32_t OSCCTRL_:1;       /*!< bit:      3  OSCCTRL APB Protect Enable         */
+    uint32_t OSC32KCTRL_:1;    /*!< bit:      4  OSC32KCTRL APB Protect Enable      */
+    uint32_t SUPC_:1;          /*!< bit:      5  SUPC APB Protect Enable            */
+    uint32_t GCLK_:1;          /*!< bit:      6  GCLK APB Protect Enable            */
+    uint32_t WDT_:1;           /*!< bit:      7  WDT APB Protect Enable             */
+    uint32_t RTC_:1;           /*!< bit:      8  RTC APB Protect Enable             */
+    uint32_t EIC_:1;           /*!< bit:      9  EIC APB Protect Enable             */
+    uint32_t PORT_:1;          /*!< bit:     10  PORT APB Protect Enable            */
+    uint32_t TAL_:1;           /*!< bit:     11  TAL APB Protect Enable             */
+    uint32_t :20;              /*!< bit: 12..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSA_OFFSET          0x34         /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */
+#define PAC_STATUSA_RESETVALUE      _U_(0x00003000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */
+
+#define PAC_STATUSA_PM_Pos          0            /**< \brief (PAC_STATUSA) PM APB Protect Enable */
+#define PAC_STATUSA_PM              (_U_(0x1) << PAC_STATUSA_PM_Pos)
+#define PAC_STATUSA_MCLK_Pos        1            /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */
+#define PAC_STATUSA_MCLK            (_U_(0x1) << PAC_STATUSA_MCLK_Pos)
+#define PAC_STATUSA_RSTC_Pos        2            /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */
+#define PAC_STATUSA_RSTC            (_U_(0x1) << PAC_STATUSA_RSTC_Pos)
+#define PAC_STATUSA_OSCCTRL_Pos     3            /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */
+#define PAC_STATUSA_OSCCTRL         (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)
+#define PAC_STATUSA_OSC32KCTRL_Pos  4            /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */
+#define PAC_STATUSA_OSC32KCTRL      (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)
+#define PAC_STATUSA_SUPC_Pos        5            /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */
+#define PAC_STATUSA_SUPC            (_U_(0x1) << PAC_STATUSA_SUPC_Pos)
+#define PAC_STATUSA_GCLK_Pos        6            /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */
+#define PAC_STATUSA_GCLK            (_U_(0x1) << PAC_STATUSA_GCLK_Pos)
+#define PAC_STATUSA_WDT_Pos         7            /**< \brief (PAC_STATUSA) WDT APB Protect Enable */
+#define PAC_STATUSA_WDT             (_U_(0x1) << PAC_STATUSA_WDT_Pos)
+#define PAC_STATUSA_RTC_Pos         8            /**< \brief (PAC_STATUSA) RTC APB Protect Enable */
+#define PAC_STATUSA_RTC             (_U_(0x1) << PAC_STATUSA_RTC_Pos)
+#define PAC_STATUSA_EIC_Pos         9            /**< \brief (PAC_STATUSA) EIC APB Protect Enable */
+#define PAC_STATUSA_EIC             (_U_(0x1) << PAC_STATUSA_EIC_Pos)
+#define PAC_STATUSA_PORT_Pos        10           /**< \brief (PAC_STATUSA) PORT APB Protect Enable */
+#define PAC_STATUSA_PORT            (_U_(0x1) << PAC_STATUSA_PORT_Pos)
+#define PAC_STATUSA_TAL_Pos         11           /**< \brief (PAC_STATUSA) TAL APB Protect Enable */
+#define PAC_STATUSA_TAL             (_U_(0x1) << PAC_STATUSA_TAL_Pos)
+#define PAC_STATUSA_MASK            _U_(0x00000FFF) /**< \brief (PAC_STATUSA) MASK Register */
+
+/* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/  32) Peripheral write protection status - Bridge B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t USB_:1;           /*!< bit:      0  USB APB Protect Enable             */
+    uint32_t DSU_:1;           /*!< bit:      1  DSU APB Protect Enable             */
+    uint32_t NVMCTRL_:1;       /*!< bit:      2  NVMCTRL APB Protect Enable         */
+    uint32_t MTB_:1;           /*!< bit:      3  MTB APB Protect Enable             */
+    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSB_OFFSET          0x38         /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */
+#define PAC_STATUSB_RESETVALUE      _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */
+
+#define PAC_STATUSB_USB_Pos         0            /**< \brief (PAC_STATUSB) USB APB Protect Enable */
+#define PAC_STATUSB_USB             (_U_(0x1) << PAC_STATUSB_USB_Pos)
+#define PAC_STATUSB_DSU_Pos         1            /**< \brief (PAC_STATUSB) DSU APB Protect Enable */
+#define PAC_STATUSB_DSU             (_U_(0x1) << PAC_STATUSB_DSU_Pos)
+#define PAC_STATUSB_NVMCTRL_Pos     2            /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */
+#define PAC_STATUSB_NVMCTRL         (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)
+#define PAC_STATUSB_MTB_Pos         3            /**< \brief (PAC_STATUSB) MTB APB Protect Enable */
+#define PAC_STATUSB_MTB             (_U_(0x1) << PAC_STATUSB_MTB_Pos)
+#define PAC_STATUSB_MASK            _U_(0x0000000F) /**< \brief (PAC_STATUSB) MASK Register */
+
+/* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/  32) Peripheral write protection status - Bridge C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SERCOM0_:1;       /*!< bit:      0  SERCOM0 APB Protect Enable         */
+    uint32_t SERCOM1_:1;       /*!< bit:      1  SERCOM1 APB Protect Enable         */
+    uint32_t SERCOM2_:1;       /*!< bit:      2  SERCOM2 APB Protect Enable         */
+    uint32_t SERCOM3_:1;       /*!< bit:      3  SERCOM3 APB Protect Enable         */
+    uint32_t SERCOM4_:1;       /*!< bit:      4  SERCOM4 APB Protect Enable         */
+    uint32_t TCC0_:1;          /*!< bit:      5  TCC0 APB Protect Enable            */
+    uint32_t TCC1_:1;          /*!< bit:      6  TCC1 APB Protect Enable            */
+    uint32_t TCC2_:1;          /*!< bit:      7  TCC2 APB Protect Enable            */
+    uint32_t TC0_:1;           /*!< bit:      8  TC0 APB Protect Enable             */
+    uint32_t TC1_:1;           /*!< bit:      9  TC1 APB Protect Enable             */
+    uint32_t TC2_:1;           /*!< bit:     10  TC2 APB Protect Enable             */
+    uint32_t TC3_:1;           /*!< bit:     11  TC3 APB Protect Enable             */
+    uint32_t DAC_:1;           /*!< bit:     12  DAC APB Protect Enable             */
+    uint32_t AES_:1;           /*!< bit:     13  AES APB Protect Enable             */
+    uint32_t TRNG_:1;          /*!< bit:     14  TRNG APB Protect Enable            */
+    uint32_t :17;              /*!< bit: 15..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSC_OFFSET          0x3C         /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */
+#define PAC_STATUSC_RESETVALUE      _U_(0x00000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */
+
+#define PAC_STATUSC_SERCOM0_Pos     0            /**< \brief (PAC_STATUSC) SERCOM0 APB Protect Enable */
+#define PAC_STATUSC_SERCOM0         (_U_(0x1) << PAC_STATUSC_SERCOM0_Pos)
+#define PAC_STATUSC_SERCOM1_Pos     1            /**< \brief (PAC_STATUSC) SERCOM1 APB Protect Enable */
+#define PAC_STATUSC_SERCOM1         (_U_(0x1) << PAC_STATUSC_SERCOM1_Pos)
+#define PAC_STATUSC_SERCOM2_Pos     2            /**< \brief (PAC_STATUSC) SERCOM2 APB Protect Enable */
+#define PAC_STATUSC_SERCOM2         (_U_(0x1) << PAC_STATUSC_SERCOM2_Pos)
+#define PAC_STATUSC_SERCOM3_Pos     3            /**< \brief (PAC_STATUSC) SERCOM3 APB Protect Enable */
+#define PAC_STATUSC_SERCOM3         (_U_(0x1) << PAC_STATUSC_SERCOM3_Pos)
+#define PAC_STATUSC_SERCOM4_Pos     4            /**< \brief (PAC_STATUSC) SERCOM4 APB Protect Enable */
+#define PAC_STATUSC_SERCOM4         (_U_(0x1) << PAC_STATUSC_SERCOM4_Pos)
+#define PAC_STATUSC_TCC0_Pos        5            /**< \brief (PAC_STATUSC) TCC0 APB Protect Enable */
+#define PAC_STATUSC_TCC0            (_U_(0x1) << PAC_STATUSC_TCC0_Pos)
+#define PAC_STATUSC_TCC1_Pos        6            /**< \brief (PAC_STATUSC) TCC1 APB Protect Enable */
+#define PAC_STATUSC_TCC1            (_U_(0x1) << PAC_STATUSC_TCC1_Pos)
+#define PAC_STATUSC_TCC2_Pos        7            /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */
+#define PAC_STATUSC_TCC2            (_U_(0x1) << PAC_STATUSC_TCC2_Pos)
+#define PAC_STATUSC_TC0_Pos         8            /**< \brief (PAC_STATUSC) TC0 APB Protect Enable */
+#define PAC_STATUSC_TC0             (_U_(0x1) << PAC_STATUSC_TC0_Pos)
+#define PAC_STATUSC_TC1_Pos         9            /**< \brief (PAC_STATUSC) TC1 APB Protect Enable */
+#define PAC_STATUSC_TC1             (_U_(0x1) << PAC_STATUSC_TC1_Pos)
+#define PAC_STATUSC_TC2_Pos         10           /**< \brief (PAC_STATUSC) TC2 APB Protect Enable */
+#define PAC_STATUSC_TC2             (_U_(0x1) << PAC_STATUSC_TC2_Pos)
+#define PAC_STATUSC_TC3_Pos         11           /**< \brief (PAC_STATUSC) TC3 APB Protect Enable */
+#define PAC_STATUSC_TC3             (_U_(0x1) << PAC_STATUSC_TC3_Pos)
+#define PAC_STATUSC_DAC_Pos         12           /**< \brief (PAC_STATUSC) DAC APB Protect Enable */
+#define PAC_STATUSC_DAC             (_U_(0x1) << PAC_STATUSC_DAC_Pos)
+#define PAC_STATUSC_AES_Pos         13           /**< \brief (PAC_STATUSC) AES APB Protect Enable */
+#define PAC_STATUSC_AES             (_U_(0x1) << PAC_STATUSC_AES_Pos)
+#define PAC_STATUSC_TRNG_Pos        14           /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */
+#define PAC_STATUSC_TRNG            (_U_(0x1) << PAC_STATUSC_TRNG_Pos)
+#define PAC_STATUSC_MASK            _U_(0x00007FFF) /**< \brief (PAC_STATUSC) MASK Register */
+
+/* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/  32) Peripheral write protection status - Bridge D -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t EVSYS_:1;         /*!< bit:      0  EVSYS APB Protect Enable           */
+    uint32_t SERCOM5_:1;       /*!< bit:      1  SERCOM5 APB Protect Enable         */
+    uint32_t TC4_:1;           /*!< bit:      2  TC4 APB Protect Enable             */
+    uint32_t ADC_:1;           /*!< bit:      3  ADC APB Protect Enable             */
+    uint32_t AC_:1;            /*!< bit:      4  AC APB Protect Enable              */
+    uint32_t PTC_:1;           /*!< bit:      5  PTC APB Protect Enable             */
+    uint32_t :1;               /*!< bit:      6  Reserved                           */
+    uint32_t CCL_:1;           /*!< bit:      7  CCL APB Protect Enable             */
+    uint32_t :24;              /*!< bit:  8..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_STATUSD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSD_OFFSET          0x40         /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */
+#define PAC_STATUSD_RESETVALUE      _U_(0x00000000) /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */
+
+#define PAC_STATUSD_EVSYS_Pos       0            /**< \brief (PAC_STATUSD) EVSYS APB Protect Enable */
+#define PAC_STATUSD_EVSYS           (_U_(0x1) << PAC_STATUSD_EVSYS_Pos)
+#define PAC_STATUSD_SERCOM5_Pos     1            /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */
+#define PAC_STATUSD_SERCOM5         (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos)
+#define PAC_STATUSD_TC4_Pos         2            /**< \brief (PAC_STATUSD) TC4 APB Protect Enable */
+#define PAC_STATUSD_TC4             (_U_(0x1) << PAC_STATUSD_TC4_Pos)
+#define PAC_STATUSD_ADC_Pos         3            /**< \brief (PAC_STATUSD) ADC APB Protect Enable */
+#define PAC_STATUSD_ADC             (_U_(0x1) << PAC_STATUSD_ADC_Pos)
+#define PAC_STATUSD_AC_Pos          4            /**< \brief (PAC_STATUSD) AC APB Protect Enable */
+#define PAC_STATUSD_AC              (_U_(0x1) << PAC_STATUSD_AC_Pos)
+#define PAC_STATUSD_PTC_Pos         5            /**< \brief (PAC_STATUSD) PTC APB Protect Enable */
+#define PAC_STATUSD_PTC             (_U_(0x1) << PAC_STATUSD_PTC_Pos)
+#define PAC_STATUSD_CCL_Pos         7            /**< \brief (PAC_STATUSD) CCL APB Protect Enable */
+#define PAC_STATUSD_CCL             (_U_(0x1) << PAC_STATUSD_CCL_Pos)
+#define PAC_STATUSD_MASK            _U_(0x000000BF) /**< \brief (PAC_STATUSD) MASK Register */
+
+/* -------- PAC_STATUSE : (PAC Offset: 0x44) (R/  32) Peripheral write protection status - Bridge E -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PAC_:1;           /*!< bit:      0  PAC APB Protect Enable             */
+    uint32_t DMAC_:1;          /*!< bit:      1  DMAC APB Protect Enable            */
+    uint32_t :30;              /*!< bit:  2..31  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PAC_STATUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_STATUSE_OFFSET          0x44         /**< \brief (PAC_STATUSE offset) Peripheral write protection status - Bridge E */
+#define PAC_STATUSE_RESETVALUE      _U_(0x00000000) /**< \brief (PAC_STATUSE reset_value) Peripheral write protection status - Bridge E */
+
+#define PAC_STATUSE_PAC_Pos         0            /**< \brief (PAC_STATUSE) PAC APB Protect Enable */
+#define PAC_STATUSE_PAC             (_U_(0x1) << PAC_STATUSE_PAC_Pos)
+#define PAC_STATUSE_DMAC_Pos        1            /**< \brief (PAC_STATUSE) DMAC APB Protect Enable */
+#define PAC_STATUSE_DMAC            (_U_(0x1) << PAC_STATUSE_DMAC_Pos)
+#define PAC_STATUSE_MASK            _U_(0x00000003) /**< \brief (PAC_STATUSE) MASK Register */
+
+/** \brief PAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PAC_WRCTRL_Type           WRCTRL;      /**< \brief Offset: 0x00 (R/W 32) Write control */
+  __IO PAC_EVCTRL_Type           EVCTRL;      /**< \brief Offset: 0x04 (R/W  8) Event control */
+       RoReg8                    Reserved1[0x3];
+  __IO PAC_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x08 (R/W  8) Interrupt enable clear */
+  __IO PAC_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x09 (R/W  8) Interrupt enable set */
+       RoReg8                    Reserved2[0x6];
+  __IO PAC_INTFLAGAHB_Type       INTFLAGAHB;  /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */
+  __IO PAC_INTFLAGA_Type         INTFLAGA;    /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */
+  __IO PAC_INTFLAGB_Type         INTFLAGB;    /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */
+  __IO PAC_INTFLAGC_Type         INTFLAGC;    /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */
+  __IO PAC_INTFLAGD_Type         INTFLAGD;    /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */
+  __IO PAC_INTFLAGE_Type         INTFLAGE;    /**< \brief Offset: 0x24 (R/W 32) Peripheral interrupt flag status - Bridge E */
+       RoReg8                    Reserved3[0xC];
+  __I  PAC_STATUSA_Type          STATUSA;     /**< \brief Offset: 0x34 (R/  32) Peripheral write protection status - Bridge A */
+  __I  PAC_STATUSB_Type          STATUSB;     /**< \brief Offset: 0x38 (R/  32) Peripheral write protection status - Bridge B */
+  __I  PAC_STATUSC_Type          STATUSC;     /**< \brief Offset: 0x3C (R/  32) Peripheral write protection status - Bridge C */
+  __I  PAC_STATUSD_Type          STATUSD;     /**< \brief Offset: 0x40 (R/  32) Peripheral write protection status - Bridge D */
+  __I  PAC_STATUSE_Type          STATUSE;     /**< \brief Offset: 0x44 (R/  32) Peripheral write protection status - Bridge E */
+} Pac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_PAC_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/pm.h

@@ -0,0 +1,277 @@
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_PM_COMPONENT_
+#define _SAMR34_PM_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAMR34_PM Power Manager */
+/*@{*/
+
+#define PM_U2240
+#define REV_PM                      0x102
+
+/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W  8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  :2;               /*!< bit:  0.. 1  Reserved                           */
+    uint8_t  IORET:1;          /*!< bit:      2  I/O Retention                      */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRLA_OFFSET             0x00         /**< \brief (PM_CTRLA offset) Control A */
+#define PM_CTRLA_RESETVALUE         _U_(0x00)    /**< \brief (PM_CTRLA reset_value) Control A */
+
+#define PM_CTRLA_IORET_Pos          2            /**< \brief (PM_CTRLA) I/O Retention */
+#define PM_CTRLA_IORET              (_U_(0x1) << PM_CTRLA_IORET_Pos)
+#define PM_CTRLA_MASK               _U_(0x04)    /**< \brief (PM_CTRLA) MASK Register */
+
+/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W  8) Sleep Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  SLEEPMODE:3;      /*!< bit:  0.. 2  Sleep Mode                         */
+    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_SLEEPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEPCFG_OFFSET          0x01         /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */
+#define PM_SLEEPCFG_RESETVALUE      _U_(0x02)    /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */
+
+#define PM_SLEEPCFG_SLEEPMODE_Pos   0            /**< \brief (PM_SLEEPCFG) Sleep Mode */
+#define PM_SLEEPCFG_SLEEPMODE_Msk   (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
+#define   PM_SLEEPCFG_SLEEPMODE_IDLE_Val  _U_(0x2)   /**< \brief (PM_SLEEPCFG) CPU, AHBx, and APBx clocks are OFF */
+#define   PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4)   /**< \brief (PM_SLEEPCFG) All Clocks are OFF */
+#define   PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x5)   /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */
+#define   PM_SLEEPCFG_SLEEPMODE_OFF_Val   _U_(0x6)   /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */
+#define PM_SLEEPCFG_SLEEPMODE_IDLE  (PM_SLEEPCFG_SLEEPMODE_IDLE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_SLEEPMODE_OFF   (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
+#define PM_SLEEPCFG_MASK            _U_(0x07)    /**< \brief (PM_SLEEPCFG) MASK Register */
+
+/* -------- PM_PLCFG : (PM Offset: 0x02) (R/W  8) Performance Level Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PLSEL:2;          /*!< bit:  0.. 1  Performance Level Select           */
+    uint8_t  :5;               /*!< bit:  2.. 6  Reserved                           */
+    uint8_t  PLDIS:1;          /*!< bit:      7  Performance Level Disable          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_PLCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_PLCFG_OFFSET             0x02         /**< \brief (PM_PLCFG offset) Performance Level Configuration */
+#define PM_PLCFG_RESETVALUE         _U_(0x00)    /**< \brief (PM_PLCFG reset_value) Performance Level Configuration */
+
+#define PM_PLCFG_PLSEL_Pos          0            /**< \brief (PM_PLCFG) Performance Level Select */
+#define PM_PLCFG_PLSEL_Msk          (_U_(0x3) << PM_PLCFG_PLSEL_Pos)
+#define PM_PLCFG_PLSEL(value)       (PM_PLCFG_PLSEL_Msk & ((value) << PM_PLCFG_PLSEL_Pos))
+#define   PM_PLCFG_PLSEL_PL0_Val          _U_(0x0)   /**< \brief (PM_PLCFG) Performance Level 0 */
+#define   PM_PLCFG_PLSEL_PL1_Val          _U_(0x1)   /**< \brief (PM_PLCFG) Performance Level 1 */
+#define   PM_PLCFG_PLSEL_PL2_Val          _U_(0x2)   /**< \brief (PM_PLCFG) Performance Level 2 */
+#define PM_PLCFG_PLSEL_PL0          (PM_PLCFG_PLSEL_PL0_Val        << PM_PLCFG_PLSEL_Pos)
+#define PM_PLCFG_PLSEL_PL1          (PM_PLCFG_PLSEL_PL1_Val        << PM_PLCFG_PLSEL_Pos)
+#define PM_PLCFG_PLSEL_PL2          (PM_PLCFG_PLSEL_PL2_Val        << PM_PLCFG_PLSEL_Pos)
+#define PM_PLCFG_PLDIS_Pos          7            /**< \brief (PM_PLCFG) Performance Level Disable */
+#define PM_PLCFG_PLDIS              (_U_(0x1) << PM_PLCFG_PLDIS_Pos)
+#define PM_PLCFG_MASK               _U_(0x83)    /**< \brief (PM_PLCFG) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W  8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PLRDY:1;          /*!< bit:      0  Performance Level Interrupt Enable */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET          0x04         /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE      _U_(0x00)    /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_PLRDY_Pos       0            /**< \brief (PM_INTENCLR) Performance Level Interrupt Enable */
+#define PM_INTENCLR_PLRDY           (_U_(0x1) << PM_INTENCLR_PLRDY_Pos)
+#define PM_INTENCLR_MASK            _U_(0x01)    /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W  8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PLRDY:1;          /*!< bit:      0  Performance Level Ready interrupt Enable */
+    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET          0x05         /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE      _U_(0x00)    /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_PLRDY_Pos       0            /**< \brief (PM_INTENSET) Performance Level Ready interrupt Enable */
+#define PM_INTENSET_PLRDY           (_U_(0x1) << PM_INTENSET_PLRDY_Pos)
+#define PM_INTENSET_MASK            _U_(0x01)    /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+  struct {
+    __I uint8_t  PLRDY:1;          /*!< bit:      0  Performance Level Ready            */
+    __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET           0x06         /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE       _U_(0x00)    /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_PLRDY_Pos        0            /**< \brief (PM_INTFLAG) Performance Level Ready */
+#define PM_INTFLAG_PLRDY            (_U_(0x1) << PM_INTFLAG_PLRDY_Pos)
+#define PM_INTFLAG_MASK             _U_(0x01)    /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 16) Standby Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint16_t PDCFG:2;          /*!< bit:  0.. 1  Power Domain Configuration         */
+    uint16_t :2;               /*!< bit:  2.. 3  Reserved                           */
+    uint16_t DPGPD0:1;         /*!< bit:      4  Dynamic Power Gating for PD0       */
+    uint16_t DPGPD1:1;         /*!< bit:      5  Dynamic Power Gating for PD1       */
+    uint16_t VREGSMOD:2;       /*!< bit:  6.. 7  Voltage Regulator Standby mode     */
+    uint16_t LINKPD:2;         /*!< bit:  8.. 9  Linked Power Domain                */
+    uint16_t BBIASHS:2;        /*!< bit: 10..11  Back Bias for HMCRAMCHS            */
+    uint16_t BBIASLP:2;        /*!< bit: 12..13  Back Bias for HMCRAMCLP            */
+    uint16_t BBIASPP:2;        /*!< bit: 14..15  Back Bias for PicoPram             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint16_t reg;                /*!< Type      used for register access              */
+} PM_STDBYCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_STDBYCFG_OFFSET          0x08         /**< \brief (PM_STDBYCFG offset) Standby Configuration */
+#define PM_STDBYCFG_RESETVALUE      _U_(0x0000)  /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */
+
+#define PM_STDBYCFG_PDCFG_Pos       0            /**< \brief (PM_STDBYCFG) Power Domain Configuration */
+#define PM_STDBYCFG_PDCFG_Msk       (_U_(0x3) << PM_STDBYCFG_PDCFG_Pos)
+#define PM_STDBYCFG_PDCFG(value)    (PM_STDBYCFG_PDCFG_Msk & ((value) << PM_STDBYCFG_PDCFG_Pos))
+#define   PM_STDBYCFG_PDCFG_DEFAULT_Val   _U_(0x0)   /**< \brief (PM_STDBYCFG) All power domains switching is handled by hardware. */
+#define   PM_STDBYCFG_PDCFG_PD0_Val       _U_(0x1)   /**< \brief (PM_STDBYCFG) PD0 is forced ACTIVE. PD1 and PD2 power domains switching is handled by hardware. */
+#define   PM_STDBYCFG_PDCFG_PD01_Val      _U_(0x2)   /**< \brief (PM_STDBYCFG) PD0 and PD1 are forced ACTIVE. PD2 power domain switching is handled by hardware. */
+#define   PM_STDBYCFG_PDCFG_PD012_Val     _U_(0x3)   /**< \brief (PM_STDBYCFG) All power domains are forced ACTIVE. */
+#define PM_STDBYCFG_PDCFG_DEFAULT   (PM_STDBYCFG_PDCFG_DEFAULT_Val << PM_STDBYCFG_PDCFG_Pos)
+#define PM_STDBYCFG_PDCFG_PD0       (PM_STDBYCFG_PDCFG_PD0_Val     << PM_STDBYCFG_PDCFG_Pos)
+#define PM_STDBYCFG_PDCFG_PD01      (PM_STDBYCFG_PDCFG_PD01_Val    << PM_STDBYCFG_PDCFG_Pos)
+#define PM_STDBYCFG_PDCFG_PD012     (PM_STDBYCFG_PDCFG_PD012_Val   << PM_STDBYCFG_PDCFG_Pos)
+#define PM_STDBYCFG_DPGPD0_Pos      4            /**< \brief (PM_STDBYCFG) Dynamic Power Gating for PD0 */
+#define PM_STDBYCFG_DPGPD0          (_U_(0x1) << PM_STDBYCFG_DPGPD0_Pos)
+#define PM_STDBYCFG_DPGPD1_Pos      5            /**< \brief (PM_STDBYCFG) Dynamic Power Gating for PD1 */
+#define PM_STDBYCFG_DPGPD1          (_U_(0x1) << PM_STDBYCFG_DPGPD1_Pos)
+#define PM_STDBYCFG_VREGSMOD_Pos    6            /**< \brief (PM_STDBYCFG) Voltage Regulator Standby mode */
+#define PM_STDBYCFG_VREGSMOD_Msk    (_U_(0x3) << PM_STDBYCFG_VREGSMOD_Pos)
+#define PM_STDBYCFG_VREGSMOD(value) (PM_STDBYCFG_VREGSMOD_Msk & ((value) << PM_STDBYCFG_VREGSMOD_Pos))
+#define   PM_STDBYCFG_VREGSMOD_AUTO_Val   _U_(0x0)   /**< \brief (PM_STDBYCFG) Automatic mode */
+#define   PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val _U_(0x1)   /**< \brief (PM_STDBYCFG) Performance oriented */
+#define   PM_STDBYCFG_VREGSMOD_LP_Val     _U_(0x2)   /**< \brief (PM_STDBYCFG) Low Power oriented */
+#define PM_STDBYCFG_VREGSMOD_AUTO   (PM_STDBYCFG_VREGSMOD_AUTO_Val << PM_STDBYCFG_VREGSMOD_Pos)
+#define PM_STDBYCFG_VREGSMOD_PERFORMANCE (PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val << PM_STDBYCFG_VREGSMOD_Pos)
+#define PM_STDBYCFG_VREGSMOD_LP     (PM_STDBYCFG_VREGSMOD_LP_Val   << PM_STDBYCFG_VREGSMOD_Pos)
+#define PM_STDBYCFG_LINKPD_Pos      8            /**< \brief (PM_STDBYCFG) Linked Power Domain */
+#define PM_STDBYCFG_LINKPD_Msk      (_U_(0x3) << PM_STDBYCFG_LINKPD_Pos)
+#define PM_STDBYCFG_LINKPD(value)   (PM_STDBYCFG_LINKPD_Msk & ((value) << PM_STDBYCFG_LINKPD_Pos))
+#define   PM_STDBYCFG_LINKPD_DEFAULT_Val  _U_(0x0)   /**< \brief (PM_STDBYCFG) Power domains are not linked */
+#define   PM_STDBYCFG_LINKPD_PD01_Val     _U_(0x1)   /**< \brief (PM_STDBYCFG) PD0 and PD1 power domains are linked */
+#define   PM_STDBYCFG_LINKPD_PD12_Val     _U_(0x2)   /**< \brief (PM_STDBYCFG) PD1 and PD2 power domains are linked */
+#define   PM_STDBYCFG_LINKPD_PD012_Val    _U_(0x3)   /**< \brief (PM_STDBYCFG) All power domains are linked */
+#define PM_STDBYCFG_LINKPD_DEFAULT  (PM_STDBYCFG_LINKPD_DEFAULT_Val << PM_STDBYCFG_LINKPD_Pos)
+#define PM_STDBYCFG_LINKPD_PD01     (PM_STDBYCFG_LINKPD_PD01_Val   << PM_STDBYCFG_LINKPD_Pos)
+#define PM_STDBYCFG_LINKPD_PD12     (PM_STDBYCFG_LINKPD_PD12_Val   << PM_STDBYCFG_LINKPD_Pos)
+#define PM_STDBYCFG_LINKPD_PD012    (PM_STDBYCFG_LINKPD_PD012_Val  << PM_STDBYCFG_LINKPD_Pos)
+#define PM_STDBYCFG_BBIASHS_Pos     10           /**< \brief (PM_STDBYCFG) Back Bias for HMCRAMCHS */
+#define PM_STDBYCFG_BBIASHS_Msk     (_U_(0x3) << PM_STDBYCFG_BBIASHS_Pos)
+#define PM_STDBYCFG_BBIASHS(value)  (PM_STDBYCFG_BBIASHS_Msk & ((value) << PM_STDBYCFG_BBIASHS_Pos))
+#define PM_STDBYCFG_BBIASLP_Pos     12           /**< \brief (PM_STDBYCFG) Back Bias for HMCRAMCLP */
+#define PM_STDBYCFG_BBIASLP_Msk     (_U_(0x3) << PM_STDBYCFG_BBIASLP_Pos)
+#define PM_STDBYCFG_BBIASLP(value)  (PM_STDBYCFG_BBIASLP_Msk & ((value) << PM_STDBYCFG_BBIASLP_Pos))
+#define PM_STDBYCFG_BBIASPP_Pos     14           /**< \brief (PM_STDBYCFG) Back Bias for PicoPram */
+#define PM_STDBYCFG_BBIASPP_Msk     (_U_(0x3) << PM_STDBYCFG_BBIASPP_Pos)
+#define PM_STDBYCFG_BBIASPP(value)  (PM_STDBYCFG_BBIASPP_Msk & ((value) << PM_STDBYCFG_BBIASPP_Pos))
+#define PM_STDBYCFG_MASK            _U_(0xFFF3)  /**< \brief (PM_STDBYCFG) MASK Register */
+
+/* -------- PM_PWSAKDLY : (PM Offset: 0x0C) (R/W  8) Power Switch Acknowledge Delay -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  DLYVAL:7;         /*!< bit:  0.. 6  Delay Value                        */
+    uint8_t  IGNACK:1;         /*!< bit:      7  Ignore Acknowledge                 */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PM_PWSAKDLY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_PWSAKDLY_OFFSET          0x0C         /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */
+#define PM_PWSAKDLY_RESETVALUE      _U_(0x00)    /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */
+
+#define PM_PWSAKDLY_DLYVAL_Pos      0            /**< \brief (PM_PWSAKDLY) Delay Value */
+#define PM_PWSAKDLY_DLYVAL_Msk      (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)
+#define PM_PWSAKDLY_DLYVAL(value)   (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
+#define PM_PWSAKDLY_IGNACK_Pos      7            /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */
+#define PM_PWSAKDLY_IGNACK          (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)
+#define PM_PWSAKDLY_MASK            _U_(0xFF)    /**< \brief (PM_PWSAKDLY) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PM_CTRLA_Type             CTRLA;       /**< \brief Offset: 0x00 (R/W  8) Control A */
+  __IO PM_SLEEPCFG_Type          SLEEPCFG;    /**< \brief Offset: 0x01 (R/W  8) Sleep Configuration */
+  __IO PM_PLCFG_Type             PLCFG;       /**< \brief Offset: 0x02 (R/W  8) Performance Level Configuration */
+       RoReg8                    Reserved1[0x1];
+  __IO PM_INTENCLR_Type          INTENCLR;    /**< \brief Offset: 0x04 (R/W  8) Interrupt Enable Clear */
+  __IO PM_INTENSET_Type          INTENSET;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Set */
+  __IO PM_INTFLAG_Type           INTFLAG;     /**< \brief Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
+       RoReg8                    Reserved2[0x1];
+  __IO PM_STDBYCFG_Type          STDBYCFG;    /**< \brief Offset: 0x08 (R/W 16) Standby Configuration */
+       RoReg8                    Reserved3[0x2];
+  __IO PM_PWSAKDLY_Type          PWSAKDLY;    /**< \brief Offset: 0x0C (R/W  8) Power Switch Acknowledge Delay */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_PM_COMPONENT_ */

firmware/SendcommCmdsys/src/ASF/sam0/utils/cmsis/samr34/include/component/port.h

@@ -0,0 +1,406 @@
+/**
+ * \file
+ *
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMR34_PORT_COMPONENT_
+#define _SAMR34_PORT_COMPONENT_
+
+/* ========================================================================== */
+/**  SOFTWARE API DEFINITION FOR PORT */
+/* ========================================================================== */
+/** \addtogroup SAMR34_PORT Port Module */
+/*@{*/
+
+#define PORT_U2210
+#define REV_PORT                    0x201
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIR:32;           /*!< bit:  0..31  Port Data Direction                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIR_OFFSET             0x00         /**< \brief (PORT_DIR offset) Data Direction */
+#define PORT_DIR_RESETVALUE         _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */
+
+#define PORT_DIR_DIR_Pos            0            /**< \brief (PORT_DIR) Port Data Direction */
+#define PORT_DIR_DIR_Msk            (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
+#define PORT_DIR_DIR(value)         (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
+#define PORT_DIR_MASK               _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRCLR:32;        /*!< bit:  0..31  Port Data Direction Clear          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRCLR_OFFSET          0x04         /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
+#define PORT_DIRCLR_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
+
+#define PORT_DIRCLR_DIRCLR_Pos      0            /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
+#define PORT_DIRCLR_DIRCLR_Msk      (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
+#define PORT_DIRCLR_DIRCLR(value)   (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
+#define PORT_DIRCLR_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRSET:32;        /*!< bit:  0..31  Port Data Direction Set            */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRSET_OFFSET          0x08         /**< \brief (PORT_DIRSET offset) Data Direction Set */
+#define PORT_DIRSET_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
+
+#define PORT_DIRSET_DIRSET_Pos      0            /**< \brief (PORT_DIRSET) Port Data Direction Set */
+#define PORT_DIRSET_DIRSET_Msk      (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
+#define PORT_DIRSET_DIRSET(value)   (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
+#define PORT_DIRSET_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t DIRTGL:32;        /*!< bit:  0..31  Port Data Direction Toggle         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_DIRTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRTGL_OFFSET          0x0C         /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
+#define PORT_DIRTGL_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
+
+#define PORT_DIRTGL_DIRTGL_Pos      0            /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
+#define PORT_DIRTGL_DIRTGL_Msk      (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
+#define PORT_DIRTGL_DIRTGL(value)   (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
+#define PORT_DIRTGL_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUT:32;           /*!< bit:  0..31  Port Data Output Value             */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUT_OFFSET             0x10         /**< \brief (PORT_OUT offset) Data Output Value */
+#define PORT_OUT_RESETVALUE         _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */
+
+#define PORT_OUT_OUT_Pos            0            /**< \brief (PORT_OUT) Port Data Output Value */
+#define PORT_OUT_OUT_Msk            (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
+#define PORT_OUT_OUT(value)         (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
+#define PORT_OUT_MASK               _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTCLR:32;        /*!< bit:  0..31  Port Data Output Value Clear       */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTCLR_OFFSET          0x14         /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
+#define PORT_OUTCLR_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
+
+#define PORT_OUTCLR_OUTCLR_Pos      0            /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
+#define PORT_OUTCLR_OUTCLR_Msk      (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
+#define PORT_OUTCLR_OUTCLR(value)   (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
+#define PORT_OUTCLR_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTSET:32;        /*!< bit:  0..31  Port Data Output Value Set         */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTSET_OFFSET          0x18         /**< \brief (PORT_OUTSET offset) Data Output Value Set */
+#define PORT_OUTSET_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
+
+#define PORT_OUTSET_OUTSET_Pos      0            /**< \brief (PORT_OUTSET) Port Data Output Value Set */
+#define PORT_OUTSET_OUTSET_Msk      (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
+#define PORT_OUTSET_OUTSET(value)   (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
+#define PORT_OUTSET_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t OUTTGL:32;        /*!< bit:  0..31  Port Data Output Value Toggle      */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_OUTTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTTGL_OFFSET          0x1C         /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
+#define PORT_OUTTGL_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
+
+#define PORT_OUTTGL_OUTTGL_Pos      0            /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
+#define PORT_OUTTGL_OUTTGL_Msk      (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
+#define PORT_OUTTGL_OUTTGL(value)   (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
+#define PORT_OUTTGL_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */
+
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/  32) GROUP Data Input Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t IN:32;            /*!< bit:  0..31  Port Data Input Value              */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_IN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_IN_OFFSET              0x20         /**< \brief (PORT_IN offset) Data Input Value */
+#define PORT_IN_RESETVALUE          _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */
+
+#define PORT_IN_IN_Pos              0            /**< \brief (PORT_IN) Port Data Input Value */
+#define PORT_IN_IN_Msk              (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)
+#define PORT_IN_IN(value)           (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
+#define PORT_IN_MASK                _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t SAMPLING:32;      /*!< bit:  0..31  Input Sampling Mode                */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_CTRL_OFFSET            0x24         /**< \brief (PORT_CTRL offset) Control */
+#define PORT_CTRL_RESETVALUE        _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */
+
+#define PORT_CTRL_SAMPLING_Pos      0            /**< \brief (PORT_CTRL) Input Sampling Mode */
+#define PORT_CTRL_SAMPLING_Msk      (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
+#define PORT_CTRL_SAMPLING(value)   (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
+#define PORT_CTRL_MASK              _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PINMASK:16;       /*!< bit:  0..15  Pin Mask for Multiple Pin Configuration */
+    uint32_t PMUXEN:1;         /*!< bit:     16  Select Peripheral Multiplexer      */
+    uint32_t INEN:1;           /*!< bit:     17  Input Enable                       */
+    uint32_t PULLEN:1;         /*!< bit:     18  Pull Enable                        */
+    uint32_t :3;               /*!< bit: 19..21  Reserved                           */
+    uint32_t DRVSTR:1;         /*!< bit:     22  Output Driver Strength Selection   */
+    uint32_t :1;               /*!< bit:     23  Reserved                           */
+    uint32_t PMUX:4;           /*!< bit: 24..27  Peripheral Multiplexing Template   */
+    uint32_t WRPMUX:1;         /*!< bit:     28  Write PMUX Registers               */
+    uint32_t :1;               /*!< bit:     29  Reserved                           */
+    uint32_t WRPINCFG:1;       /*!< bit:     30  Write PINCFG Registers             */
+    uint32_t HWSEL:1;          /*!< bit:     31  Half-Word Select                   */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_WRCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_WRCONFIG_OFFSET        0x28         /**< \brief (PORT_WRCONFIG offset) Write Configuration */
+#define PORT_WRCONFIG_RESETVALUE    _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
+
+#define PORT_WRCONFIG_PINMASK_Pos   0            /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_Msk   (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
+#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
+#define PORT_WRCONFIG_PMUXEN_Pos    16           /**< \brief (PORT_WRCONFIG) Select Peripheral Multiplexer */
+#define PORT_WRCONFIG_PMUXEN        (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
+#define PORT_WRCONFIG_INEN_Pos      17           /**< \brief (PORT_WRCONFIG) Input Enable */
+#define PORT_WRCONFIG_INEN          (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
+#define PORT_WRCONFIG_PULLEN_Pos    18           /**< \brief (PORT_WRCONFIG) Pull Enable */
+#define PORT_WRCONFIG_PULLEN        (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
+#define PORT_WRCONFIG_DRVSTR_Pos    22           /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
+#define PORT_WRCONFIG_DRVSTR        (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
+#define PORT_WRCONFIG_PMUX_Pos      24           /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing Template */
+#define PORT_WRCONFIG_PMUX_Msk      (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
+#define PORT_WRCONFIG_PMUX(value)   (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
+#define PORT_WRCONFIG_WRPMUX_Pos    28           /**< \brief (PORT_WRCONFIG) Write PMUX Registers */
+#define PORT_WRCONFIG_WRPMUX        (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
+#define PORT_WRCONFIG_WRPINCFG_Pos  30           /**< \brief (PORT_WRCONFIG) Write PINCFG Registers */
+#define PORT_WRCONFIG_WRPINCFG      (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
+#define PORT_WRCONFIG_HWSEL_Pos     31           /**< \brief (PORT_WRCONFIG) Half-Word Select */
+#define PORT_WRCONFIG_HWSEL         (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
+#define PORT_WRCONFIG_MASK          _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */
+
+/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint32_t PID0:5;           /*!< bit:  0.. 4  Port Event Pin Identifier 0        */
+    uint32_t EVACT0:2;         /*!< bit:  5.. 6  Port Event Action 0                */
+    uint32_t PORTEI0:1;        /*!< bit:      7  Port Event Enable Input 0          */
+    uint32_t PID1:5;           /*!< bit:  8..12  Port Event Pin Identifier 1        */
+    uint32_t EVACT1:2;         /*!< bit: 13..14  Port Event Action 1                */
+    uint32_t PORTEI1:1;        /*!< bit:     15  Port Event Enable Input 1          */
+    uint32_t PID2:5;           /*!< bit: 16..20  Port Event Pin Identifier 2        */
+    uint32_t EVACT2:2;         /*!< bit: 21..22  Port Event Action 2                */
+    uint32_t PORTEI2:1;        /*!< bit:     23  Port Event Enable Input 2          */
+    uint32_t PID3:5;           /*!< bit: 24..28  Port Event Pin Identifier 3        */
+    uint32_t EVACT3:2;         /*!< bit: 29..30  Port Event Action 3                */
+    uint32_t PORTEI3:1;        /*!< bit:     31  Port Event Enable Input 3          */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint32_t reg;                /*!< Type      used for register access              */
+} PORT_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_EVCTRL_OFFSET          0x2C         /**< \brief (PORT_EVCTRL offset) Event Input Control */
+#define PORT_EVCTRL_RESETVALUE      _U_(0x00000000) /**< \brief (PORT_EVCTRL reset_value) Event Input Control */
+
+#define PORT_EVCTRL_PID0_Pos        0            /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 0 */
+#define PORT_EVCTRL_PID0_Msk        (_U_(0x1F) << PORT_EVCTRL_PID0_Pos)
+#define PORT_EVCTRL_PID0(value)     (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
+#define PORT_EVCTRL_EVACT0_Pos      5            /**< \brief (PORT_EVCTRL) Port Event Action 0 */
+#define PORT_EVCTRL_EVACT0_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos)
+#define PORT_EVCTRL_EVACT0(value)   (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
+#define PORT_EVCTRL_PORTEI0_Pos     7            /**< \brief (PORT_EVCTRL) Port Event Enable Input 0 */
+#define PORT_EVCTRL_PORTEI0         (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos)
+#define PORT_EVCTRL_PID1_Pos        8            /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 1 */
+#define PORT_EVCTRL_PID1_Msk        (_U_(0x1F) << PORT_EVCTRL_PID1_Pos)
+#define PORT_EVCTRL_PID1(value)     (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
+#define PORT_EVCTRL_EVACT1_Pos      13           /**< \brief (PORT_EVCTRL) Port Event Action 1 */
+#define PORT_EVCTRL_EVACT1_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos)
+#define PORT_EVCTRL_EVACT1(value)   (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
+#define PORT_EVCTRL_PORTEI1_Pos     15           /**< \brief (PORT_EVCTRL) Port Event Enable Input 1 */
+#define PORT_EVCTRL_PORTEI1         (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos)
+#define PORT_EVCTRL_PID2_Pos        16           /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 2 */
+#define PORT_EVCTRL_PID2_Msk        (_U_(0x1F) << PORT_EVCTRL_PID2_Pos)
+#define PORT_EVCTRL_PID2(value)     (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
+#define PORT_EVCTRL_EVACT2_Pos      21           /**< \brief (PORT_EVCTRL) Port Event Action 2 */
+#define PORT_EVCTRL_EVACT2_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos)
+#define PORT_EVCTRL_EVACT2(value)   (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
+#define PORT_EVCTRL_PORTEI2_Pos     23           /**< \brief (PORT_EVCTRL) Port Event Enable Input 2 */
+#define PORT_EVCTRL_PORTEI2         (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos)
+#define PORT_EVCTRL_PID3_Pos        24           /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 3 */
+#define PORT_EVCTRL_PID3_Msk        (_U_(0x1F) << PORT_EVCTRL_PID3_Pos)
+#define PORT_EVCTRL_PID3(value)     (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
+#define PORT_EVCTRL_EVACT3_Pos      29           /**< \brief (PORT_EVCTRL) Port Event Action 3 */
+#define PORT_EVCTRL_EVACT3_Msk      (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos)
+#define PORT_EVCTRL_EVACT3(value)   (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
+#define PORT_EVCTRL_PORTEI3_Pos     31           /**< \brief (PORT_EVCTRL) Port Event Enable Input 3 */
+#define PORT_EVCTRL_PORTEI3         (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos)
+#define PORT_EVCTRL_MASK            _U_(0xFFFFFFFF) /**< \brief (PORT_EVCTRL) MASK Register */
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W  8) GROUP Peripheral Multiplexing n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXE:4;          /*!< bit:  0.. 3  Peripheral Multiplexing for Even-Numbered Pin */
+    uint8_t  PMUXO:4;          /*!< bit:  4.. 7  Peripheral Multiplexing for Odd-Numbered Pin */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PMUX_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PMUX_OFFSET            0x30         /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
+#define PORT_PMUX_RESETVALUE        _U_(0x00)    /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
+
+#define PORT_PMUX_PMUXE_Pos         0            /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */
+#define PORT_PMUX_PMUXE_Msk         (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE(value)      (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
+#define PORT_PMUX_PMUXO_Pos         4            /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */
+#define PORT_PMUX_PMUXO_Msk         (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO(value)      (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
+#define PORT_PMUX_MASK              _U_(0xFF)    /**< \brief (PORT_PMUX) MASK Register */
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W  8) GROUP Pin Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+  struct {
+    uint8_t  PMUXEN:1;         /*!< bit:      0  Select Peripheral Multiplexer      */
+    uint8_t  INEN:1;           /*!< bit:      1  Input Enable                       */
+    uint8_t  PULLEN:1;         /*!< bit:      2  Pull Enable                        */
+    uint8_t  :3;               /*!< bit:  3.. 5  Reserved                           */
+    uint8_t  DRVSTR:1;         /*!< bit:      6  Output Driver Strength Selection   */
+    uint8_t  :1;               /*!< bit:      7  Reserved                           */
+  } bit;                       /*!< Structure used for bit  access                  */
+  uint8_t reg;                 /*!< Type      used for register access              */
+} PORT_PINCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PINCFG_OFFSET          0x40         /**< \brief (PORT_PINCFG offset) Pin Configuration n */
+#define PORT_PINCFG_RESETVALUE      _U_(0x00)    /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
+
+#define PORT_PINCFG_PMUXEN_Pos      0            /**< \brief (PORT_PINCFG) Select Peripheral Multiplexer */
+#define PORT_PINCFG_PMUXEN          (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
+#define PORT_PINCFG_INEN_Pos        1            /**< \brief (PORT_PINCFG) Input Enable */
+#define PORT_PINCFG_INEN            (_U_(0x1) << PORT_PINCFG_INEN_Pos)
+#define PORT_PINCFG_PULLEN_Pos      2            /**< \brief (PORT_PINCFG) Pull Enable */
+#define PORT_PINCFG_PULLEN          (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
+#define PORT_PINCFG_DRVSTR_Pos      6            /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR          (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
+#define PORT_PINCFG_MASK            _U_(0x47)    /**< \brief (PORT_PINCFG) MASK Register */
+
+/** \brief PortGroup hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+  __IO PORT_DIR_Type             DIR;         /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+  __IO PORT_DIRCLR_Type          DIRCLR;      /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+  __IO PORT_DIRSET_Type          DIRSET;      /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+  __IO PORT_DIRTGL_Type          DIRTGL;      /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+  __IO PORT_OUT_Type             OUT;         /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+  __IO PORT_OUTCLR_Type          OUTCLR;      /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+  __IO PORT_OUTSET_Type          OUTSET;      /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+  __IO PORT_OUTTGL_Type          OUTTGL;      /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+  __I  PORT_IN_Type              IN;          /**< \brief Offset: 0x20 (R/  32) Data Input Value */
+  __IO PORT_CTRL_Type            CTRL;        /**< \brief Offset: 0x24 (R/W 32) Control */
+  __O  PORT_WRCONFIG_Type        WRCONFIG;    /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+  __IO PORT_EVCTRL_Type          EVCTRL;      /**< \brief Offset: 0x2C (R/W 32) Event Input Control */
+  __IO PORT_PMUX_Type            PMUX[16];    /**< \brief Offset: 0x30 (R/W  8) Peripheral Multiplexing n */
+  __IO PORT_PINCFG_Type          PINCFG[32];  /**< \brief Offset: 0x40 (R/W  8) Pin Configuration n */
+       RoReg8                    Reserved1[0x20];
+} PortGroup;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief PORT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+       PortGroup                 Group[3];    /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+} Port;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMR34_PORT_COMPONENT_ */