To foster research and exploration, test points TP5 and TP6 break out the clock and data of the controller's interintegrated circuit (I²C) with copper traces that cross antennas’ keep out areas.
Steps to reproduce
Refer to the layout are of AE1 and AE5
Locate traces between test points and SCL/SDA
Expected result
Copper traces do not cross antenna keep out areas.
Actual result
TP5 and TP6 connect to traces that cross AE1 and AE5.
Workaround
It is acceptable to temporarily keep the interference until higher efficiency in the on board antennas is needed more.
Severity level
This is low priority because project requirements do not mandate antenna choice.
# I²C testpoint traces cause interference
## Problem environment
To foster research and exploration, test points TP5 and TP6 break out the clock and data of the controller's interintegrated circuit (I²C) with copper traces that cross antennas' keep out areas.
## Steps to reproduce
1. Refer to the layout are of AE1 and AE5
1. Locate traces between test points and SCL/SDA
## Expected result
Copper traces do not cross antenna keep out areas.
## Actual result
TP5 and TP6 connect to traces that cross AE1 and AE5.
## Workaround
It is acceptable to temporarily keep the interference until higher efficiency in the on board antennas is needed more.
## Severity level
This is **low priority** because project requirements do not mandate antenna choice.
I²C testpoint traces cause interference
Problem environment
To foster research and exploration, test points TP5 and TP6 break out the clock and data of the controller's interintegrated circuit (I²C) with copper traces that cross antennas’ keep out areas.
Steps to reproduce
Expected result
Copper traces do not cross antenna keep out areas.
Actual result
TP5 and TP6 connect to traces that cross AE1 and AE5.
Workaround
It is acceptable to temporarily keep the interference until higher efficiency in the on board antennas is needed more.
Severity level
This is low priority because project requirements do not mandate antenna choice.