Chip programming occurs over SWD or JTAG interfaces which may support various serial debugging features such as daisy chaining.
Steps to reproduce
Refer to the schematic
Locate programming connectors
Examine for supported interfaces
Expected result
JTAG communication using TDI, TDO, TMS, TCK signals is supported.
Actual result
Only SWD communication using SWDCLK and SWDIO is supported.
Consequences
Because a full JTAG interface is required for daisy chaining, multiple hardware debuggers are needed to properly design a test jig.
Workaround
Integrate multiple hardware debuggers and connect them with USB interfaces.
Severity level
This is low priority because project requirements do not mandate a debugging interface.
# JTAG connection is incomplete
## Problem environment
Chip programming occurs over SWD or JTAG interfaces which may support various serial debugging features such as daisy chaining.
## Steps to reproduce
1. Refer to the schematic
1. Locate programming connectors
1. Examine for supported interfaces
## Expected result
JTAG communication using TDI, TDO, TMS, TCK signals is supported.
## Actual result
Only SWD communication using SWDCLK and SWDIO is supported.
## Consequences
Because a full JTAG interface is required for daisy chaining, multiple hardware debuggers are needed to properly design a test jig.
## Workaround
Integrate multiple hardware debuggers and connect them with USB interfaces.
## Severity level
This is **low priority** because project requirements do not mandate a debugging interface.
Michael Schloh von Bennewitz
ha añadido esto al hito Target platform regression testinghace 4 años '
issues.change_milestone_at=`modificó el hito de %!s(MISSING) a %!s(MISSING) %!s(MISSING)
JTAG connection is incomplete
Problem environment
Chip programming occurs over SWD or JTAG interfaces which may support various serial debugging features such as daisy chaining.
Steps to reproduce
Expected result
JTAG communication using TDI, TDO, TMS, TCK signals is supported.
Actual result
Only SWD communication using SWDCLK and SWDIO is supported.
Consequences
Because a full JTAG interface is required for daisy chaining, multiple hardware debuggers are needed to properly design a test jig.
Workaround
Integrate multiple hardware debuggers and connect them with USB interfaces.
Severity level
This is low priority because project requirements do not mandate a debugging interface.
There is little chance of routing traces to the extra JTAG contacts within current resource levels.