The schematic is a hierarchical nest of logic blocks, which is only partially abstracted.
Steps to reproduce
Observe pages in the schematic diagram
Consider mapping of blocks to pages
Expected result
Nested blocks are logically mapped to schematic circuits.
Actual result
Some schematic circuits are not correctly abstracted.
Severity level
This is low priority because project requirements do not state a high degree of readability.
# Refactor schematic blocks
## Problem environment
The schematic is a hierarchical nest of logic blocks, which is only partially abstracted.
## Steps to reproduce
1. Observe pages in the schematic diagram
2. Consider mapping of blocks to pages
## Expected result
Nested blocks are logically mapped to schematic circuits.
## Actual result
Some schematic circuits are not correctly abstracted.
## Severity level
This is **low priority** because project requirements do not state a high degree of readability.
Refactor schematic blocks
Problem environment
The schematic is a hierarchical nest of logic blocks, which is only partially abstracted.
Steps to reproduce
Expected result
Nested blocks are logically mapped to schematic circuits.
Actual result
Some schematic circuits are not correctly abstracted.
Severity level
This is low priority because project requirements do not state a high degree of readability.
Abstraction is adequate after refactoring in
fc60477441.