Europalab Devices produces a LoRaWAN transmitting client node, specialised for higher research of actuator and sensor assisted IoT networks. https://dev.europalab.com/nlnet/20200000/
您最多选择25个主题 主题必须以字母或数字开头,可以包含连字符 (-),并且长度不得超过35个字符

116 行
2.6KB

  1. (kicad_pcb (version 20171130) (host pcbnew 5.1.5+dfsg1-2build2)
  2. (general
  3. (thickness 1.6)
  4. (drawings 0)
  5. (tracks 0)
  6. (zones 0)
  7. (modules 0)
  8. (nets 1)
  9. )
  10. (page A4)
  11. (title_block
  12. (title "Democratic Sendcomm")
  13. (date 2020-08-30)
  14. (rev 0.8.0)
  15. (company "Europalab Devices")
  16. (comment 1 "Copyright © 2020, Europalab Devices")
  17. (comment 2 "Fulfilling requirements of 201708018")
  18. (comment 3 "Pending quality assurance testing")
  19. (comment 4 "Release revision for manufacturing")
  20. )
  21. (layers
  22. (0 F.Cu signal)
  23. (31 B.Cu signal)
  24. (32 B.Adhes user)
  25. (33 F.Adhes user)
  26. (34 B.Paste user)
  27. (35 F.Paste user)
  28. (36 B.SilkS user)
  29. (37 F.SilkS user)
  30. (38 B.Mask user)
  31. (39 F.Mask user)
  32. (40 Dwgs.User user)
  33. (41 Cmts.User user)
  34. (42 Eco1.User user)
  35. (43 Eco2.User user)
  36. (44 Edge.Cuts user)
  37. (45 Margin user)
  38. (46 B.CrtYd user)
  39. (47 F.CrtYd user)
  40. (48 B.Fab user)
  41. (49 F.Fab user)
  42. )
  43. (setup
  44. (last_trace_width 0.25)
  45. (trace_clearance 0.2)
  46. (zone_clearance 0.508)
  47. (zone_45_only no)
  48. (trace_min 0.2)
  49. (via_size 0.8)
  50. (via_drill 0.4)
  51. (via_min_size 0.4)
  52. (via_min_drill 0.3)
  53. (uvia_size 0.3)
  54. (uvia_drill 0.1)
  55. (uvias_allowed no)
  56. (uvia_min_size 0.2)
  57. (uvia_min_drill 0.1)
  58. (edge_width 0.05)
  59. (segment_width 0.2)
  60. (pcb_text_width 0.3)
  61. (pcb_text_size 1.5 1.5)
  62. (mod_edge_width 0.12)
  63. (mod_text_size 1 1)
  64. (mod_text_width 0.15)
  65. (pad_size 1.524 1.524)
  66. (pad_drill 0.762)
  67. (pad_to_mask_clearance 0.051)
  68. (solder_mask_min_width 0.25)
  69. (aux_axis_origin 0 0)
  70. (visible_elements FFFFFF7F)
  71. (pcbplotparams
  72. (layerselection 0x010fc_ffffffff)
  73. (usegerberextensions false)
  74. (usegerberattributes false)
  75. (usegerberadvancedattributes false)
  76. (creategerberjobfile false)
  77. (excludeedgelayer true)
  78. (linewidth 0.100000)
  79. (plotframeref false)
  80. (viasonmask false)
  81. (mode 1)
  82. (useauxorigin false)
  83. (hpglpennumber 1)
  84. (hpglpenspeed 20)
  85. (hpglpendiameter 15.000000)
  86. (psnegative false)
  87. (psa4output false)
  88. (plotreference true)
  89. (plotvalue true)
  90. (plotinvisibletext false)
  91. (padsonsilk false)
  92. (subtractmaskfromsilk false)
  93. (outputformat 1)
  94. (mirror false)
  95. (drillshape 1)
  96. (scaleselection 1)
  97. (outputdirectory ""))
  98. )
  99. (net 0 "")
  100. (net_class Default "Dies ist die voreingestellte Netzklasse."
  101. (clearance 0.2)
  102. (trace_width 0.25)
  103. (via_dia 0.8)
  104. (via_drill 0.4)
  105. (uvia_dia 0.3)
  106. (uvia_drill 0.1)
  107. )
  108. )