 Michael Schloh von Bennewitz
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2efab65f8a
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Add nested part to allow either DFN or SOIC secure elements to be used.
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4 年前 |
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Michael Schloh von Bennewitz
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57d2b72b53
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Add test point loops and correct sized mounting holes.
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4 年前 |
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Michael Schloh von Bennewitz
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2a1cbb6ddb
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Add nested part to allow either DFN or SOIC EEPROMs to be used.
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4 年前 |
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Michael Schloh von Bennewitz
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69acaf3e33
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Add EEPROM, jumpers, and connector pending migration to hat format.
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4 年前 |
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Michael Schloh von Bennewitz
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54e8c2e73c
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Correct schematics after electric rules check results in warnings.
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4 年前 |
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Michael Schloh von Bennewitz
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37dbf8f109
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Adequately improve and clarify power circuit design for bug #12.
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4 年前 |
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Michael Schloh von Bennewitz
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fc60477441
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Correct poor abstraction bug #4 and generally complete Microchip circuits.
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4 年前 |
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Michael Schloh von Bennewitz
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ff52db338c
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Annotate symbols, correct power circuits, and assign footprints.
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4 年前 |
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Michael Schloh von Bennewitz
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c2b37009ee
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Add remaining circuits to almost complete minimum MCU application.
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4 年前 |
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Michael Schloh von Bennewitz
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202089cd61
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Complete draft design of RF switch for power amplifier and HF circuits.
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4 年前 |
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Michael Schloh von Bennewitz
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8731ecd254
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Create and add a SKY13373 RF switch with corresponding symbol and footprint.
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4 年前 |
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Michael Schloh von Bennewitz
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ea03063239
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Initialise schematic hierarchy and add nested blocks for controller logic.
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4 年前 |
