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dsendcomm
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  • e10cf0b (HEAD -> master) Import draft state of UART and USB bootloader firmware for #86/#186. by Michael Schloh von Bennewitz 2021-04-03 18:50:38 +0200
  • 917ee18 Merge branch 'master' of git.europalab.com:NLNetfound/dsendcomm by Michael Schloh von Bennewitz 2021-03-31 13:08:39 +0200
  • e42dceb Import mechanical engineering design files for packaging standoffs. by Michael Schloh von Bennewitz 2021-03-31 13:07:14 +0200
  • 28f686c test change by Sander Kukk 2021-03-19 13:57:47 +0200
  • 8a7168e Complete resolution of #172 by adding a bill of materials part entry. by Michael Schloh von Bennewitz 2021-03-03 09:33:16 +0100
  • 79bea93 Correct number sequence of parts from mistaken 00 indication at L1. by Michael Schloh von Bennewitz 2021-03-03 09:24:56 +0100
  • 9083169 Resolve #172 by adding a connector conformant with Qwiic and Stemma sensors. by Michael Schloh von Bennewitz 2021-03-03 00:11:12 +0100
  • 98fe39c Annotate EEPROM flashing procedure with optional erase operation first. by Michael Schloh von Bennewitz 2021-02-28 19:10:50 +0100
  • 0846cc8 Resize and reposition bottom layer SWD contacts to testjig standard header. by Michael Schloh von Bennewitz 2021-02-23 21:54:22 +0100
  • 7460617 Change from default (down) to pull up resistance, which may be better. by Michael Schloh von Bennewitz 2021-02-17 13:09:10 +0100
  • 5dd172c Resolve #182 by adding breakout circuits for GND and 3V3 to rail edges. by Michael Schloh von Bennewitz 2021-02-17 10:36:23 +0100
  • dd7d78a Mitigate radio regulation risk of wrong frequency use in hardcoded values. by Michael Schloh von Bennewitz 2021-02-16 17:00:21 +0100
  • 45b3467 Add standoff holes towards the middle of panels to allow more support. by Michael Schloh von Bennewitz 2021-02-16 15:50:49 +0100
  • a6ec05f Complete device tree fragment import and correct for flawed output level. by Michael Schloh von Bennewitz 2021-02-14 15:02:47 +0100
  • 0859e50 Resolve #173 by importing a device tree fragment and supporting logic. by Michael Schloh von Bennewitz 2021-02-14 15:01:09 +0100
  • 9ff259e Prepare to import a devtree fragment and new EEPROM logic for GPIO resets. by Michael Schloh von Bennewitz 2021-02-14 14:59:25 +0100
  • b079559 Increment date year numbers to correspond with the current year 2021. by Michael Schloh von Bennewitz 2021-02-13 15:57:40 +0100
  • 049fd1d Backport decrease of luminosity modification for D3/R40 power LED pair. by Michael Schloh von Bennewitz 2021-02-13 15:54:19 +0100
  • ea19d47 Increment identifiers to indicate the new year after the spring festival. by Michael Schloh von Bennewitz 2021-02-09 22:54:04 +0100
  • 4b34cb3 Fix false inclusion bug and decrudify poorly formatted source lines. by Michael Schloh von Bennewitz 2021-02-09 22:53:50 +0100
  • bb6402b Resolve #174 by replacing and modifying logic according to another model. by Michael Schloh von Bennewitz 2021-02-09 11:52:34 +0100
  • 2beb1f6 Resolve #175 by including recommended antenna models in the parts list. by Michael Schloh von Bennewitz 2021-02-09 10:20:53 +0100
  • fb799c1 Modify antenna modification text to at least include jumper numbers. by Michael Schloh von Bennewitz 2021-02-08 23:48:04 +0100
  • df1e548 Resolve #67 by reviewing parts in stock and editing a corresponding legend. by Michael Schloh von Bennewitz 2021-02-07 15:31:49 +0100
  • ef09d61 Replace 1K value with 2K4 for R40 to dim power indicator LED D3. by Michael Schloh von Bennewitz 2021-02-07 15:06:45 +0100
  • 66cc2e4 Remove paste on DNP R41, backout 8819d77 15/18pF, and correct placements. by Michael Schloh von Bennewitz 2021-02-07 14:30:12 +0100
  • b8fb9b9 Assign feeders and chiplist to nozzle matrix and deselect dev model parts. by Michael Schloh von Bennewitz 2021-02-04 22:54:11 +0100
  • b9f6f61 Add capacitor and inductor value modifications for integrated pi network. by Michael Schloh von Bennewitz 2021-02-04 22:53:02 +0100
  • d56f6cc Complete HSE adjustment specification of load capacitors in the parts list. by Michael Schloh von Bennewitz 2021-01-28 23:01:10 +0100
  • 8819d77 Resolve #123 by replacing C94 and C95 values with 18pF following analysis. by Michael Schloh von Bennewitz 2021-01-28 22:58:16 +0100
  • 4e84bae Modify second crystal load capacitance following spectrum analysis. by Michael Schloh von Bennewitz 2021-01-28 22:44:54 +0100
  • 39e7dba Configure the panel first chip positions and many feeder corrections. by Michael Schloh von Bennewitz 2021-01-25 17:52:30 +0100
  • ef19061 Consider the problem of false tag indexes when releasing past tense. by Michael Schloh von Bennewitz 2021-01-23 15:44:16 +0100
  • 76f8fc9 Partially resolve #55 by reducing vias and severed traces in the RF path. by Michael Schloh von Bennewitz 2021-01-23 15:38:41 +0100
  • af5147c (tag: REL_2) Correct superfluous placeholder entry (remaining after consolidation.) by Michael Schloh von Bennewitz 2021-01-23 11:23:15 +0100
  • 9f10c7d Configure the tape reel positions and their feed box mappings. by Michael Schloh von Bennewitz 2021-01-22 00:24:11 +0100
  • 89e932a Solve the problem causing a layout error (79794b0) in the part footprint. by Michael Schloh von Bennewitz 2021-01-21 12:26:30 +0100
  • 79794b0 Correct the mask clearance for the RF switch causing a paste problem. by Michael Schloh von Bennewitz 2021-01-21 11:38:34 +0100
  • 6341cce Adjust placement configuration to reflect ferrite bead consolidation. by Michael Schloh von Bennewitz 2021-01-21 00:22:51 +0100
  • 8c2fc04 Replace tape feeders and regenerate following ferrite bead consolidation. by Michael Schloh von Bennewitz 2021-01-21 00:07:59 +0100
  • bd529ef Modify and consolidate both ferrite beads according to manufacturer advice. by Michael Schloh von Bennewitz 2021-01-20 23:55:10 +0100
  • b91f6a0 Regenerate foil apertures to match panel corrections near J4 connector. by Michael Schloh von Bennewitz 2021-01-20 23:27:26 +0100
  • e308d27 Improve comment describing the backpowering function of FB2 and JP7. by Michael Schloh von Bennewitz 2021-01-19 12:38:02 +0100
  • 72c593b Recorrect format from PDF to Gerber RS-274X and repaint pour hatches. by Michael Schloh von Bennewitz 2021-01-19 00:10:28 +0100
  • 8e0ade7 Recorrect panelised format when plotting Gerber and Excellon archives. by Michael Schloh von Bennewitz 2021-01-19 00:08:53 +0100
  • b576aba Inform of imminent release and record revision numbers of releases. by Michael Schloh von Bennewitz 2021-01-19 00:06:05 +0100
  • 9da6387 Record a release engineering checklist for reasons of quality assurance. by Michael Schloh von Bennewitz 2021-01-19 00:04:24 +0100
  • 63af422 Reconfigure automated placer configuration pending release to manufacturing. by Michael Schloh von Bennewitz 2021-01-19 00:00:18 +0100
  • 88d7d21 Include layout plots in addition to schematic and parts list of type PDF. by Michael Schloh von Bennewitz 2021-01-18 23:59:06 +0100
  • 991ad27 Regenerate portable document format schematic capture for release. by Michael Schloh von Bennewitz 2021-01-18 23:57:58 +0100
  • e55d772 Modify SWDCLK route between programming connectors to satisfy fabricator. by Michael Schloh von Bennewitz 2021-01-18 23:55:59 +0100
  • daa7f7c Reconnect solderfield pads and satisfy board fabricator trace to hole. by Michael Schloh von Bennewitz 2021-01-18 23:54:22 +0100
  • 44f662e Correct the target output directory path to correspond with panels. by Michael Schloh von Bennewitz 2021-01-17 22:04:14 +0100
  • 9afc5ee Correct the target output directory path to correspond with foils. by Michael Schloh von Bennewitz 2021-01-17 22:00:51 +0100
  • 2287982 Improve descriptive text on prototype assembly frame top layer. by Michael Schloh von Bennewitz 2021-01-17 17:52:55 +0100
  • 659c316 Bump revision numbers, dates, and copyright pending release to manufacturing. by Michael Schloh von Bennewitz 2021-01-17 15:33:32 +0100
  • 409d07a Redesign panel and foil for board fabrication after adding via stiching. by Michael Schloh von Bennewitz 2021-01-17 14:51:58 +0100
  • a64db6a Make a intermediate commit to track the panel design with custom planes. by Michael Schloh von Bennewitz 2021-01-17 14:20:54 +0100
  • 68bb414 Add via stiching to more closely resemble the antenna datasheet reference. by Michael Schloh von Bennewitz 2021-01-17 13:53:54 +0100
  • 0904bbd Resolve #31 by adding via stiching to feed lines, pending RF tests. by Michael Schloh von Bennewitz 2021-01-17 13:48:57 +0100
  • d94aab0 Update to state of panel pending 0.9.4 release to board fabrication. by Michael Schloh von Bennewitz 2021-01-17 13:23:57 +0100
  • b3ffb6c Correct spelling of unique parts and regenerate portable document format. by Michael Schloh von Bennewitz 2021-01-17 13:02:50 +0100
  • a36d54c Update panel design pending release of 0.9.4 to board fabrication. by Michael Schloh von Bennewitz 2021-01-17 12:41:10 +0100
  • 234e679 Correct misaligned trace on board edge and oversized trace near cutout. by Michael Schloh von Bennewitz 2021-01-17 12:40:34 +0100
  • 12b319a Resolve #167 by including a EEPROM device tree entry for J3 pin 37. by Michael Schloh von Bennewitz 2021-01-17 12:37:57 +0100
  • 7e14a12 Include useful information relating to the temporary nature of paperclips. by Michael Schloh von Bennewitz 2021-01-17 12:37:36 +0100
  • e15611b Correct URL of the chip antenna to change sources due to inavailability. by Michael Schloh von Bennewitz 2021-01-16 23:23:44 +0100
  • 1dc2ba4 Add a portable document formatted generated bill archive for hard copy. by Michael Schloh von Bennewitz 2021-01-16 18:23:27 +0100
  • 35c3f2f Include the approximate revision number and rearrange header and footer. by Michael Schloh von Bennewitz 2021-01-16 18:22:24 +0100
  • c54941d Improve wording and allow cell span binding to view legend in foot row. by Michael Schloh von Bennewitz 2021-01-16 18:18:50 +0100
  • 0848ee3 Generate and annotate a new structured spreadsheet for the CSV source. by Michael Schloh von Bennewitz 2021-01-16 18:13:54 +0100
  • f36857e Reverse UFL and try to finish chip antenna and 50 ohm feed line traces. by Michael Schloh von Bennewitz 2021-01-16 18:11:04 +0100
  • 65aca19 Add missing entry of a Samtec FTSH THT connector for the J20 SWD footprint. by Michael Schloh von Bennewitz 2021-01-16 18:06:44 +0100
  • d8d2d02 Correct missing entry for line number two, by renumbering lines. by Michael Schloh von Bennewitz 2021-01-16 18:03:35 +0100
  • 80951d0 Integrate manufacturer advice from Johanson on AE5 corner placement. by Michael Schloh von Bennewitz 2021-01-16 02:34:28 +0100
  • c6ed8ea Reposition chip antenna to improve return loss at the target frequency. by Michael Schloh von Bennewitz 2021-01-15 23:00:31 +0100
  • 21a5e89 Correct recent tolerance configuration with redundant via diamters. by Michael Schloh von Bennewitz 2021-01-15 22:59:45 +0100
  • 95308f7 Set default track width, spacing, via size, and hole diameters suitably. by Michael Schloh von Bennewitz 2021-01-15 15:01:46 +0100
  • dce2fa3 Correct syntax errors, replace false identifiers, and remove unpopulations. by Michael Schloh von Bennewitz 2021-01-15 14:09:21 +0100
  • 1f3a516 Correct syntax error in parts list to avoid parsing errors. by Michael Schloh von Bennewitz 2021-01-15 13:40:13 +0100
  • 75ae0e5 Renumber tape feeder positions according to switch resistor consolidation. by Michael Schloh von Bennewitz 2021-01-15 13:35:23 +0100
  • 670ea5e Try a risky consolidation of switch circuits from 39 ohm series to 220. by Michael Schloh von Bennewitz 2021-01-15 13:32:43 +0100
  • 69e759d Renumber tape feeder position to correspond with #164 consolidation work. by Michael Schloh von Bennewitz 2021-01-15 13:03:03 +0100
  • 7d374fa Try to reach magic number of fourty seven tape feeders by consolidation. by Michael Schloh von Bennewitz 2021-01-15 13:02:32 +0100
  • 812a589 Regenerate schematic designs for use in RF analysis and consultation. by Michael Schloh von Bennewitz 2021-01-15 01:38:47 +0100
  • ca4f317 Update the automated placement configuration accordingly. by Michael Schloh von Bennewitz 2021-01-14 16:59:46 +0100
  • fb71af7 Resolve #160 by laboriously rerouting test point trace to an unsused pin. by Michael Schloh von Bennewitz 2021-01-14 16:51:44 +0100
  • 55b3621 Improve to partially accommodate #147 bus power to backpower a host. by Michael Schloh von Bennewitz 2021-01-14 16:02:55 +0100
  • 47cf21d Resolve #164 by consolidating most parts in the comment suggestion. by Michael Schloh von Bennewitz 2021-01-14 15:10:17 +0100
  • 731c5e9 Correct load capacitor values for LSE and modify HSE on assumptions. by Michael Schloh von Bennewitz 2021-01-14 15:05:36 +0100
  • bbe2fa3 Track feeder areas in use to contrast with DNP or derivative models. by Michael Schloh von Bennewitz 2021-01-14 13:42:06 +0100
  • 33ff357 Begin process of reducing unique part count by DNP identifying 0R. by Michael Schloh von Bennewitz 2021-01-14 13:41:00 +0100
  • c965b8a Adjust schematic labels, relabel D8 designator to D3, and regenerate layout. by Michael Schloh von Bennewitz 2021-01-14 12:05:34 +0100
  • bb1358e Try to resolve #161 and #162 mechanical engineering problems. by Michael Schloh von Bennewitz 2021-01-13 10:53:04 +0100
  • 9983967 Add a specifications based representation of a J-Link mini device. by Michael Schloh von Bennewitz 2021-01-12 15:52:01 +0100
  • 59b01f1 Resolve 155 by adding minimal but important extra notation for alternates. by Michael Schloh von Bennewitz 2021-01-12 01:46:00 +0100
  • a137ed3 Modify parts list according to recent diode and resistance corrections. by Michael Schloh von Bennewitz 2021-01-12 01:36:58 +0100
  • b810dbe Resolve #154 again by correcting the 2mm and 1,6mm mounting holes to 1,8mm. by Michael Schloh von Bennewitz 2021-01-12 01:26:32 +0100
  • a2fe5b3 Resolve #158 and #159 by balancing resistance values of light diodes. by Michael Schloh von Bennewitz 2021-01-12 00:54:52 +0100
  • 7d6f26e Improve placement of ground indicator symbol in the bottom silkscreen. by Michael Schloh von Bennewitz 2021-01-11 13:18:52 +0100