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ec0c1a0 Mostly complete the bill of materials, and prepare to order parts. by Michael Schloh von Bennewitz 2020-10-23 22:21:18 +0200
ec01c31 Replace PTS with KSC tactile switch type after testing quality in #43. by Michael Schloh von Bennewitz 2020-10-23 22:14:40 +0200
1697e52 Record an out of scope concept to integrate FOMU in design to bookmark. by Michael Schloh von Bennewitz 2020-10-22 10:36:16 +0200
6fb5a11 Remove leading zero character in single digit line numbers. by Michael Schloh von Bennewitz 2020-10-21 19:23:42 +0200
a4609e6 Correct flawed CSV syntax and information for the recent audio sensor. by Michael Schloh von Bennewitz 2020-10-21 19:16:35 +0200
9893372 Improve wording and make identifiers more descriptive and consistent. by Michael Schloh von Bennewitz 2020-10-21 19:09:49 +0200
5c4a108 Include a bill of materials for recently designed STM32WL architecture. by Michael Schloh von Bennewitz 2020-10-21 19:04:12 +0200
6c5b7f3 Commit overlooked file name change from previous renaming. by Michael Schloh von Bennewitz 2020-10-21 19:02:06 +0200
dde3d94 Add forgotten Raspberry Pi 40W female connector material information. by Michael Schloh von Bennewitz 2020-10-21 19:00:54 +0200
22eb0a2 Rename the bill of materials associated with Microchip SiP parts. by Michael Schloh von Bennewitz 2020-10-21 18:59:12 +0200
cd5e47e Integrate new audio level sensor library symbol and regenerate netlists. by Michael Schloh von Bennewitz 2020-10-21 18:47:52 +0200
6e8d767 Correct TSNP name, adjust crystal capacitors, and add an audio sensor. by Michael Schloh von Bennewitz 2020-10-21 18:42:17 +0200
7b4a5a9 Correct TSNP package name after adding corresponding footprint. by Michael Schloh von Bennewitz 2020-10-21 18:40:31 +0200
fa1bcf0 Add a Grove connector, audio level sensor, and remove a UART test point. by Michael Schloh von Bennewitz 2020-10-21 18:37:11 +0200
7435efc Add a library symbol for the soon to be added audio level sensor. by Michael Schloh von Bennewitz 2020-10-21 18:29:47 +0200
04a0c99 Add footprints and shaded models for soon to be added sensors. by Michael Schloh von Bennewitz 2020-10-21 18:27:13 +0200
166e5a0 Correct TSNP package name and adjust crystal capacitors accordingly. by Michael Schloh von Bennewitz 2020-10-21 18:20:17 +0200
f332c46 Correct serial connector library symbol for future compatability. by Michael Schloh von Bennewitz 2020-10-20 20:10:09 +0200
7e9d778 Bump version number pending layout engineering of STM32WL SiP migration. by Michael Schloh von Bennewitz 2020-10-20 18:22:10 +0200
9a36de6 Correct footprint related flaws in preparation for layout edition. by Michael Schloh von Bennewitz 2020-10-20 18:17:00 +0200
06be850 Renumber and bump version pending layout edition of ST SoC migration. by Michael Schloh von Bennewitz 2020-10-20 17:51:06 +0200
1f6ccf2 Improve placement of RF switch circuits by centering entire schematic. by Michael Schloh von Bennewitz 2020-10-20 17:49:47 +0200
f124b45 Correct flawed connector symbol in schematic for SiP architecture. by Michael Schloh von Bennewitz 2020-10-20 17:47:16 +0200
e1e0f5c Redesign for STM32WL SoC architecture, add features, and bump version. by Michael Schloh von Bennewitz 2020-10-20 17:39:00 +0200
b40d648 Add a comment collumn to accommodate do not place (DNP) parts. by Michael Schloh von Bennewitz 2020-10-05 22:28:46 +0200
494fcf4 Complete bill of materials for current prototype design revision 0.8.2. by Michael Schloh von Bennewitz 2020-10-05 11:39:54 +0200
cff2121 Add a paste layer to NPTH mounts to configure for foil apertures. by Michael Schloh von Bennewitz 2020-10-05 11:38:12 +0200
44bdd2e (tag: PRE_1) Bump hardware revision number pending release to manufacturing. by Michael Schloh von Bennewitz 2020-09-25 18:59:37 +0200
65fc253 Add panel support like mouse bite integrated tabs for panelisation. by Michael Schloh von Bennewitz 2020-09-25 18:59:07 +0200
5da94c3 Include a solderfield breadboard to support daughterboard development. by Michael Schloh von Bennewitz 2020-09-25 18:58:06 +0200
c0aa16f Resolve #35 add a board to board connector to prepare daughterboards. by Michael Schloh von Bennewitz 2020-09-25 18:35:39 +0200
f7c3988 Resolve #33 Align panel to Stencil8 by relocating mount holes slightly. by Michael Schloh von Bennewitz 2020-09-25 18:01:23 +0200
04d94df Avoid tracking manufacturing archives and selectively copy to releases. by Michael Schloh von Bennewitz 2020-09-25 17:50:48 +0200
0a3fb05 Resolve #21 publish a bill of materials, in draft without suppliers. by Michael Schloh von Bennewitz 2020-09-25 17:47:42 +0200
9ef3094 Resolve #32 include missing footprints by adding shaded models. by Michael Schloh von Bennewitz 2020-09-25 17:41:15 +0200
6c7b76d Bump hardware revision number pending milestone progress and test cycle. by Michael Schloh von Bennewitz 2020-09-25 17:36:55 +0200
d07d09c Increase parts count to 124, and connect all remaining circuits. by Michael Schloh von Bennewitz 2020-09-25 17:35:36 +0200
15d9f44 Regenerate the netlist after introducing solder jumpers for antennas. by Michael Schloh von Bennewitz 2020-09-25 17:34:45 +0200
b657eb2 Add solder switch symbols for use in new antenna decoupling from switch. by Michael Schloh von Bennewitz 2020-09-25 17:34:08 +0200
7229a08 Add solder jumpers to decouple antenna array from transceiver switch. by Michael Schloh von Bennewitz 2020-09-25 17:33:00 +0200
772f799 Connect power voltage and ground to bottom quarter of board parts. by Michael Schloh von Bennewitz 2020-09-23 23:49:41 +0200
b762320 Dump layout regeneration after trying to design new test points. by Michael Schloh von Bennewitz 2020-09-23 23:23:50 +0200
2fa32f8 Add test points to allow flexible postassembly prototype debugging. by Michael Schloh von Bennewitz 2020-09-23 23:22:58 +0200
4a6fe14 Apply copper pours to all layers with ground nets except on layer 3. by Michael Schloh von Bennewitz 2020-09-23 23:10:00 +0200
2aa746b Add logos to schematic, that unfortunately do not fit in the layout. by Michael Schloh von Bennewitz 2020-09-23 22:49:21 +0200
dc6f024 Remove pad to pad spacing tolerance error to almost completely correct. by Michael Schloh von Bennewitz 2020-09-23 22:28:19 +0200
4a041e9 Clean up vias, tracks, spacing, and remove redundant segments. by Michael Schloh von Bennewitz 2020-09-23 22:25:51 +0200
fe06fd4 Adjust track width, via drills, and annular rings to minimum specs. by Michael Schloh von Bennewitz 2020-09-23 22:23:35 +0200
50ca6fb Connect remaining USB data and UART data circuits for input output. by Michael Schloh von Bennewitz 2020-09-23 15:06:37 +0200
dca0d14 Correct flawed net in cross connected serial wire debug contacts. by Michael Schloh von Bennewitz 2020-09-23 02:10:04 +0200
7cadc14 Connect both LEDs to MCU pins for controlling user output. by Michael Schloh von Bennewitz 2020-09-23 01:46:28 +0200
b639be7 Complete draft revision of the radio frequency switch circuit. by Michael Schloh von Bennewitz 2020-09-23 01:04:02 +0200
2063328 Remove useless chip antenna which takes up more area than total size. by Michael Schloh von Bennewitz 2020-09-22 23:22:02 +0200
b1fa69d Replace coin cell battery holder and move crystal to make room. by Michael Schloh von Bennewitz 2020-09-22 23:20:24 +0200
6daad3b Complete most circuits pending layout of RF switch and passive arrays. by Michael Schloh von Bennewitz 2020-09-22 23:10:03 +0200
53362e2 Upload intermediate layout design with most decapsulation circuits. by Michael Schloh von Bennewitz 2020-09-21 23:52:00 +0200
8d28560 Tighten tolerances to highest four layer ENIG cheap fabrication capacity. by Michael Schloh von Bennewitz 2020-09-21 23:50:40 +0200
7519f8f Adjust ball pad clearance and solder mask aperature to allow sanity. by Michael Schloh von Bennewitz 2020-09-21 23:49:59 +0200
802ec1d Reflect corrections in power circuits and generally develop layout. by Michael Schloh von Bennewitz 2020-09-21 02:37:34 +0200
cc5a038 Correct power circuit in LED parts that require a power flag. by Michael Schloh von Bennewitz 2020-09-21 02:34:05 +0200
636ecc1 Correct flawed ground short in secure element authentication circuit. by Michael Schloh von Bennewitz 2020-09-21 02:30:26 +0200
8da9ab1 Correct electrical connection to chip and loop antenna symbol. by Michael Schloh von Bennewitz 2020-09-21 01:33:07 +0200
eedb5cd Improve mounting hole unit numbering by hand modifying identifiers. by Michael Schloh von Bennewitz 2020-09-21 00:49:02 +0200
2efab65 Add nested part to allow either DFN or SOIC secure elements to be used. by Michael Schloh von Bennewitz 2020-09-21 00:42:12 +0200
9364408 Correct footprint for Atmel secure element to comply with standards. by Michael Schloh von Bennewitz 2020-09-21 00:31:41 +0200
36323d0 Improve tab text and position of mouse bites pending part placements. by Michael Schloh von Bennewitz 2020-09-21 00:27:01 +0200
0d1eed7 Reduce and (prototype) panelise for format change from badge to hat. by Michael Schloh von Bennewitz 2020-09-21 00:22:57 +0200
57d2b72 Add test point loops and correct sized mounting holes. by Michael Schloh von Bennewitz 2020-09-21 00:18:32 +0200
2a1cbb6 Add nested part to allow either DFN or SOIC EEPROMs to be used. by Michael Schloh von Bennewitz 2020-09-20 22:56:50 +0200
b4e7cd3 Merge branch 'master' of git.europalab.com:NLNetfound/dsendcomm by Michael Schloh von Bennewitz 2020-09-20 22:00:36 +0200
f779b79 Adapt layers and tolerances to correspond with four layer qualities. by Michael Schloh von Bennewitz 2020-09-20 21:59:19 +0200
aea4480 Hide copper antenna surface underneath soldermask instead of plating it. by Michael Schloh von Bennewitz 2020-09-20 21:58:47 +0200
69acaf3 Add EEPROM, jumpers, and connector pending migration to hat format. by Michael Schloh von Bennewitz 2020-09-20 21:57:35 +0200
9bfa087 Add an explanation about why the project lacks software. by Michael Schloh von Bennewitz 2020-09-09 17:57:41 +0000
f562757 Initialise a explanation for the lack of project software. by Michael Schloh von Bennewitz 2020-09-09 19:48:32 +0200
54e8c2e Correct schematics after electric rules check results in warnings. by Michael Schloh von Bennewitz 2020-09-09 02:44:14 +0200
0b9e714 Update library cache to most recent changes and add forgotten netlist. by Michael Schloh von Bennewitz 2020-09-09 01:58:19 +0200
a88a134 Update existing schematics after modification and subsequent reannotation. by Michael Schloh von Bennewitz 2020-09-09 00:05:54 +0200
37dbf8f Adequately improve and clarify power circuit design for bug #12. by Michael Schloh von Bennewitz 2020-09-08 20:25:15 +0200
fc60477 Correct poor abstraction bug #4 and generally complete Microchip circuits. by Michael Schloh von Bennewitz 2020-09-08 19:58:03 +0200
33e82ab Add missing antenna footprints, in use during layout design. by Michael Schloh von Bennewitz 2020-09-08 19:52:11 +0200
4a307de Add LDO voltage regulator to step down from 5V (Host/USB) to 3V3. by Michael Schloh von Bennewitz 2020-09-07 16:26:47 +0200
d46e563 Add ECC authentication secure element for imminent schematic capture. by Michael Schloh von Bennewitz 2020-09-07 15:15:13 +0200
a71b05c Prepare for layout edition in BGA with corresponding traces and vias. by Michael Schloh von Bennewitz 2020-09-06 23:43:35 +0200
ff52db3 Annotate symbols, correct power circuits, and assign footprints. by Michael Schloh von Bennewitz 2020-09-06 23:43:05 +0200
c2b3700 Add remaining circuits to almost complete minimum MCU application. by Michael Schloh von Bennewitz 2020-09-06 00:54:40 +0200
202089c Complete draft design of RF switch for power amplifier and HF circuits. by Michael Schloh von Bennewitz 2020-09-05 21:04:35 +0200
8731ecd Create and add a SKY13373 RF switch with corresponding symbol and footprint. by Michael Schloh von Bennewitz 2020-09-05 17:55:44 +0200
ea03063 Initialise schematic hierarchy and add nested blocks for controller logic. by Michael Schloh von Bennewitz 2020-09-05 15:17:12 +0200
0b005a0 Add very small crystal oscillator needed for microcontroller operation. by Michael Schloh von Bennewitz 2020-09-05 14:40:39 +0200
65703b0 Import test plan including test cases and unit tests. by Michael Schloh von Bennewitz 2020-09-04 11:10:00 +0200
e7de86f Abstract static definitions out of source containing variable code. by Michael Schloh von Bennewitz 2020-09-04 11:08:16 +0200
1ff923c Improve wording of project description in main information. by Michael Schloh von Bennewitz 2020-09-04 11:07:08 +0200
1a467fc Include GPIO blink source file for boilerplate and correct project. by Michael Schloh von Bennewitz 2020-09-03 23:43:38 +0200
30a3c02 Import firmware and new Platform IO project with VSCode artifacts. by Michael Schloh von Bennewitz 2020-09-03 22:49:54 +0200
6076ee8 Indicate UHF tranceiver and power functions completing symbols. by Michael Schloh von Bennewitz 2020-09-03 19:59:34 +0200
425ff00 Add MCU part symbols and missing BGA footprint to project libraries. by Michael Schloh von Bennewitz 2020-09-03 16:58:11 +0200
a2807cc Correct title text delimiters in the project layout file. by Michael Schloh von Bennewitz 2020-08-30 20:44:42 +0200
41e5f09 Include more project boilerplate structure and library cache. by Michael Schloh von Bennewitz 2020-08-30 20:42:58 +0200
65161c2 Integrate local symbols and footprint libraries pending components. by Michael Schloh von Bennewitz 2020-08-30 20:27:58 +0200

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