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  • 12d95a2 Add a provisional (used in panelisation) frame design and solve #154. by Michael Schloh von Bennewitz 2021-01-11 13:13:33 +0100
  • 72d6589 Solve automation vision errors #145 by positioning and removing fiducials. by Michael Schloh von Bennewitz 2021-01-11 12:23:18 +0100
  • e64c25b Integrate new reset host interface, documented in #153 and 08e3618. by Michael Schloh von Bennewitz 2021-01-09 12:25:06 +0100
  • 08e3618 Route reset signal from controller chip to host, solving #153. by Michael Schloh von Bennewitz 2021-01-09 12:21:32 +0100
  • e684579 Remove partless entries corresponding with solder jumpers and annotate. by Michael Schloh von Bennewitz 2021-01-09 12:05:26 +0100
  • 062c71b Add a openocd(1) configuration, to enable user firmware programming. by Michael Schloh von Bennewitz 2021-01-09 11:25:55 +0100
  • 84c7614 Hack the horizontal J4 UART connector notation to accommodate an edge. by Michael Schloh von Bennewitz 2021-01-08 11:35:50 +0100
  • f790aa3 Reposition fiducials according to automation test results, and add FID6. by Michael Schloh von Bennewitz 2021-01-08 11:32:46 +0100
  • 7f64df9 Improve notations of programming connector headers avoiding JTAG. by Michael Schloh von Bennewitz 2021-01-08 11:20:37 +0100
  • 8c965b9 Modify tape feeder pick configuration to improve handling of parts. by Michael Schloh von Bennewitz 2021-01-07 16:00:03 +0100
  • 7af8ba9 Improve fiducial size, form, placement, and structure to resolve #145. by Michael Schloh von Bennewitz 2021-01-07 11:40:04 +0100
  • eb74067 Add test points for USB data quality assurance (especially type C.) by Michael Schloh von Bennewitz 2021-01-05 21:59:46 +0100
  • a2e7654 Remove MPLab Snap because it fails on all Opensource (GDB) applications. by Michael Schloh von Bennewitz 2021-01-05 21:26:35 +0100
  • c7e1804 Add MPLab Snap and STLink V3Mini devices as candidate programmers. by Michael Schloh von Bennewitz 2021-01-05 13:59:20 +0100
  • d6f0deb Increase track widths and reduce (sloppy) vias in RF paths to antennas. by Michael Schloh von Bennewitz 2021-01-05 00:27:20 +0100
  • 1aa5ae7 Provisionally added chip programmer dimensions and hole spacing. by Michael Schloh von Bennewitz 2021-01-04 17:20:49 +0100
  • 02bbb27 Remove paste from unpopulated chip antenna passive pads and clarify. by Michael Schloh von Bennewitz 2021-01-04 15:43:30 +0100
  • 50e65f2 Add mounting holes to the test jig and avoid upside down text in panels. by Michael Schloh von Bennewitz 2021-01-04 15:05:31 +0100
  • d8106eb Add structures and circuits to support forthcoming test jig construction. by Michael Schloh von Bennewitz 2021-01-04 13:25:21 +0100
  • 4f9180b Add configuration for a first revision of the education destined device. by Michael Schloh von Bennewitz 2021-01-03 14:45:22 +0100
  • fadea4c Add test, debug, and program files for hardware attached on top EEPROM. by Michael Schloh von Bennewitz 2021-01-03 14:44:02 +0100
  • 70ff0c7 Develop the placement configuration pending assembly of release 0.9.2. by Michael Schloh von Bennewitz 2021-01-02 17:23:52 +0100
  • 5a29587 Work on #141 by integrating pi networks to match impedence in antennas. by Michael Schloh von Bennewitz 2021-01-02 17:16:31 +0100
  • 7927ab7 (tag: REL_1) Roughly inform of the code complete and release status pending production. by Michael Schloh von Bennewitz 2020-12-31 16:10:02 +0100
  • fd8033c Import project samples to illustrate hardware features in ARM firmware; This addition resolves #111 and #112 and concludes milestone group 6. by Michael Schloh von Bennewitz 2020-12-31 15:55:21 +0100
  • 3b87055 Import a sample solution and corresponding logic pending project import. by Michael Schloh von Bennewitz 2020-12-31 15:54:08 +0100
  • b5efdcc Clear area pending integration of current set of firmware projects. by Michael Schloh von Bennewitz 2020-12-30 00:28:00 +0100
  • b3b668c Calibrate for tooling update to 0.9.2 and prepare for placments. by Michael Schloh von Bennewitz 2020-12-30 00:18:29 +0100
  • c42820d Update according to latest state of the SMT assembly lab toolset. by Michael Schloh von Bennewitz 2020-12-28 21:47:44 +0100
  • dfae213 Adjust label spacing slightly on designator text in the silkscreen. by Michael Schloh von Bennewitz 2020-12-28 21:47:06 +0100
  • c80ec05 Correct electronic design rules check results pending imminent release. by Michael Schloh von Bennewitz 2020-12-28 02:03:36 +0100
  • 035f934 Repour lost filled areas on all layers, forgotten in last commit. by Michael Schloh von Bennewitz 2020-12-28 00:56:57 +0100
  • e71589f Reshape and position the hack that silkscreen indicator bar. by Michael Schloh von Bennewitz 2020-12-28 00:55:44 +0100
  • 7d0f591 Add forgotten but used in layout replacement for cut holes a module. by Michael Schloh von Bennewitz 2020-12-28 00:37:04 +0100
  • 898da4f Regenerate portable document format schematic capture for update. by Michael Schloh von Bennewitz 2020-12-28 00:35:25 +0100
  • f143228 Selectively remove paste apertures and replace hole cuts with drills. by Michael Schloh von Bennewitz 2020-12-28 00:29:12 +0100
  • 8e9ea63 Generate and curate parts list, panel design, and stencil foil. by Michael Schloh von Bennewitz 2020-12-27 23:24:33 +0100
  • 3ba5b28 Add out of tree footprint module files for inclusion in manufacturing. by Michael Schloh von Bennewitz 2020-12-27 23:23:23 +0100
  • 9702fcf Improve name text of artist signature which was too long before. by Michael Schloh von Bennewitz 2020-12-27 23:19:21 +0100
  • 719e193 Add a 45mm large mousebite panel tab to accommodate enclosure hinges. by Michael Schloh von Bennewitz 2020-12-27 23:10:16 +0100
  • 9f370cd Annotate J5 and J20 according to their serial protocols in silkscreens. by Michael Schloh von Bennewitz 2020-12-27 20:02:59 +0100
  • 3dfc431 Mark the first JTAG SWD debug interface connector in the silkscreen. by Michael Schloh von Bennewitz 2020-12-27 19:29:05 +0100
  • 7d49528 Reflect information from bug reports #129 and #130 pending VNA tests. by Michael Schloh von Bennewitz 2020-12-27 19:04:58 +0100
  • f2ad7f7 Remove stray user drawing layer of a edge cut guidance horizontal bar. by Michael Schloh von Bennewitz 2020-12-27 19:04:05 +0100
  • f4a7a6c Bump version numbers pending panelisation and prepare to manufacture. by Michael Schloh von Bennewitz 2020-12-27 15:45:10 +0100
  • 4f3db6f Correct USB bus power circuit according to reference design and adjust. by Michael Schloh von Bennewitz 2020-12-27 14:54:25 +0100
  • 8eebf51 Adjust position of external display connection cutout on board bottom. by Michael Schloh von Bennewitz 2020-12-27 12:37:19 +0100
  • 6040ddc Add holes for hackfield, antenna legend, and correct enclosure hinges. by Michael Schloh von Bennewitz 2020-12-27 12:32:17 +0100
  • 5bf1b6c Refine calibration suggestion from 12pF to 15pF indicated by counter. by Michael Schloh von Bennewitz 2020-12-27 01:54:55 +0100
  • c4e91a8 Update parts list according to recent corrections in schematic capture. by Michael Schloh von Bennewitz 2020-12-27 01:39:06 +0100
  • 98b1e69 Correct version number as indicated in silkscreen text. by Michael Schloh von Bennewitz 2020-12-27 01:25:58 +0100
  • 1c8ea48 Implement design review suggestions to resolve #61 and #62. by Michael Schloh von Bennewitz 2020-12-27 00:59:07 +0100
  • 73a6ed9 Add a test point to allow LSE crystal output redirection to a MCU pin. by Michael Schloh von Bennewitz 2020-12-26 00:55:18 +0100
  • 95df659 Resolve #128 by rerouting bus power to PA07 F3 to bus test circuit. by Michael Schloh von Bennewitz 2020-12-25 21:17:14 +0100
  • e14d452 Calibrate crystal circuits by trial and error pending spectrum analysis. by Michael Schloh von Bennewitz 2020-12-25 19:53:31 +0100
  • 799c6fe Calibrate crystal circuits by trial and error pending spectrum analysis. by Michael Schloh von Bennewitz 2020-12-25 19:27:03 +0100
  • 1f2fe60 Connect pads from pogo pin test matrix to GND and 3V3 to future proof. by Michael Schloh von Bennewitz 2020-12-19 16:03:11 +0100
  • afa5216 Resolve #122 by removing AE7 and JP10 from the layout, and add a PWR LED. by Michael Schloh von Bennewitz 2020-12-16 14:41:18 +0100
  • d772d2f Resolve #83 after tests indicate MLS correctly supplies power from PA09. by Michael Schloh von Bennewitz 2020-12-14 12:32:08 +0100
  • a6fcbdf Resolve bug report #118 by replacing 10pF with 7pF load capacitors. by Michael Schloh von Bennewitz 2020-12-12 15:59:39 +0100
  • 8c6be81 (tag: DCHK_1) Update generated schematic output to correspond with current design. by Michael Schloh von Bennewitz 2020-12-09 11:18:08 +0100
  • 89c95b9 Bump hardware revision number pending tag for design review. by Michael Schloh von Bennewitz 2020-12-09 10:41:14 +0100
  • 8c114dd Correct optional PA14_XIN and PA15_XOUT external crystal floating pins. by Michael Schloh von Bennewitz 2020-12-08 18:35:18 +0100
  • 52eec91 Correct HSE circuit and remove JP26, add RFSW testpoints and text. by Michael Schloh von Bennewitz 2020-12-08 18:19:13 +0100
  • 7c358dd Resolve #114 by replacing flawed 27 pF value with 2,7 pF throughout. by Michael Schloh von Bennewitz 2020-12-08 11:24:39 +0100
  • 68066fe Include a portable document format rendition of the schematic. by Michael Schloh von Bennewitz 2020-12-08 10:26:31 +0100
  • b6cc593 Correct secure element model number to support easy TTN integration. by Michael Schloh von Bennewitz 2020-12-07 10:47:25 +0100
  • 819a415 Modify deprecated secure element model to new ATECC608B throughout. by Michael Schloh von Bennewitz 2020-12-07 10:39:22 +0100
  • f6764b5 Add top layer test points to connect with bottom layer solder grid. by Michael Schloh von Bennewitz 2020-12-03 13:29:02 +0100
  • b969424 Resolve #104 by removing unconnected vias from AE5 pad 1. by Michael Schloh von Bennewitz 2020-12-03 13:02:01 +0100
  • 40a2b21 Redevelop, correct corners, and add connections to format variants. by Michael Schloh von Bennewitz 2020-12-02 01:29:51 +0100
  • 060584f Complete milestone 'Blank FR4 design' for remaining device formats. by Michael Schloh von Bennewitz 2020-12-01 14:21:26 +0100
  • bb8473a (tag: PRE_2) Complete production grade panelisation and foil design for LPKF frames. by Michael Schloh von Bennewitz 2020-11-25 22:02:13 +0100
  • 6697d42 Correct misplaced designator text label rotated in the last commit. by Michael Schloh von Bennewitz 2020-11-25 21:56:29 +0100
  • 9a29ebf Resolve #97 by redesigning the QFN-12 footprint used for the U4 RF switch. by Michael Schloh von Bennewitz 2020-11-25 17:01:03 +0100
  • a2b3858 Add handwritten signature decorative text to bottom silkscreen. by Michael Schloh von Bennewitz 2020-11-25 00:06:26 +0100
  • b727e44 Resolve DRC errors and panelise irregular tabs for consistency. by Michael Schloh von Bennewitz 2020-11-24 21:39:00 +0100
  • 62e6e0b Regenerate and commit the netlist reflecting the power flag addition. by Michael Schloh von Bennewitz 2020-11-24 18:03:27 +0100
  • 0753ffa Resolve a false positive on ERC by adding a power flag to a supply input. by Michael Schloh von Bennewitz 2020-11-24 17:50:36 +0100
  • 73d2e45 Improve continuity of the ground plane of the top layer by adding a via. by Michael Schloh von Bennewitz 2020-11-24 01:56:43 +0100
  • dde5e9f Bump revision pending release to panelisation and imminent fabrication. by Michael Schloh von Bennewitz 2020-11-24 01:34:25 +0100
  • 7c2b89e Correct flawed U2 package size and bump revision pending release. by Michael Schloh von Bennewitz 2020-11-24 01:32:41 +0100
  • 3c10b07 Modify placement of J1 battery power selection jumper to improve access. by Michael Schloh von Bennewitz 2020-11-22 22:45:24 +0100
  • a66f58c Align placement of resistor at R3 to the existing resistor at R2. by Michael Schloh von Bennewitz 2020-11-22 22:38:06 +0100
  • 55a0f50 Resolve #71 by replacing the 0402 part with a same brand 0805 part. by Michael Schloh von Bennewitz 2020-11-22 22:24:18 +0100
  • 0d38f32 Reduce length of antenna selection jumper traces to improve signal. by Michael Schloh von Bennewitz 2020-11-22 19:09:43 +0100
  • 6969e8e Complete partially implemented RF switch power selection jumper. by Michael Schloh von Bennewitz 2020-11-22 18:38:21 +0100
  • 7da0bfb Connect spring contacts for daughterboard and add jumper to resolve #88. by Michael Schloh von Bennewitz 2020-11-22 03:03:35 +0100
  • b4f491a Add a ambient light sensor circuit and route to the MCU. by Michael Schloh von Bennewitz 2020-11-22 02:34:39 +0100
  • 06ee3e4 Resolve #80 and #89 by adding a 1 uF decoupling capacitor and connector. by Michael Schloh von Bennewitz 2020-11-22 01:35:45 +0100
  • 787e5fe Resolve #76 by replacing triangle solder jumper shapes with ovals. by Michael Schloh von Bennewitz 2020-11-21 20:37:16 +0100
  • 7e32c82 Resolve #75 by replacing header pin footprints with solder jumpers. by Michael Schloh von Bennewitz 2020-11-21 18:47:34 +0100
  • 8e36a89 Resolve #72 and #74 by rerouting traces, jumpers, and pads. by Michael Schloh von Bennewitz 2020-11-21 16:52:32 +0100
  • 5547c5c Correct bottom ground plane cohesion across island regions. by Michael Schloh von Bennewitz 2020-11-21 01:31:14 +0100
  • d1de14d Resolve #81 and #82 by replacing oscillator circuit and inductors. by Michael Schloh von Bennewitz 2020-11-21 01:11:27 +0100
  • fbd2c4d Include bottom layer positions for tool configuration and machine import. by Michael Schloh von Bennewitz 2020-11-04 17:19:34 +0100
  • be68447 Improve position of bottom layer silkscreen text for designators. by Michael Schloh von Bennewitz 2020-10-31 14:43:42 +0100
  • b568796 Include placer tooling configuration for forthcoming assembly step. by Michael Schloh von Bennewitz 2020-10-29 17:51:23 +0100
  • ae8846b Include positions for forthcoming tool configuration and machine import. by Michael Schloh von Bennewitz 2020-10-27 16:55:14 +0100
  • 3729b8a Work around reference design flaw #58 by replacing with a ferrite bead. by Michael Schloh von Bennewitz 2020-10-26 12:11:27 +0100