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12 Commits (5dd172c1c9aef176fea4cad0b9a373ca22c46dfc)

Author SHA1 Message Date
  Michael Schloh von Bennewitz 21a5e8909f Correct recent tolerance configuration with redundant via diamters. 4 years ago
  Michael Schloh von Bennewitz 95308f748c Set default track width, spacing, via size, and hole diameters suitably. 4 years ago
  Michael Schloh von Bennewitz d6f0deb432 Increase track widths and reduce (sloppy) vias in RF paths to antennas. 4 years ago
  Michael Schloh von Bennewitz 50e65f2bcb Add mounting holes to the test jig and avoid upside down text in panels. 4 years ago
  Michael Schloh von Bennewitz 898da4fa7c Regenerate portable document format schematic capture for update. 4 years ago
  Michael Schloh von Bennewitz 1c8ea4862a Implement design review suggestions to resolve #61 and #62. 4 years ago
  Michael Schloh von Bennewitz fe06fd495f Adjust track width, via drills, and annular rings to minimum specs. 4 years ago
  Michael Schloh von Bennewitz 8d28560c4e Tighten tolerances to highest four layer ENIG cheap fabrication capacity. 4 years ago
  Michael Schloh von Bennewitz f779b7999a Adapt layers and tolerances to correspond with four layer qualities. 4 years ago
  Michael Schloh von Bennewitz a71b05cc81 Prepare for layout edition in BGA with corresponding traces and vias. 4 years ago
  Michael Schloh von Bennewitz 41e5f095e8 Include more project boilerplate structure and library cache. 4 years ago
  Michael Schloh von Bennewitz 56dfb433cc Initialise hardware engineering for imminent schematic capture. 4 years ago