 Michael Schloh von Bennewitz
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659c316ae0
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Bump revision numbers, dates, and copyright pending release to manufacturing.
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4年前 |
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Michael Schloh von Bennewitz
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409d07abe1
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Redesign panel and foil for board fabrication after adding via stiching.
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4年前 |
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Michael Schloh von Bennewitz
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a64db6a94c
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Make a intermediate commit to track the panel design with custom planes.
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4年前 |
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Michael Schloh von Bennewitz
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68bb4141e3
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Add via stiching to more closely resemble the antenna datasheet reference.
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4年前 |
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Michael Schloh von Bennewitz
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0904bbdda6
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Resolve #31 by adding via stiching to feed lines, pending RF tests.
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4年前 |
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Michael Schloh von Bennewitz
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d94aab0e8a
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Update to state of panel pending 0.9.4 release to board fabrication.
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4年前 |
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Michael Schloh von Bennewitz
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b3ffb6c035
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Correct spelling of unique parts and regenerate portable document format.
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4年前 |
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Michael Schloh von Bennewitz
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a36d54c0dc
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Update panel design pending release of 0.9.4 to board fabrication.
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4年前 |
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Michael Schloh von Bennewitz
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234e679a69
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Correct misaligned trace on board edge and oversized trace near cutout.
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4年前 |
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Michael Schloh von Bennewitz
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e15611b3a7
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Correct URL of the chip antenna to change sources due to inavailability.
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4年前 |
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Michael Schloh von Bennewitz
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1dc2ba4803
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Add a portable document formatted generated bill archive for hard copy.
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4年前 |
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Michael Schloh von Bennewitz
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35c3f2f83d
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Include the approximate revision number and rearrange header and footer.
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4年前 |
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Michael Schloh von Bennewitz
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c54941d649
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Improve wording and allow cell span binding to view legend in foot row.
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4年前 |
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Michael Schloh von Bennewitz
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0848ee3d5d
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Generate and annotate a new structured spreadsheet for the CSV source.
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4年前 |
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Michael Schloh von Bennewitz
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f36857e49e
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Reverse UFL and try to finish chip antenna and 50 ohm feed line traces.
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4年前 |
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Michael Schloh von Bennewitz
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65aca19040
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Add missing entry of a Samtec FTSH THT connector for the J20 SWD footprint.
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4年前 |
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Michael Schloh von Bennewitz
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d8d2d02ef2
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Correct missing entry for line number two, by renumbering lines.
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4年前 |
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Michael Schloh von Bennewitz
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80951d020f
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Integrate manufacturer advice from Johanson on AE5 corner placement.
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4年前 |
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Michael Schloh von Bennewitz
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c6ed8ea5c8
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Reposition chip antenna to improve return loss at the target frequency.
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4年前 |
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Michael Schloh von Bennewitz
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21a5e8909f
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Correct recent tolerance configuration with redundant via diamters.
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4年前 |
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Michael Schloh von Bennewitz
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95308f748c
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Set default track width, spacing, via size, and hole diameters suitably.
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4年前 |
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Michael Schloh von Bennewitz
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dce2fa31e9
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Correct syntax errors, replace false identifiers, and remove unpopulations.
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4年前 |
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Michael Schloh von Bennewitz
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1f3a516c01
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Correct syntax error in parts list to avoid parsing errors.
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4年前 |
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Michael Schloh von Bennewitz
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75ae0e50b3
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Renumber tape feeder positions according to switch resistor consolidation.
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4年前 |
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Michael Schloh von Bennewitz
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670ea5ea44
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Try a risky consolidation of switch circuits from 39 ohm series to 220.
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4年前 |
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Michael Schloh von Bennewitz
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69e759d47c
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Renumber tape feeder position to correspond with #164 consolidation work.
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4年前 |
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Michael Schloh von Bennewitz
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7d374fafcc
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Try to reach magic number of fourty seven tape feeders by consolidation.
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4年前 |
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Michael Schloh von Bennewitz
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812a589f28
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Regenerate schematic designs for use in RF analysis and consultation.
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4年前 |
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Michael Schloh von Bennewitz
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ca4f317856
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Update the automated placement configuration accordingly.
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4年前 |
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Michael Schloh von Bennewitz
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fb71af7c10
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Resolve #160 by laboriously rerouting test point trace to an unsused pin.
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4年前 |
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Michael Schloh von Bennewitz
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55b36219e6
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Improve to partially accommodate #147 bus power to backpower a host.
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4年前 |
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Michael Schloh von Bennewitz
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47cf21d85a
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Resolve #164 by consolidating most parts in the comment suggestion.
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4年前 |
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Michael Schloh von Bennewitz
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731c5e9822
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Correct load capacitor values for LSE and modify HSE on assumptions.
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4年前 |
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Michael Schloh von Bennewitz
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bbe2fa3ba0
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Track feeder areas in use to contrast with DNP or derivative models.
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4年前 |
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Michael Schloh von Bennewitz
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33ff35773c
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Begin process of reducing unique part count by DNP identifying 0R.
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4年前 |
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Michael Schloh von Bennewitz
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c965b8a3f8
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Adjust schematic labels, relabel D8 designator to D3, and regenerate layout.
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4年前 |
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Michael Schloh von Bennewitz
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bb1358e0cd
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Try to resolve #161 and #162 mechanical engineering problems.
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4年前 |
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Michael Schloh von Bennewitz
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9983967507
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Add a specifications based representation of a J-Link mini device.
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4年前 |
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Michael Schloh von Bennewitz
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59b01f1a56
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Resolve 155 by adding minimal but important extra notation for alternates.
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4年前 |
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Michael Schloh von Bennewitz
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a137ed3acd
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Modify parts list according to recent diode and resistance corrections.
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4年前 |
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Michael Schloh von Bennewitz
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b810dbe634
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Resolve #154 again by correcting the 2mm and 1,6mm mounting holes to 1,8mm.
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4年前 |
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Michael Schloh von Bennewitz
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a2fe5b3342
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Resolve #158 and #159 by balancing resistance values of light diodes.
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4年前 |
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Michael Schloh von Bennewitz
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7d6f26ec2c
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Improve placement of ground indicator symbol in the bottom silkscreen.
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4年前 |
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Michael Schloh von Bennewitz
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12d95a2a2f
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Add a provisional (used in panelisation) frame design and solve #154.
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4年前 |
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Michael Schloh von Bennewitz
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72d65899a0
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Solve automation vision errors #145 by positioning and removing fiducials.
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4年前 |
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Michael Schloh von Bennewitz
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08e361811f
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Route reset signal from controller chip to host, solving #153.
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4年前 |
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Michael Schloh von Bennewitz
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e6845790e5
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Remove partless entries corresponding with solder jumpers and annotate.
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4年前 |
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Michael Schloh von Bennewitz
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84c7614e99
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Hack the horizontal J4 UART connector notation to accommodate an edge.
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4年前 |
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Michael Schloh von Bennewitz
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f790aa3252
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Reposition fiducials according to automation test results, and add FID6.
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4年前 |
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Michael Schloh von Bennewitz
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7f64df9903
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Improve notations of programming connector headers avoiding JTAG.
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4年前 |
