Michael Schloh von Bennewitz
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d6f0deb432
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Increase track widths and reduce (sloppy) vias in RF paths to antennas.
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4 лет назад |
Michael Schloh von Bennewitz
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50e65f2bcb
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Add mounting holes to the test jig and avoid upside down text in panels.
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4 лет назад |
Michael Schloh von Bennewitz
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898da4fa7c
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Regenerate portable document format schematic capture for update.
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4 лет назад |
Michael Schloh von Bennewitz
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1c8ea4862a
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Implement design review suggestions to resolve #61 and #62.
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4 лет назад |
Michael Schloh von Bennewitz
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fe06fd495f
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Adjust track width, via drills, and annular rings to minimum specs.
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4 лет назад |
Michael Schloh von Bennewitz
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8d28560c4e
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Tighten tolerances to highest four layer ENIG cheap fabrication capacity.
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4 лет назад |
Michael Schloh von Bennewitz
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f779b7999a
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Adapt layers and tolerances to correspond with four layer qualities.
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4 лет назад |
Michael Schloh von Bennewitz
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a71b05cc81
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Prepare for layout edition in BGA with corresponding traces and vias.
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4 лет назад |
Michael Schloh von Bennewitz
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41e5f095e8
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Include more project boilerplate structure and library cache.
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4 лет назад |
Michael Schloh von Bennewitz
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56dfb433cc
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Initialise hardware engineering for imminent schematic capture.
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4 лет назад |