A pin with GCLK_IO[x] functionality can be used to route GCLKx clock. In this case, we will use GCLK3 to output clock as PA17(GCLK_IO[3]) is available for probing in the design through R14(I2C_SCL).

Enable clock output by configuring GCLKx as below to enable clock output(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE) for the specific GCLK. These changes are done in conf_clocks.h.

# define CONF_CLOCK_GCLK_3_ENABLE               true
# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY       false
# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE         SYSTEM_CLOCK_SOURCE_XOSC32K
# define CONF_CLOCK_GCLK_3_PRESCALER            1
# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE        true

Next, I/O PA17 which has GCLK_IO[3] as one of the PINMUX needs to be configured with Pinmux function H. The following code snippet could be added in the board_init.c

struct system_pinmux_config pinmux_config;
system_pinmux_get_config_defaults(&pinmux_config);

pinmux_config.mux_position= PINMUX_PA17H_GCLK_IO3;
pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;

system_pinmux_pin_set_config(PIN_PA17,&pinmux_config);

The above code changes would enable GCLK3 with XOSC32K as clock source with output enabled. The pin PA17(GCLK_IO[3]) is enabled with PINMUX function H. With these changes, the device should be able to output XOSC32K clock on PA17.

# Test LSE crystal circuit for best practice ## Problem environment Crystals in radio applications play an increasingly important role at run time. ## Steps to reproduce 1. Refer to the layout 1. Use a frequency counter 1. Measure crystal circuits ## Expected result The output of all crystals is as expected, and the circuit design follows best practices. ## Actual result Crystal outputs is unknown pending finding a suitable measurement tool. ## Resources https://www.murata.com/en-us/products/timingdevice/crystalu/basic/ https://ww1.microchip.com/downloads/en/AppNotes/AN2648-Selecting_Testing-32KHz-Crystal-Osc-for-AVR-MCUs-00002648B.pdf ## Instructions ``` A pin with GCLK_IO[x] functionality can be used to route GCLKx clock. In this case, we will use GCLK3 to output clock as PA17(GCLK_IO[3]) is available for probing in the design through R14(I2C_SCL). Enable clock output by configuring GCLKx as below to enable clock output(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE) for the specific GCLK. These changes are done in conf_clocks.h. # define CONF_CLOCK_GCLK_3_ENABLE true # define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false # define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_XOSC32K # define CONF_CLOCK_GCLK_3_PRESCALER 1 # define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE true Next, I/O PA17 which has GCLK_IO[3] as one of the PINMUX needs to be configured with Pinmux function H. The following code snippet could be added in the board_init.c struct system_pinmux_config pinmux_config; system_pinmux_get_config_defaults(&pinmux_config); pinmux_config.mux_position= PINMUX_PA17H_GCLK_IO3; pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; system_pinmux_pin_set_config(PIN_PA17,&pinmux_config); The above code changes would enable GCLK3 with XOSC32K as clock source with output enabled. The pin PA17(GCLK_IO[3]) is enabled with PINMUX function H. With these changes, the device should be able to output XOSC32K clock on PA17. ``` ## Severity level This is **low priority** because project requirements do not mandate calibrated radio transception.

It was determined that the optimal capacitor load is between 15pF and 20pF, as shown by the C18 and C19 values of 18pF.