# Use of GCLK_0 for LSE output is flawed ## Problem environment The clock frequency of the low speed external crystal (LSE) can be configured to output a interference free signal to selected GPIO pins, such as PB22(E5.) ## Steps to reproduce 1. Refer to the schematic 1. Locate the PB22 (E5) pin 1. Locate the PA22 (D8) and PA23 (D7) pins 1. Compare the quality of routing from pins ## Expected result The GCLK_0 output is reserved for the main clock, and either PA22 or PA23 are used to copy LSE crystal output to GCLK_6 or GCLK_7. ## Actual result Main clock configuration is disregarded and LSE crystal output is copied to GCLK_0. ## Severity level This is **low priority** because project requirements do not mandate clock calibration.

Solved by commits reported in #160.