Conflicting GCLK0 is used for LSE tests

Problem environment

A MCU GPIO pin is used to output the LSE crystal frequency to the GCLK0 timer, which is used by default to set the general controller speed.

Steps to reproduce

1. Refer to the schematic
2. Refer to the MCU datasheet
3. Locate documentation regarding clock output

Expected result

A MCU GPIO pin is chosen and routed according to the ability to duplicate the LSE frewquency output to a timer other than GCLK0.

Actual result

The LSE frequency output is duplicated to a MCU GPIO pin that is only able to use the GCLK0 timer circuit.

Workaround

Reprogram the I²C data pin to carry the LSE frequency crystal's output signal, and remove the pull up resistor and other parts connected to the I²C data pin. Measure LSE output at the new hacked pin circuit, after programming the chip to route the signal to GCLK3.

Severity level

This is low priority because crystal tuning and clock hacking are not one of the use cases supported.

All other GCLK compatible pins support GCLK_IO[0] only, according to the SAM R34/R35 datasheet page 14.

Solved in fb71af7 by rerouting testpoint TP13 from E5 (PB22/GCLK0) to D8 (PA22/GCLK6) and modifying firmware sample files respectively.