Different values of capacitance balance input to switching circuits, and sometimes multiple values are specified. Each capacitance may benefit from variation in package size due to internal parasitics and resonance.
Steps to reproduce
Observe the most active ICs in schematic
Follow the bypass capacitor arrays
Ensure spacial arrangement
Ensure different packages
Expected result
The bypass capacitor array sizes and spacial arrangement is optimal.
Actual result
The capacitor array(s) are not examined for optmial behaviour.
Severity level
This is low priority because project requirements make no mention of power supply optimisation.
# Optimise bypass capacitances
## Problem environment
Different values of capacitance balance input to switching circuits, and sometimes multiple values are specified. Each capacitance may benefit from variation in package size due to internal parasitics and resonance.
## Steps to reproduce
1. Observe the most active ICs in schematic
1. Follow the bypass capacitor arrays
1. Ensure spacial arrangement
1. Ensure different packages
## Expected result
The bypass capacitor array sizes and spacial arrangement is optimal.
## Actual result
The capacitor array(s) are not examined for optmial behaviour.
## Severity level
This is **low priority** because project requirements make no mention of power supply optimisation.
Optimise bypass capacitances
Problem environment
Different values of capacitance balance input to switching circuits, and sometimes multiple values are specified. Each capacitance may benefit from variation in package size due to internal parasitics and resonance.
Steps to reproduce
Expected result
The bypass capacitor array sizes and spacial arrangement is optimal.
Actual result
The capacitor array(s) are not examined for optmial behaviour.
Severity level
This is low priority because project requirements make no mention of power supply optimisation.