Europalab Devices produces a LoRaWAN transmitting client node, specialised for higher research of actuator and sensor assisted IoT networks. https://dev.europalab.com/nlnet/20200000/
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Michael Schloh von Bennewitz 84c7614e99 Hack the horizontal J4 UART connector notation to accommodate an edge. 4 years ago
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billofmat Work on #141 by integrating pi networks to match impedence in antennas. 4 years ago
fabplace Modify tape feeder pick configuration to improve handling of parts. 4 years ago
fabprint Regenerate portable document format schematic capture for update. 4 years ago
libraries Modify deprecated secure element model to new ATECC608B throughout. 4 years ago
modules Add forgotten but used in layout replacement for cut holes a module. 4 years ago
.gitignore Include positions for forthcoming tool configuration and machine import. 4 years ago
LICENSE Add project infrastructure files corresponding to hardware engineering. 5 years ago
conn-mchip.sch Add test points for USB data quality assurance (especially type C.) 4 years ago
conn-stmicro.sch Bump version numbers pending panelisation and prepare to manufacture. 4 years ago
ctrl-mchip.sch Bump version numbers pending panelisation and prepare to manufacture. 4 years ago
ctrl-stmicro.sch Bump version numbers pending panelisation and prepare to manufacture. 4 years ago
dscomm-cache.lib Implement design review suggestions to resolve #61 and #62. 4 years ago
dscomm-panel.kicad_pcb Correct electronic design rules check results pending imminent release. 4 years ago
dscomm-panel.pro Complete production grade panelisation and foil design for LPKF frames. 4 years ago
dscomm-stencil.kicad_pcb Selectively remove paste apertures and replace hole cuts with drills. 4 years ago
dscomm-stencil.pro Complete production grade panelisation and foil design for LPKF frames. 4 years ago
dscomm-tstjig.kicad_pcb Remove MPLab Snap because it fails on all Opensource (GDB) applications. 4 years ago
dscomm-tstjig.pro Add mounting holes to the test jig and avoid upside down text in panels. 4 years ago
dscomm.kicad_pcb Hack the horizontal J4 UART connector notation to accommodate an edge. 4 years ago
dscomm.net Reposition fiducials according to automation test results, and add FID6. 4 years ago
dscomm.pro Increase track widths and reduce (sloppy) vias in RF paths to antennas. 4 years ago
dscomm.sch Reposition fiducials according to automation test results, and add FID6. 4 years ago
elabdev-black.kicad_wks Include more project boilerplate structure and library cache. 4 years ago
elabdev-white.kicad_wks Include more project boilerplate structure and library cache. 4 years ago
feat-mchip.sch Bump version numbers pending panelisation and prepare to manufacture. 4 years ago
form-arduino.kicad_pcb Bump hardware revision number pending tag for design review. 4 years ago
form-arduino.pro Complete milestone 'Blank FR4 design' for remaining device formats. 4 years ago
form-arduino.sch Bump version numbers pending panelisation and prepare to manufacture. 4 years ago
form-beagle.kicad_pcb Bump hardware revision number pending tag for design review. 4 years ago
form-beagle.pro Complete milestone 'Blank FR4 design' for remaining device formats. 4 years ago
form-beagle.sch Bump version numbers pending panelisation and prepare to manufacture. 4 years ago
form-bmicro.kicad_pcb Bump hardware revision number pending tag for design review. 4 years ago
form-bmicro.pro Redevelop, correct corners, and add connections to format variants. 4 years ago
form-bmicro.sch Bump version numbers pending panelisation and prepare to manufacture. 4 years ago
form-frdm.kicad_pcb Bump hardware revision number pending tag for design review. 4 years ago
form-frdm.pro Redevelop, correct corners, and add connections to format variants. 4 years ago
form-frdm.sch Bump version numbers pending panelisation and prepare to manufacture. 4 years ago
fp-lib-table Redesign for STM32WL SoC architecture, add features, and bump version. 4 years ago
pwr-stmicro.sch Bump version numbers pending panelisation and prepare to manufacture. 4 years ago
rfsw-mchip.sch Work on #141 by integrating pi networks to match impedence in antennas. 4 years ago
rfsw-stmicro.sch Bump version numbers pending panelisation and prepare to manufacture. 4 years ago
sym-lib-table Integrate local symbols and footprint libraries pending components. 4 years ago