 Michael Schloh von Bennewitz
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234e679a69
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Correct misaligned trace on board edge and oversized trace near cutout.
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4年前 |
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Michael Schloh von Bennewitz
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f36857e49e
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Reverse UFL and try to finish chip antenna and 50 ohm feed line traces.
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4年前 |
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Michael Schloh von Bennewitz
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80951d020f
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Integrate manufacturer advice from Johanson on AE5 corner placement.
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4年前 |
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Michael Schloh von Bennewitz
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c6ed8ea5c8
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Reposition chip antenna to improve return loss at the target frequency.
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4年前 |
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Michael Schloh von Bennewitz
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95308f748c
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Set default track width, spacing, via size, and hole diameters suitably.
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4年前 |
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Michael Schloh von Bennewitz
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670ea5ea44
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Try a risky consolidation of switch circuits from 39 ohm series to 220.
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4年前 |
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Michael Schloh von Bennewitz
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7d374fafcc
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Try to reach magic number of fourty seven tape feeders by consolidation.
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4年前 |
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Michael Schloh von Bennewitz
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fb71af7c10
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Resolve #160 by laboriously rerouting test point trace to an unsused pin.
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4年前 |
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Michael Schloh von Bennewitz
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55b36219e6
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Improve to partially accommodate #147 bus power to backpower a host.
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4年前 |
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Michael Schloh von Bennewitz
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47cf21d85a
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Resolve #164 by consolidating most parts in the comment suggestion.
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4年前 |
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Michael Schloh von Bennewitz
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731c5e9822
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Correct load capacitor values for LSE and modify HSE on assumptions.
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4年前 |
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Michael Schloh von Bennewitz
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33ff35773c
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Begin process of reducing unique part count by DNP identifying 0R.
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4年前 |
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Michael Schloh von Bennewitz
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c965b8a3f8
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Adjust schematic labels, relabel D8 designator to D3, and regenerate layout.
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4年前 |
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Michael Schloh von Bennewitz
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bb1358e0cd
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Try to resolve #161 and #162 mechanical engineering problems.
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4年前 |
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Michael Schloh von Bennewitz
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59b01f1a56
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Resolve 155 by adding minimal but important extra notation for alternates.
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4年前 |
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Michael Schloh von Bennewitz
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a2fe5b3342
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Resolve #158 and #159 by balancing resistance values of light diodes.
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4年前 |
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Michael Schloh von Bennewitz
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7d6f26ec2c
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Improve placement of ground indicator symbol in the bottom silkscreen.
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4年前 |
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Michael Schloh von Bennewitz
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72d65899a0
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Solve automation vision errors #145 by positioning and removing fiducials.
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4年前 |
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Michael Schloh von Bennewitz
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08e361811f
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Route reset signal from controller chip to host, solving #153.
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4年前 |
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Michael Schloh von Bennewitz
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84c7614e99
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Hack the horizontal J4 UART connector notation to accommodate an edge.
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4年前 |
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Michael Schloh von Bennewitz
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f790aa3252
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Reposition fiducials according to automation test results, and add FID6.
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4年前 |
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Michael Schloh von Bennewitz
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7f64df9903
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Improve notations of programming connector headers avoiding JTAG.
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4年前 |
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Michael Schloh von Bennewitz
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7af8ba97f5
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Improve fiducial size, form, placement, and structure to resolve #145.
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4年前 |
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Michael Schloh von Bennewitz
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eb74067f05
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Add test points for USB data quality assurance (especially type C.)
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4年前 |
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Michael Schloh von Bennewitz
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d6f0deb432
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Increase track widths and reduce (sloppy) vias in RF paths to antennas.
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4年前 |
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Michael Schloh von Bennewitz
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02bbb27912
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Remove paste from unpopulated chip antenna passive pads and clarify.
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4年前 |
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Michael Schloh von Bennewitz
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d8106ebb3a
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Add structures and circuits to support forthcoming test jig construction.
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4年前 |
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Michael Schloh von Bennewitz
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5a29587d8e
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Work on #141 by integrating pi networks to match impedence in antennas.
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4年前 |
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Michael Schloh von Bennewitz
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dfae2135e6
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Adjust label spacing slightly on designator text in the silkscreen.
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4年前 |
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Michael Schloh von Bennewitz
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c80ec05067
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Correct electronic design rules check results pending imminent release.
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4年前 |
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Michael Schloh von Bennewitz
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035f934f79
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Repour lost filled areas on all layers, forgotten in last commit.
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4年前 |
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Michael Schloh von Bennewitz
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e71589f739
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Reshape and position the hack that silkscreen indicator bar.
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4年前 |
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Michael Schloh von Bennewitz
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f143228cb3
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Selectively remove paste apertures and replace hole cuts with drills.
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4年前 |
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Michael Schloh von Bennewitz
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9702fcfc69
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Improve name text of artist signature which was too long before.
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4年前 |
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Michael Schloh von Bennewitz
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9f370cd029
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Annotate J5 and J20 according to their serial protocols in silkscreens.
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4年前 |
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Michael Schloh von Bennewitz
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3dfc431d97
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Mark the first JTAG SWD debug interface connector in the silkscreen.
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4年前 |
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Michael Schloh von Bennewitz
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f2ad7f7ead
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Remove stray user drawing layer of a edge cut guidance horizontal bar.
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4年前 |
 Michael Schloh von Bennewitz
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f4a7a6cc9f
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Bump version numbers pending panelisation and prepare to manufacture.
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4年前 |
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Michael Schloh von Bennewitz
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4f3db6f44a
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Correct USB bus power circuit according to reference design and adjust.
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4年前 |
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Michael Schloh von Bennewitz
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8eebf51cfb
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Adjust position of external display connection cutout on board bottom.
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4年前 |
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Michael Schloh von Bennewitz
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6040ddcdfa
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Add holes for hackfield, antenna legend, and correct enclosure hinges.
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4年前 |
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Michael Schloh von Bennewitz
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5bf1b6c077
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Refine calibration suggestion from 12pF to 15pF indicated by counter.
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4年前 |
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Michael Schloh von Bennewitz
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98b1e69d93
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Correct version number as indicated in silkscreen text.
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4年前 |
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Michael Schloh von Bennewitz
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1c8ea4862a
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Implement design review suggestions to resolve #61 and #62.
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4年前 |
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Michael Schloh von Bennewitz
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73a6ed98bc
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Add a test point to allow LSE crystal output redirection to a MCU pin.
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4年前 |
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Michael Schloh von Bennewitz
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95df65933d
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Resolve #128 by rerouting bus power to PA07 F3 to bus test circuit.
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4年前 |
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Michael Schloh von Bennewitz
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799c6fe772
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Calibrate crystal circuits by trial and error pending spectrum analysis.
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4年前 |
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Michael Schloh von Bennewitz
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1f2fe604d8
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Connect pads from pogo pin test matrix to GND and 3V3 to future proof.
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4年前 |
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Michael Schloh von Bennewitz
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afa5216e09
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Resolve #122 by removing AE7 and JP10 from the layout, and add a PWR LED.
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4年前 |
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Michael Schloh von Bennewitz
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d772d2f788
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Resolve #83 after tests indicate MLS correctly supplies power from PA09.
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4年前 |
