271 次程式碼提交 (76f8fc95beeb168d050dc733bad3977d18b96fae)

 

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作者	SHA1	備註	提交日期
Michael Schloh von Bennewitz	7d0f59100f	Add forgotten but used in layout replacement for cut holes a module.	4 年之前
Michael Schloh von Bennewitz	898da4fa7c	Regenerate portable document format schematic capture for update.	4 年之前
Michael Schloh von Bennewitz	f143228cb3	Selectively remove paste apertures and replace hole cuts with drills.	4 年之前
Michael Schloh von Bennewitz	8e9ea6370a	Generate and curate parts list, panel design, and stencil foil.	4 年之前
Michael Schloh von Bennewitz	3ba5b2870f	Add out of tree footprint module files for inclusion in manufacturing.	4 年之前
Michael Schloh von Bennewitz	9702fcfc69	Improve name text of artist signature which was too long before.	4 年之前
Michael Schloh von Bennewitz	719e193c1b	Add a 45mm large mousebite panel tab to accommodate enclosure hinges.	4 年之前
Michael Schloh von Bennewitz	9f370cd029	Annotate J5 and J20 according to their serial protocols in silkscreens.	4 年之前
Michael Schloh von Bennewitz	3dfc431d97	Mark the first JTAG SWD debug interface connector in the silkscreen.	4 年之前
Michael Schloh von Bennewitz	7d49528ff2	Reflect information from bug reports #129 and #130 pending VNA tests.	4 年之前
Michael Schloh von Bennewitz	f2ad7f7ead	Remove stray user drawing layer of a edge cut guidance horizontal bar.	4 年之前
Michael Schloh von Bennewitz	f4a7a6cc9f	Bump version numbers pending panelisation and prepare to manufacture.	4 年之前
Michael Schloh von Bennewitz	4f3db6f44a	Correct USB bus power circuit according to reference design and adjust.	4 年之前
Michael Schloh von Bennewitz	8eebf51cfb	Adjust position of external display connection cutout on board bottom.	4 年之前
Michael Schloh von Bennewitz	6040ddcdfa	Add holes for hackfield, antenna legend, and correct enclosure hinges.	4 年之前
Michael Schloh von Bennewitz	5bf1b6c077	Refine calibration suggestion from 12pF to 15pF indicated by counter.	4 年之前
Michael Schloh von Bennewitz	c4e91a8557	Update parts list according to recent corrections in schematic capture.	4 年之前
Michael Schloh von Bennewitz	98b1e69d93	Correct version number as indicated in silkscreen text.	4 年之前
Michael Schloh von Bennewitz	1c8ea4862a	Implement design review suggestions to resolve #61 and #62.	4 年之前
Michael Schloh von Bennewitz	73a6ed98bc	Add a test point to allow LSE crystal output redirection to a MCU pin.	4 年之前
Michael Schloh von Bennewitz	95df65933d	Resolve #128 by rerouting bus power to PA07 F3 to bus test circuit.	4 年之前
Michael Schloh von Bennewitz	e14d4526eb	Calibrate crystal circuits by trial and error pending spectrum analysis.	4 年之前
Michael Schloh von Bennewitz	799c6fe772	Calibrate crystal circuits by trial and error pending spectrum analysis.	4 年之前
Michael Schloh von Bennewitz	1f2fe604d8	Connect pads from pogo pin test matrix to GND and 3V3 to future proof.	4 年之前
Michael Schloh von Bennewitz	afa5216e09	Resolve #122 by removing AE7 and JP10 from the layout, and add a PWR LED.	4 年之前
Michael Schloh von Bennewitz	d772d2f788	Resolve #83 after tests indicate MLS correctly supplies power from PA09.	4 年之前
Michael Schloh von Bennewitz	a6fcbdf613	Resolve bug report #118 by replacing 10pF with 7pF load capacitors.	4 年之前
Michael Schloh von Bennewitz	8c6be81782	Update generated schematic output to correspond with current design.	4 年之前
Michael Schloh von Bennewitz	89c95b975f	Bump hardware revision number pending tag for design review.	4 年之前
Michael Schloh von Bennewitz	8c114dd4b4	Correct optional PA14_XIN and PA15_XOUT external crystal floating pins.	4 年之前
Michael Schloh von Bennewitz	52eec91b20	Correct HSE circuit and remove JP26, add RFSW testpoints and text.	4 年之前
Michael Schloh von Bennewitz	7c358ddd46	Resolve #114 by replacing flawed 27 pF value with 2,7 pF throughout.	4 年之前
Michael Schloh von Bennewitz	68066fe6a9	Include a portable document format rendition of the schematic.	4 年之前
Michael Schloh von Bennewitz	b6cc59333c	Correct secure element model number to support easy TTN integration.	4 年之前
Michael Schloh von Bennewitz	819a415fc9	Modify deprecated secure element model to new ATECC608B throughout.	4 年之前
Michael Schloh von Bennewitz	f6764b5d5e	Add top layer test points to connect with bottom layer solder grid.	4 年之前
Michael Schloh von Bennewitz	b969424881	Resolve #104 by removing unconnected vias from AE5 pad 1.	4 年之前
Michael Schloh von Bennewitz	40a2b218fe	Redevelop, correct corners, and add connections to format variants.	4 年之前
Michael Schloh von Bennewitz	060584f6bc	Complete milestone 'Blank FR4 design' for remaining device formats.	4 年之前
Michael Schloh von Bennewitz	bb8473ae5a	Complete production grade panelisation and foil design for LPKF frames.	4 年之前
Michael Schloh von Bennewitz	6697d42f59	Correct misplaced designator text label rotated in the last commit.	4 年之前
Michael Schloh von Bennewitz	9a29ebfc09	Resolve #97 by redesigning the QFN-12 footprint used for the U4 RF switch.	4 年之前
Michael Schloh von Bennewitz	a2b385851b	Add handwritten signature decorative text to bottom silkscreen.	4 年之前
Michael Schloh von Bennewitz	b727e44ef5	Resolve DRC errors and panelise irregular tabs for consistency.	4 年之前
Michael Schloh von Bennewitz	62e6e0b06b	Regenerate and commit the netlist reflecting the power flag addition.	4 年之前
Michael Schloh von Bennewitz	0753ffa445	Resolve a false positive on ERC by adding a power flag to a supply input.	4 年之前
Michael Schloh von Bennewitz	73d2e45c06	Improve continuity of the ground plane of the top layer by adding a via.	4 年之前
Michael Schloh von Bennewitz	dde5e9ffb4	Bump revision pending release to panelisation and imminent fabrication.	4 年之前
Michael Schloh von Bennewitz	7c2b89e222	Correct flawed U2 package size and bump revision pending release.	4 年之前
Michael Schloh von Bennewitz	3c10b0797f	Modify placement of J1 battery power selection jumper to improve access.	4 年之前