 Michael Schloh von Bennewitz
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55b36219e6
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Improve to partially accommodate #147 bus power to backpower a host.
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4年前 |
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Michael Schloh von Bennewitz
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47cf21d85a
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Resolve #164 by consolidating most parts in the comment suggestion.
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4年前 |
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Michael Schloh von Bennewitz
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731c5e9822
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Correct load capacitor values for LSE and modify HSE on assumptions.
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4年前 |
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Michael Schloh von Bennewitz
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bbe2fa3ba0
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Track feeder areas in use to contrast with DNP or derivative models.
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4年前 |
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Michael Schloh von Bennewitz
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33ff35773c
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Begin process of reducing unique part count by DNP identifying 0R.
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4年前 |
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Michael Schloh von Bennewitz
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c965b8a3f8
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Adjust schematic labels, relabel D8 designator to D3, and regenerate layout.
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4年前 |
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Michael Schloh von Bennewitz
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bb1358e0cd
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Try to resolve #161 and #162 mechanical engineering problems.
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4年前 |
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Michael Schloh von Bennewitz
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9983967507
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Add a specifications based representation of a J-Link mini device.
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4年前 |
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Michael Schloh von Bennewitz
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59b01f1a56
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Resolve 155 by adding minimal but important extra notation for alternates.
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4年前 |
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Michael Schloh von Bennewitz
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a137ed3acd
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Modify parts list according to recent diode and resistance corrections.
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4年前 |
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Michael Schloh von Bennewitz
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b810dbe634
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Resolve #154 again by correcting the 2mm and 1,6mm mounting holes to 1,8mm.
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4年前 |
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Michael Schloh von Bennewitz
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a2fe5b3342
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Resolve #158 and #159 by balancing resistance values of light diodes.
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4年前 |
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Michael Schloh von Bennewitz
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7d6f26ec2c
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Improve placement of ground indicator symbol in the bottom silkscreen.
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4年前 |
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Michael Schloh von Bennewitz
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12d95a2a2f
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Add a provisional (used in panelisation) frame design and solve #154.
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4年前 |
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Michael Schloh von Bennewitz
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72d65899a0
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Solve automation vision errors #145 by positioning and removing fiducials.
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4年前 |
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Michael Schloh von Bennewitz
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08e361811f
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Route reset signal from controller chip to host, solving #153.
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4年前 |
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Michael Schloh von Bennewitz
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e6845790e5
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Remove partless entries corresponding with solder jumpers and annotate.
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4年前 |
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Michael Schloh von Bennewitz
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84c7614e99
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Hack the horizontal J4 UART connector notation to accommodate an edge.
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4年前 |
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Michael Schloh von Bennewitz
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f790aa3252
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Reposition fiducials according to automation test results, and add FID6.
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4年前 |
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Michael Schloh von Bennewitz
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7f64df9903
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Improve notations of programming connector headers avoiding JTAG.
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4年前 |
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Michael Schloh von Bennewitz
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8c965b9b90
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Modify tape feeder pick configuration to improve handling of parts.
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4年前 |
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Michael Schloh von Bennewitz
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7af8ba97f5
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Improve fiducial size, form, placement, and structure to resolve #145.
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4年前 |
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Michael Schloh von Bennewitz
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eb74067f05
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Add test points for USB data quality assurance (especially type C.)
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4年前 |
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Michael Schloh von Bennewitz
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a2e76541c1
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Remove MPLab Snap because it fails on all Opensource (GDB) applications.
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4年前 |
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Michael Schloh von Bennewitz
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c7e1804622
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Add MPLab Snap and STLink V3Mini devices as candidate programmers.
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4年前 |
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Michael Schloh von Bennewitz
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d6f0deb432
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Increase track widths and reduce (sloppy) vias in RF paths to antennas.
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4年前 |
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Michael Schloh von Bennewitz
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1aa5ae7f55
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Provisionally added chip programmer dimensions and hole spacing.
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4年前 |
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Michael Schloh von Bennewitz
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02bbb27912
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Remove paste from unpopulated chip antenna passive pads and clarify.
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4年前 |
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Michael Schloh von Bennewitz
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50e65f2bcb
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Add mounting holes to the test jig and avoid upside down text in panels.
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4年前 |
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Michael Schloh von Bennewitz
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d8106ebb3a
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Add structures and circuits to support forthcoming test jig construction.
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4年前 |
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Michael Schloh von Bennewitz
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70ff0c71ff
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Develop the placement configuration pending assembly of release 0.9.2.
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4年前 |
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Michael Schloh von Bennewitz
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5a29587d8e
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Work on #141 by integrating pi networks to match impedence in antennas.
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4年前 |
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Michael Schloh von Bennewitz
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b3b668c47c
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Calibrate for tooling update to 0.9.2 and prepare for placments.
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4年前 |
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Michael Schloh von Bennewitz
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c42820dfaa
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Update according to latest state of the SMT assembly lab toolset.
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4年前 |
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Michael Schloh von Bennewitz
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dfae2135e6
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Adjust label spacing slightly on designator text in the silkscreen.
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4年前 |
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Michael Schloh von Bennewitz
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c80ec05067
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Correct electronic design rules check results pending imminent release.
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4年前 |
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Michael Schloh von Bennewitz
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035f934f79
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Repour lost filled areas on all layers, forgotten in last commit.
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4年前 |
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Michael Schloh von Bennewitz
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e71589f739
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Reshape and position the hack that silkscreen indicator bar.
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4年前 |
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Michael Schloh von Bennewitz
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7d0f59100f
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Add forgotten but used in layout replacement for cut holes a module.
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4年前 |
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Michael Schloh von Bennewitz
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898da4fa7c
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Regenerate portable document format schematic capture for update.
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4年前 |
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Michael Schloh von Bennewitz
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f143228cb3
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Selectively remove paste apertures and replace hole cuts with drills.
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4年前 |
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Michael Schloh von Bennewitz
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8e9ea6370a
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Generate and curate parts list, panel design, and stencil foil.
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4年前 |
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Michael Schloh von Bennewitz
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3ba5b2870f
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Add out of tree footprint module files for inclusion in manufacturing.
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4年前 |
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Michael Schloh von Bennewitz
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9702fcfc69
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Improve name text of artist signature which was too long before.
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4年前 |
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Michael Schloh von Bennewitz
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719e193c1b
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Add a 45mm large mousebite panel tab to accommodate enclosure hinges.
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4年前 |
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Michael Schloh von Bennewitz
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9f370cd029
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Annotate J5 and J20 according to their serial protocols in silkscreens.
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4年前 |
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Michael Schloh von Bennewitz
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3dfc431d97
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Mark the first JTAG SWD debug interface connector in the silkscreen.
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4年前 |
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Michael Schloh von Bennewitz
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7d49528ff2
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Reflect information from bug reports #129 and #130 pending VNA tests.
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4年前 |
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Michael Schloh von Bennewitz
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f2ad7f7ead
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Remove stray user drawing layer of a edge cut guidance horizontal bar.
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4年前 |
 Michael Schloh von Bennewitz
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f4a7a6cc9f
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Bump version numbers pending panelisation and prepare to manufacture.
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4年前 |
