#160 Conflicting GCLK0 is used for LSE tests

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opened 3 years ago by Michael Schloh von Bennewitz · 2 comments

Conflicting GCLK0 is used for LSE tests

Problem environment

A MCU GPIO pin is used to output the LSE crystal frequency to the GCLK0 timer, which is used by default to set the general controller speed.

Steps to reproduce

Refer to the schematic
Refer to the MCU datasheet
Locate documentation regarding clock output

Expected result

A MCU GPIO pin is chosen and routed according to the ability to duplicate the LSE frewquency output to a timer other than GCLK0.

Actual result

The LSE frequency output is duplicated to a MCU GPIO pin that is only able to use the GCLK0 timer circuit.

Workaround

Reprogram the I²C data pin to carry the LSE frequency crystal's output signal, and remove the pull up resistor and other parts connected to the I²C data pin. Measure LSE output at the new hacked pin circuit, after programming the chip to route the signal to GCLK3.

Severity level

This is low priority because crystal tuning and clock hacking are not one of the use cases supported.

Michael Schloh von Bennewitz added the

enhancement

label 3 years ago

Michael Schloh von Bennewitz added the

help wanted

label 3 years ago

Michael Schloh von Bennewitz added this to the Final schematic and layout design milestone 3 years ago

Pin	Clock-ID	I/O	In-use
G8	GCLK_IO[1]	PA15	CRYOUT
F7	GCLK_IO[2]	PA16	I²C-SDA
E6	GCLK_IO[3]	PA17	I²C-SCL
D8	GCLK_IO[6]	PA22	202101
D7	GCLK_IO[7]	PA23	No
C7	GCLK_IO[1]	PB23	No
E5	GCLK_IO[0]	PB22	202012