 Michael Schloh von Bennewitz
|
659c316ae0
|
Bump revision numbers, dates, and copyright pending release to manufacturing.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
f790aa3252
|
Reposition fiducials according to automation test results, and add FID6.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
7af8ba97f5
|
Improve fiducial size, form, placement, and structure to resolve #145.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
f143228cb3
|
Selectively remove paste apertures and replace hole cuts with drills.
|
4 年之前 |
 Michael Schloh von Bennewitz
|
f4a7a6cc9f
|
Bump version numbers pending panelisation and prepare to manufacture.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
1c8ea4862a
|
Implement design review suggestions to resolve #61 and #62.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
73a6ed98bc
|
Add a test point to allow LSE crystal output redirection to a MCU pin.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
89c95b975f
|
Bump hardware revision number pending tag for design review.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
060584f6bc
|
Complete milestone 'Blank FR4 design' for remaining device formats.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
dde5e9ffb4
|
Bump revision pending release to panelisation and imminent fabrication.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
8e36a89bf0
|
Resolve #72 and #74 by rerouting traces, jumpers, and pads.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
1697e5268f
|
Record an out of scope concept to integrate FOMU in design to bookmark.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
06be85075b
|
Renumber and bump version pending layout edition of ST SoC migration.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
e1e0f5c1d5
|
Redesign for STM32WL SoC architecture, add features, and bump version.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
44bdd2e1e4
|
Bump hardware revision number pending release to manufacturing.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
6c7b76d799
|
Bump hardware revision number pending milestone progress and test cycle.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
2fa32f80c2
|
Add test points to allow flexible postassembly prototype debugging.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
2aa746b314
|
Add logos to schematic, that unfortunately do not fit in the layout.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
dca0d14ff0
|
Correct flawed net in cross connected serial wire debug contacts.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
636ecc14e6
|
Correct flawed ground short in secure element authentication circuit.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
eedb5cdd42
|
Improve mounting hole unit numbering by hand modifying identifiers.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
57d2b72b53
|
Add test point loops and correct sized mounting holes.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
69acaf3e33
|
Add EEPROM, jumpers, and connector pending migration to hat format.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
54e8c2e73c
|
Correct schematics after electric rules check results in warnings.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
fc60477441
|
Correct poor abstraction bug #4 and generally complete Microchip circuits.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
ff52db338c
|
Annotate symbols, correct power circuits, and assign footprints.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
c2b37009ee
|
Add remaining circuits to almost complete minimum MCU application.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
202089cd61
|
Complete draft design of RF switch for power amplifier and HF circuits.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
ea03063239
|
Initialise schematic hierarchy and add nested blocks for controller logic.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
41e5f095e8
|
Include more project boilerplate structure and library cache.
|
4 年之前 |
|
Michael Schloh von Bennewitz
|
56dfb433cc
|
Initialise hardware engineering for imminent schematic capture.
|
4 年之前 |
