 Michael Schloh von Bennewitz
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47cf21d85a
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Resolve #164 by consolidating most parts in the comment suggestion.
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Michael Schloh von Bennewitz
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c965b8a3f8
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Adjust schematic labels, relabel D8 designator to D3, and regenerate layout.
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Michael Schloh von Bennewitz
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08e361811f
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Route reset signal from controller chip to host, solving #153.
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Michael Schloh von Bennewitz
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eb74067f05
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Add test points for USB data quality assurance (especially type C.)
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Michael Schloh von Bennewitz
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d8106ebb3a
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Add structures and circuits to support forthcoming test jig construction.
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 Michael Schloh von Bennewitz
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f4a7a6cc9f
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Bump version numbers pending panelisation and prepare to manufacture.
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Michael Schloh von Bennewitz
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4f3db6f44a
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Correct USB bus power circuit according to reference design and adjust.
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Michael Schloh von Bennewitz
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1c8ea4862a
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Implement design review suggestions to resolve #61 and #62.
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Michael Schloh von Bennewitz
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95df65933d
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Resolve #128 by rerouting bus power to PA07 F3 to bus test circuit.
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Michael Schloh von Bennewitz
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1f2fe604d8
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Connect pads from pogo pin test matrix to GND and 3V3 to future proof.
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Michael Schloh von Bennewitz
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89c95b975f
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Bump hardware revision number pending tag for design review.
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Michael Schloh von Bennewitz
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f6764b5d5e
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Add top layer test points to connect with bottom layer solder grid.
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Michael Schloh von Bennewitz
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40a2b218fe
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Redevelop, correct corners, and add connections to format variants.
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Michael Schloh von Bennewitz
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dde5e9ffb4
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Bump revision pending release to panelisation and imminent fabrication.
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Michael Schloh von Bennewitz
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06ee3e4234
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Resolve #80 and #89 by adding a 1 uF decoupling capacitor and connector.
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Michael Schloh von Bennewitz
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8e36a89bf0
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Resolve #72 and #74 by rerouting traces, jumpers, and pads.
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Michael Schloh von Bennewitz
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fa1bcf02a3
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Add a Grove connector, audio level sensor, and remove a UART test point.
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Michael Schloh von Bennewitz
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f332c465c1
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Correct serial connector library symbol for future compatability.
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Michael Schloh von Bennewitz
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06be85075b
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Renumber and bump version pending layout edition of ST SoC migration.
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Michael Schloh von Bennewitz
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f124b45881
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Correct flawed connector symbol in schematic for SiP architecture.
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Michael Schloh von Bennewitz
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e1e0f5c1d5
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Redesign for STM32WL SoC architecture, add features, and bump version.
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Michael Schloh von Bennewitz
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5da94c3830
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Include a solderfield breadboard to support daughterboard development.
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Michael Schloh von Bennewitz
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c0aa16f26e
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Resolve #35 add a board to board connector to prepare daughterboards.
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Michael Schloh von Bennewitz
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6c7b76d799
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Bump hardware revision number pending milestone progress and test cycle.
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Michael Schloh von Bennewitz
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2fa32f80c2
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Add test points to allow flexible postassembly prototype debugging.
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Michael Schloh von Bennewitz
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cc5a03834a
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Correct power circuit in LED parts that require a power flag.
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Michael Schloh von Bennewitz
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636ecc14e6
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Correct flawed ground short in secure element authentication circuit.
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Michael Schloh von Bennewitz
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57d2b72b53
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Add test point loops and correct sized mounting holes.
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Michael Schloh von Bennewitz
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2a1cbb6ddb
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Add nested part to allow either DFN or SOIC EEPROMs to be used.
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Michael Schloh von Bennewitz
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69acaf3e33
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Add EEPROM, jumpers, and connector pending migration to hat format.
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Michael Schloh von Bennewitz
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54e8c2e73c
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Correct schematics after electric rules check results in warnings.
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Michael Schloh von Bennewitz
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a88a134751
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Update existing schematics after modification and subsequent reannotation.
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Michael Schloh von Bennewitz
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fc60477441
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Correct poor abstraction bug #4 and generally complete Microchip circuits.
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