 Michael Schloh von Bennewitz
|
d1de14d468
|
Resolve #81 and #82 by replacing oscillator circuit and inductors.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
be68447c46
|
Improve position of bottom layer silkscreen text for designators.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
7e9d77859b
|
Bump version number pending layout engineering of STM32WL SiP migration.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
e1e0f5c1d5
|
Redesign for STM32WL SoC architecture, add features, and bump version.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
cff212170b
|
Add a paste layer to NPTH mounts to configure for foil apertures.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
5da94c3830
|
Include a solderfield breadboard to support daughterboard development.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
c0aa16f26e
|
Resolve #35 add a board to board connector to prepare daughterboards.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
f7c398852a
|
Resolve #33 Align panel to Stencil8 by relocating mount holes slightly.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
d07d09c41a
|
Increase parts count to 124, and connect all remaining circuits.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
772f799d43
|
Connect power voltage and ground to bottom quarter of board parts.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
b7623201ba
|
Dump layout regeneration after trying to design new test points.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
4a6fe14ba6
|
Apply copper pours to all layers with ground nets except on layer 3.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
dc6f024b36
|
Remove pad to pad spacing tolerance error to almost completely correct.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
4a041e91f9
|
Clean up vias, tracks, spacing, and remove redundant segments.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
fe06fd495f
|
Adjust track width, via drills, and annular rings to minimum specs.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
50ca6fbb0b
|
Connect remaining USB data and UART data circuits for input output.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
dca0d14ff0
|
Correct flawed net in cross connected serial wire debug contacts.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
7cadc14d8f
|
Connect both LEDs to MCU pins for controlling user output.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
b639be76b3
|
Complete draft revision of the radio frequency switch circuit.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
2063328cb1
|
Remove useless chip antenna which takes up more area than total size.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
b1fa69de4a
|
Replace coin cell battery holder and move crystal to make room.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
6daad3ba72
|
Complete most circuits pending layout of RF switch and passive arrays.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
53362e2b0c
|
Upload intermediate layout design with most decapsulation circuits.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
802ec1d175
|
Reflect corrections in power circuits and generally develop layout.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
36323d05c0
|
Improve tab text and position of mouse bites pending part placements.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
0d1eed7fcb
|
Reduce and (prototype) panelise for format change from badge to hat.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
a2807cc2b2
|
Correct title text delimiters in the project layout file.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
41e5f095e8
|
Include more project boilerplate structure and library cache.
|
il y a 4 ans |
|
Michael Schloh von Bennewitz
|
56dfb433cc
|
Initialise hardware engineering for imminent schematic capture.
|
il y a 4 ans |
