 Michael Schloh von Bennewitz
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65fc253676
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Add panel support like mouse bite integrated tabs for panelisation.
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5年前 |
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Michael Schloh von Bennewitz
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5da94c3830
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Include a solderfield breadboard to support daughterboard development.
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5年前 |
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Michael Schloh von Bennewitz
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c0aa16f26e
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Resolve #35 add a board to board connector to prepare daughterboards.
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5年前 |
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Michael Schloh von Bennewitz
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f7c398852a
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Resolve #33 Align panel to Stencil8 by relocating mount holes slightly.
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5年前 |
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Michael Schloh von Bennewitz
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04d94df71d
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Avoid tracking manufacturing archives and selectively copy to releases.
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5年前 |
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Michael Schloh von Bennewitz
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0a3fb0548d
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Resolve #21 publish a bill of materials, in draft without suppliers.
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5年前 |
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Michael Schloh von Bennewitz
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9ef3094d39
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Resolve #32 include missing footprints by adding shaded models.
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5年前 |
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Michael Schloh von Bennewitz
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6c7b76d799
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Bump hardware revision number pending milestone progress and test cycle.
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5年前 |
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Michael Schloh von Bennewitz
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d07d09c41a
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Increase parts count to 124, and connect all remaining circuits.
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5年前 |
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Michael Schloh von Bennewitz
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15d9f44faf
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Regenerate the netlist after introducing solder jumpers for antennas.
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5年前 |
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Michael Schloh von Bennewitz
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b657eb2ec5
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Add solder switch symbols for use in new antenna decoupling from switch.
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5年前 |
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Michael Schloh von Bennewitz
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7229a08eed
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Add solder jumpers to decouple antenna array from transceiver switch.
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5年前 |
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Michael Schloh von Bennewitz
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772f799d43
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Connect power voltage and ground to bottom quarter of board parts.
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5年前 |
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Michael Schloh von Bennewitz
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b7623201ba
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Dump layout regeneration after trying to design new test points.
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5年前 |
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Michael Schloh von Bennewitz
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2fa32f80c2
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Add test points to allow flexible postassembly prototype debugging.
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5年前 |
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Michael Schloh von Bennewitz
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4a6fe14ba6
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Apply copper pours to all layers with ground nets except on layer 3.
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5年前 |
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Michael Schloh von Bennewitz
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2aa746b314
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Add logos to schematic, that unfortunately do not fit in the layout.
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5年前 |
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Michael Schloh von Bennewitz
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dc6f024b36
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Remove pad to pad spacing tolerance error to almost completely correct.
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5年前 |
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Michael Schloh von Bennewitz
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4a041e91f9
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Clean up vias, tracks, spacing, and remove redundant segments.
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5年前 |
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Michael Schloh von Bennewitz
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fe06fd495f
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Adjust track width, via drills, and annular rings to minimum specs.
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5年前 |
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Michael Schloh von Bennewitz
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50ca6fbb0b
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Connect remaining USB data and UART data circuits for input output.
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5年前 |
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Michael Schloh von Bennewitz
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dca0d14ff0
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Correct flawed net in cross connected serial wire debug contacts.
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5年前 |
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Michael Schloh von Bennewitz
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7cadc14d8f
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Connect both LEDs to MCU pins for controlling user output.
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5年前 |
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Michael Schloh von Bennewitz
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b639be76b3
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Complete draft revision of the radio frequency switch circuit.
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5年前 |
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Michael Schloh von Bennewitz
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2063328cb1
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Remove useless chip antenna which takes up more area than total size.
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5年前 |
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Michael Schloh von Bennewitz
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b1fa69de4a
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Replace coin cell battery holder and move crystal to make room.
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5年前 |
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Michael Schloh von Bennewitz
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6daad3ba72
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Complete most circuits pending layout of RF switch and passive arrays.
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5年前 |
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Michael Schloh von Bennewitz
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53362e2b0c
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Upload intermediate layout design with most decapsulation circuits.
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5年前 |
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Michael Schloh von Bennewitz
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8d28560c4e
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Tighten tolerances to highest four layer ENIG cheap fabrication capacity.
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5年前 |
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Michael Schloh von Bennewitz
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7519f8f491
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Adjust ball pad clearance and solder mask aperature to allow sanity.
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5年前 |
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Michael Schloh von Bennewitz
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802ec1d175
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Reflect corrections in power circuits and generally develop layout.
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5年前 |
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Michael Schloh von Bennewitz
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cc5a03834a
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Correct power circuit in LED parts that require a power flag.
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5年前 |
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Michael Schloh von Bennewitz
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636ecc14e6
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Correct flawed ground short in secure element authentication circuit.
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5年前 |
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Michael Schloh von Bennewitz
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8da9ab17c4
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Correct electrical connection to chip and loop antenna symbol.
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5年前 |
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Michael Schloh von Bennewitz
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eedb5cdd42
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Improve mounting hole unit numbering by hand modifying identifiers.
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5年前 |
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Michael Schloh von Bennewitz
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2efab65f8a
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Add nested part to allow either DFN or SOIC secure elements to be used.
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5年前 |
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Michael Schloh von Bennewitz
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9364408811
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Correct footprint for Atmel secure element to comply with standards.
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5年前 |
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Michael Schloh von Bennewitz
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36323d05c0
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Improve tab text and position of mouse bites pending part placements.
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5年前 |
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Michael Schloh von Bennewitz
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0d1eed7fcb
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Reduce and (prototype) panelise for format change from badge to hat.
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5年前 |
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Michael Schloh von Bennewitz
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57d2b72b53
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Add test point loops and correct sized mounting holes.
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5年前 |
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Michael Schloh von Bennewitz
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2a1cbb6ddb
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Add nested part to allow either DFN or SOIC EEPROMs to be used.
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5年前 |
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Michael Schloh von Bennewitz
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b4e7cd354f
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Merge branch 'master' of git.europalab.com:NLNetfound/dsendcomm
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5年前 |
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Michael Schloh von Bennewitz
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f779b7999a
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Adapt layers and tolerances to correspond with four layer qualities.
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5年前 |
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Michael Schloh von Bennewitz
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aea4480af7
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Hide copper antenna surface underneath soldermask instead of plating it.
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5年前 |
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Michael Schloh von Bennewitz
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69acaf3e33
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Add EEPROM, jumpers, and connector pending migration to hat format.
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5年前 |
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Michael Schloh von Bennewitz
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9bfa087f15
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Add an explanation about why the project lacks software.
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5年前 |
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Michael Schloh von Bennewitz
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f562757082
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Initialise a explanation for the lack of project software.
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5年前 |
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Michael Schloh von Bennewitz
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54e8c2e73c
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Correct schematics after electric rules check results in warnings.
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5年前 |
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Michael Schloh von Bennewitz
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0b9e714c81
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Update library cache to most recent changes and add forgotten netlist.
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5年前 |
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Michael Schloh von Bennewitz
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a88a134751
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Update existing schematics after modification and subsequent reannotation.
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5年前 |
