 Michael Schloh von Bennewitz
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7af8ba97f5
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Improve fiducial size, form, placement, and structure to resolve #145.
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4年前 |
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Michael Schloh von Bennewitz
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eb74067f05
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Add test points for USB data quality assurance (especially type C.)
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4年前 |
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Michael Schloh von Bennewitz
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a2e76541c1
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Remove MPLab Snap because it fails on all Opensource (GDB) applications.
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4年前 |
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Michael Schloh von Bennewitz
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c7e1804622
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Add MPLab Snap and STLink V3Mini devices as candidate programmers.
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4年前 |
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Michael Schloh von Bennewitz
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d6f0deb432
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Increase track widths and reduce (sloppy) vias in RF paths to antennas.
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4年前 |
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Michael Schloh von Bennewitz
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1aa5ae7f55
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Provisionally added chip programmer dimensions and hole spacing.
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4年前 |
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Michael Schloh von Bennewitz
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02bbb27912
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Remove paste from unpopulated chip antenna passive pads and clarify.
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4年前 |
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Michael Schloh von Bennewitz
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50e65f2bcb
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Add mounting holes to the test jig and avoid upside down text in panels.
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4年前 |
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Michael Schloh von Bennewitz
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d8106ebb3a
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Add structures and circuits to support forthcoming test jig construction.
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4年前 |
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Michael Schloh von Bennewitz
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4f9180baf2
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Add configuration for a first revision of the education destined device.
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4年前 |
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Michael Schloh von Bennewitz
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fadea4cfdb
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Add test, debug, and program files for hardware attached on top EEPROM.
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4年前 |
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Michael Schloh von Bennewitz
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70ff0c71ff
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Develop the placement configuration pending assembly of release 0.9.2.
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4年前 |
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Michael Schloh von Bennewitz
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5a29587d8e
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Work on #141 by integrating pi networks to match impedence in antennas.
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4年前 |
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Michael Schloh von Bennewitz
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7927ab7047
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Roughly inform of the code complete and release status pending production.
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4年前 |
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Michael Schloh von Bennewitz
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fd8033c28a
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Import project samples to illustrate hardware features in ARM firmware;
This addition resolves #111 and #112 and concludes milestone group 6.
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4年前 |
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Michael Schloh von Bennewitz
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3b87055112
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Import a sample solution and corresponding logic pending project import.
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4年前 |
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Michael Schloh von Bennewitz
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b5efdccec2
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Clear area pending integration of current set of firmware projects.
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4年前 |
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Michael Schloh von Bennewitz
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b3b668c47c
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Calibrate for tooling update to 0.9.2 and prepare for placments.
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4年前 |
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Michael Schloh von Bennewitz
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c42820dfaa
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Update according to latest state of the SMT assembly lab toolset.
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4年前 |
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Michael Schloh von Bennewitz
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dfae2135e6
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Adjust label spacing slightly on designator text in the silkscreen.
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4年前 |
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Michael Schloh von Bennewitz
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c80ec05067
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Correct electronic design rules check results pending imminent release.
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4年前 |
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Michael Schloh von Bennewitz
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035f934f79
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Repour lost filled areas on all layers, forgotten in last commit.
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4年前 |
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Michael Schloh von Bennewitz
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e71589f739
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Reshape and position the hack that silkscreen indicator bar.
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4年前 |
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Michael Schloh von Bennewitz
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7d0f59100f
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Add forgotten but used in layout replacement for cut holes a module.
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4年前 |
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Michael Schloh von Bennewitz
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898da4fa7c
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Regenerate portable document format schematic capture for update.
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4年前 |
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Michael Schloh von Bennewitz
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f143228cb3
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Selectively remove paste apertures and replace hole cuts with drills.
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4年前 |
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Michael Schloh von Bennewitz
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8e9ea6370a
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Generate and curate parts list, panel design, and stencil foil.
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4年前 |
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Michael Schloh von Bennewitz
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3ba5b2870f
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Add out of tree footprint module files for inclusion in manufacturing.
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4年前 |
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Michael Schloh von Bennewitz
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9702fcfc69
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Improve name text of artist signature which was too long before.
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4年前 |
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Michael Schloh von Bennewitz
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719e193c1b
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Add a 45mm large mousebite panel tab to accommodate enclosure hinges.
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4年前 |
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Michael Schloh von Bennewitz
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9f370cd029
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Annotate J5 and J20 according to their serial protocols in silkscreens.
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4年前 |
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Michael Schloh von Bennewitz
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3dfc431d97
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Mark the first JTAG SWD debug interface connector in the silkscreen.
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4年前 |
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Michael Schloh von Bennewitz
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7d49528ff2
|
Reflect information from bug reports #129 and #130 pending VNA tests.
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4年前 |
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Michael Schloh von Bennewitz
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f2ad7f7ead
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Remove stray user drawing layer of a edge cut guidance horizontal bar.
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4年前 |
 Michael Schloh von Bennewitz
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f4a7a6cc9f
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Bump version numbers pending panelisation and prepare to manufacture.
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4年前 |
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Michael Schloh von Bennewitz
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4f3db6f44a
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Correct USB bus power circuit according to reference design and adjust.
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4年前 |
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Michael Schloh von Bennewitz
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8eebf51cfb
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Adjust position of external display connection cutout on board bottom.
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4年前 |
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Michael Schloh von Bennewitz
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6040ddcdfa
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Add holes for hackfield, antenna legend, and correct enclosure hinges.
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4年前 |
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Michael Schloh von Bennewitz
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5bf1b6c077
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Refine calibration suggestion from 12pF to 15pF indicated by counter.
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4年前 |
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Michael Schloh von Bennewitz
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c4e91a8557
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Update parts list according to recent corrections in schematic capture.
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4年前 |
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Michael Schloh von Bennewitz
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98b1e69d93
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Correct version number as indicated in silkscreen text.
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4年前 |
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Michael Schloh von Bennewitz
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1c8ea4862a
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Implement design review suggestions to resolve #61 and #62.
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4年前 |
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Michael Schloh von Bennewitz
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73a6ed98bc
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Add a test point to allow LSE crystal output redirection to a MCU pin.
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4年前 |
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Michael Schloh von Bennewitz
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95df65933d
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Resolve #128 by rerouting bus power to PA07 F3 to bus test circuit.
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4年前 |
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Michael Schloh von Bennewitz
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e14d4526eb
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Calibrate crystal circuits by trial and error pending spectrum analysis.
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4年前 |
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Michael Schloh von Bennewitz
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799c6fe772
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Calibrate crystal circuits by trial and error pending spectrum analysis.
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4年前 |
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Michael Schloh von Bennewitz
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1f2fe604d8
|
Connect pads from pogo pin test matrix to GND and 3V3 to future proof.
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4年前 |
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Michael Schloh von Bennewitz
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afa5216e09
|
Resolve #122 by removing AE7 and JP10 from the layout, and add a PWR LED.
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4年前 |
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Michael Schloh von Bennewitz
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d772d2f788
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Resolve #83 after tests indicate MLS correctly supplies power from PA09.
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4年前 |
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Michael Schloh von Bennewitz
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a6fcbdf613
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Resolve bug report #118 by replacing 10pF with 7pF load capacitors.
|
4年前 |
