 Michael Schloh von Bennewitz
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9ff259eef9
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Prepare to import a devtree fragment and new EEPROM logic for GPIO resets.
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4年前 |
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Michael Schloh von Bennewitz
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b07955925c
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Increment date year numbers to correspond with the current year 2021.
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4年前 |
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Michael Schloh von Bennewitz
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049fd1d2fa
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Backport decrease of luminosity modification for D3/R40 power LED pair.
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4年前 |
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Michael Schloh von Bennewitz
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ea19d4720a
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Increment identifiers to indicate the new year after the spring festival.
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4年前 |
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Michael Schloh von Bennewitz
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4b34cb33cb
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Fix false inclusion bug and decrudify poorly formatted source lines.
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4年前 |
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Michael Schloh von Bennewitz
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bb6402bbd6
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Resolve #174 by replacing and modifying logic according to another model.
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4年前 |
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Michael Schloh von Bennewitz
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2beb1f6ca3
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Resolve #175 by including recommended antenna models in the parts list.
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4年前 |
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Michael Schloh von Bennewitz
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fb799c1632
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Modify antenna modification text to at least include jumper numbers.
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4年前 |
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Michael Schloh von Bennewitz
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df1e5480bb
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Resolve #67 by reviewing parts in stock and editing a corresponding legend.
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4年前 |
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Michael Schloh von Bennewitz
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ef09d61643
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Replace 1K value with 2K4 for R40 to dim power indicator LED D3.
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4年前 |
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Michael Schloh von Bennewitz
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66cc2e4438
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Remove paste on DNP R41, backout 8819d77 15/18pF, and correct placements.
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4年前 |
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Michael Schloh von Bennewitz
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b8fb9b9d94
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Assign feeders and chiplist to nozzle matrix and deselect dev model parts.
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4年前 |
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Michael Schloh von Bennewitz
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b9f6f61168
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Add capacitor and inductor value modifications for integrated pi network.
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4年前 |
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Michael Schloh von Bennewitz
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d56f6cc9e4
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Complete HSE adjustment specification of load capacitors in the parts list.
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4年前 |
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Michael Schloh von Bennewitz
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8819d778aa
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Resolve #123 by replacing C94 and C95 values with 18pF following analysis.
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4年前 |
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Michael Schloh von Bennewitz
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4e84bae6b9
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Modify second crystal load capacitance following spectrum analysis.
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4年前 |
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Michael Schloh von Bennewitz
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39e7dba495
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Configure the panel first chip positions and many feeder corrections.
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4年前 |
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Michael Schloh von Bennewitz
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ef19061f70
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Consider the problem of false tag indexes when releasing past tense.
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4年前 |
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Michael Schloh von Bennewitz
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76f8fc95be
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Partially resolve #55 by reducing vias and severed traces in the RF path.
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4年前 |
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Michael Schloh von Bennewitz
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af5147cf78
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Correct superfluous placeholder entry (remaining after consolidation.)
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4年前 |
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Michael Schloh von Bennewitz
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9f10c7d742
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Configure the tape reel positions and their feed box mappings.
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4年前 |
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Michael Schloh von Bennewitz
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89e932a840
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Solve the problem causing a layout error (79794b0) in the part footprint.
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4年前 |
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Michael Schloh von Bennewitz
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79794b0a07
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Correct the mask clearance for the RF switch causing a paste problem.
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4年前 |
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Michael Schloh von Bennewitz
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6341ccec33
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Adjust placement configuration to reflect ferrite bead consolidation.
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4年前 |
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Michael Schloh von Bennewitz
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8c2fc0481e
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Replace tape feeders and regenerate following ferrite bead consolidation.
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4年前 |
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Michael Schloh von Bennewitz
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bd529efcb4
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Modify and consolidate both ferrite beads according to manufacturer advice.
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4年前 |
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Michael Schloh von Bennewitz
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b91f6a00b8
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Regenerate foil apertures to match panel corrections near J4 connector.
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4年前 |
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Michael Schloh von Bennewitz
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e308d27de8
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Improve comment describing the backpowering function of FB2 and JP7.
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4年前 |
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Michael Schloh von Bennewitz
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72c593b8f8
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Recorrect format from PDF to Gerber RS-274X and repaint pour hatches.
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4年前 |
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Michael Schloh von Bennewitz
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8e0ade7765
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Recorrect panelised format when plotting Gerber and Excellon archives.
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4年前 |
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Michael Schloh von Bennewitz
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b576aba216
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Inform of imminent release and record revision numbers of releases.
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4年前 |
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Michael Schloh von Bennewitz
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9da63878d4
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Record a release engineering checklist for reasons of quality assurance.
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4年前 |
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Michael Schloh von Bennewitz
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63af4224c6
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Reconfigure automated placer configuration pending release to manufacturing.
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4年前 |
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Michael Schloh von Bennewitz
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88d7d2197e
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Include layout plots in addition to schematic and parts list of type PDF.
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4年前 |
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Michael Schloh von Bennewitz
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991ad27237
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Regenerate portable document format schematic capture for release.
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4年前 |
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Michael Schloh von Bennewitz
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e55d772e7e
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Modify SWDCLK route between programming connectors to satisfy fabricator.
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4年前 |
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Michael Schloh von Bennewitz
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daa7f7c387
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Reconnect solderfield pads and satisfy board fabricator trace to hole.
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4年前 |
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Michael Schloh von Bennewitz
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44f662eb77
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Correct the target output directory path to correspond with panels.
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4年前 |
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Michael Schloh von Bennewitz
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9afc5ee2ca
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Correct the target output directory path to correspond with foils.
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4年前 |
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Michael Schloh von Bennewitz
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2287982aa1
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Improve descriptive text on prototype assembly frame top layer.
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4年前 |
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Michael Schloh von Bennewitz
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659c316ae0
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Bump revision numbers, dates, and copyright pending release to manufacturing.
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4年前 |
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Michael Schloh von Bennewitz
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409d07abe1
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Redesign panel and foil for board fabrication after adding via stiching.
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4年前 |
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Michael Schloh von Bennewitz
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a64db6a94c
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Make a intermediate commit to track the panel design with custom planes.
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4年前 |
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Michael Schloh von Bennewitz
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68bb4141e3
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Add via stiching to more closely resemble the antenna datasheet reference.
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4年前 |
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Michael Schloh von Bennewitz
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0904bbdda6
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Resolve #31 by adding via stiching to feed lines, pending RF tests.
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4年前 |
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Michael Schloh von Bennewitz
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d94aab0e8a
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Update to state of panel pending 0.9.4 release to board fabrication.
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4年前 |
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Michael Schloh von Bennewitz
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b3ffb6c035
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Correct spelling of unique parts and regenerate portable document format.
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4年前 |
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Michael Schloh von Bennewitz
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a36d54c0dc
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Update panel design pending release of 0.9.4 to board fabrication.
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4年前 |
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Michael Schloh von Bennewitz
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234e679a69
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Correct misaligned trace on board edge and oversized trace near cutout.
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4年前 |
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Michael Schloh von Bennewitz
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12b319a7de
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Resolve #167 by including a EEPROM device tree entry for J3 pin 37.
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4年前 |
