# Capacitor C18-19 values are wrong ## Problem environment The low speed external (LSE) crystal load capacitance is fixed but the stray capacitance is not, and our board adds more capacitance than is reflected in the schematic. ## Steps to reproduce 1. Use a oscilloscope 1. Test the LSE frequency ## Expected result The LSE frequency (according to load capacitance and C18/C19 is exactly the specified value. ## Actual result The LSE frequency is so wrong, that DFLL and DPLL clocks cannot synchronise to it. ## Severity level This is **high priority** because the MCU clocks fail to lock and program execution is accordingly corrupted.

Resolved in a6fcbdf.