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#118 Capacitor C18-19 values are wrong

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opened 3 years ago by Michael Schloh von Bennewitz · 1 comments
Michael Schloh von Bennewitz commented 3 years ago

Capacitor C18-19 values are wrong

Problem environment

The low speed external (LSE) crystal load capacitance is fixed but the stray capacitance is not, and our board adds more capacitance than is reflected in the schematic.

Steps to reproduce

  1. Use a oscilloscope
  2. Test the LSE frequency

Expected result

The LSE frequency (according to load capacitance and C18/C19 is exactly the specified value.

Actual result

The LSE frequency is so wrong, that DFLL and DPLL clocks cannot synchronise to it.

Severity level

This is high priority because the MCU clocks fail to lock and program execution is accordingly corrupted.

# Capacitor C18-19 values are wrong ## Problem environment The low speed external (LSE) crystal load capacitance is fixed but the stray capacitance is not, and our board adds more capacitance than is reflected in the schematic. ## Steps to reproduce 1. Use a oscilloscope 1. Test the LSE frequency ## Expected result The LSE frequency (according to load capacitance and C18/C19 is exactly the specified value. ## Actual result The LSE frequency is so wrong, that DFLL and DPLL clocks cannot synchronise to it. ## Severity level This is **high priority** because the MCU clocks fail to lock and program execution is accordingly corrupted.
Michael Schloh von Bennewitz added the
bug
label 3 years ago
Michael Schloh von Bennewitz added this to the Layout design milestone 3 years ago
Michael Schloh von Bennewitz modified the milestone from Layout design to Final schematic and layout design 3 years ago
Michael Schloh von Bennewitz commented 3 years ago
Owner

Resolved in a6fcbdf.

Resolved in a6fcbdf.
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